KR20130129883A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device with an improved texture stabilization speed is provided. The liquid crystal display device includes: a first insulation substrate; a pixel electrode which is arranged on the first insulation substrate and is divided by a plurality of domain forming units; a pixel electrode insulating layer which is arranged on the pixel electrode; and a control electrode which is arranged on the pixel electrode insulating layer between the domain forming units to be insulated from the pixel electrode.

Description

[0001] Liquid crystal display [0002]

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among them, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal is arranged perpendicular to the upper and lower display panels without an electric field applied to the display device has a high contrast ratio and easy to implement a wide reference viewing angle. Vertical alignment mode As a means for realizing a wide viewing angle in a liquid crystal display, there is a method of disposing a domain forming means such as a gap or protrusion on the field generating electrode.

On the other hand, the liquid crystal display device having a gap between both the upper and lower display panels is vulnerable to static electricity and align misses, so that a pattern is formed only on the lower display panel and the pattern is not formed on the upper display panel. Patternless VA mode liquid crystal display devices have been studied. However, the patternless VA mode liquid crystal display also has a problem in that texture occurs at the boundary of a domain.

In order to control this, a method of arranging a separate control electrode (DCE) on the pixel electrode has been studied, but this also has a problem in that the texture is not easily stabilized.

Therefore, it is necessary to improve the stabilization speed of the texture.

An object of the present invention is to provide a liquid crystal display device having improved texture stabilization speed.

Technical problems of the present invention are not limited to the above-mentioned technical problems, other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a first insulating substrate, a pixel electrode disposed on the first insulating substrate, and partitioned by a plurality of domain forming means; And a pixel electrode insulating film disposed on the pixel electrode, and a control electrode disposed on the pixel electrode insulating film between the plurality of domain forming means so as to be insulated from the pixel electrode, and having a plurality of notches.

The details of other embodiments are included in the detailed description and drawings.

As described above, according to the liquid crystal display according to the exemplary embodiments, there are one or more of the following effects.

First, by including the notch in the control electrode it is possible to quickly stabilize the texture formed on the control electrode.

Second, when the control electrode is disposed above the pixel electrode, the texture can be stabilized quickly even if the thickness of the pixel electrode insulating film is formed thin.

Third, when the control electrode is disposed above the pixel electrode, the aperture ratio can be improved.

1 is a layout view of a thin film transistor array panel included in a liquid crystal display according to a first exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line AA ′ of the thin film transistor array panel of FIG. 1.
3 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line B-B ′ of the thin film transistor array panel of FIG. 1.
4 is a partially enlarged view of a control electrode having a notch included in the liquid crystal display according to the first exemplary embodiment of the present invention.
FIG. 5 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line CC ′ of the thin film transistor array panel of FIG. 1.
6A to 7B are photographs comparing the texture generation degree of the liquid crystal display according to the first exemplary embodiment of the present invention including the notch with no notch.
8 is a layout view of a thin film transistor array panel included in a liquid crystal display according to a second exemplary embodiment of the present invention.
FIG. 9 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line D-D ′ of the thin film transistor array panel of FIG. 8.
10 is a layout view of a thin film transistor array panel included in a liquid crystal display according to a third exemplary embodiment of the present invention.
FIG. 11 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line E-E ′ of the thin film transistor array panel of FIG. 10.
12 is a layout view of a thin film transistor array panel included in a liquid crystal display according to a fourth exemplary embodiment of the present invention.
FIG. 13 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line F-F ′ of the thin film transistor array panel of FIG. 12.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation.

Hereinafter, a liquid crystal display according to a first exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a layout view of a thin film transistor array panel included in a liquid crystal display according to a first exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line AA ′ of the thin film transistor array panel of FIG. 1.

The liquid crystal display according to the present exemplary embodiment includes a thin film transistor array panel 100 and a common electrode panel 200 disposed to face each other, and a liquid crystal layer 300 interposed between the two display panels 100 and 200.

1 and 2, both the color filter 130, the pixel electrode 82, and the like may be formed in the thin film transistor array panel 100 included in the liquid crystal display of the present exemplary embodiment. The liquid crystal display according to the present exemplary embodiment has an array on color filter (AOC) structure in which a thin film transistor array such as a gate wiring is formed on the color filter 130, or a color filter on in which the color filter 130 is formed on the thin film transistor array. Array) structure, but for convenience, a liquid crystal display device having an AOC structure will be described as an example.

In the thin film transistor array panel 100 of the AOC structure liquid crystal display device, a black matrix 120 is formed directly on the first insulating substrate 10 to define a pixel area and prevent light leakage to improve image quality. For example, the black matrix 120 may be formed of a metal (metal oxide) such as chromium (Cr) or chromium oxide, or an organic black resist. The black matrix 120 may be formed to overlap the gate and / or data line to maximize the aperture ratio.

Red, green, and blue color filters 130 are sequentially arranged in the pixel area defined by the black matrix 120. These color filters 130 serve to pass only light of a specific wavelength band.

The color filter 130 may be formed of a photosensitive organic material, for example, a photoresist. These color filters 130 may be formed to have the same thickness or may have a predetermined step.

An overcoat layer 135 may be formed on the color filter 130 to planarize these steps.

On the overcoat layer 135, for example, a gate line 22 extending in the horizontal direction and transmitting a gate signal is formed. The gate lines 22 are allocated one for one pixel. The gate line 22 is provided with a pair of protruding first and second gate electrodes 26a and 26b. The gate line 22 and the first and second gate electrodes 26a and 26b are referred to as gate wirings.

In addition, the storage wirings 28 extending in the horizontal direction substantially parallel to the gate lines 22 are formed on the first insulating substrate 10. The storage wiring 28 is formed to overlap a part of the pixel electrode 82 to be described later in the pixel. In the present embodiment illustrated in FIG. 1, the storage wiring 28 is disposed at the center of the pixel. However, the present invention is not limited thereto, and the storage wiring 28 overlaps the pixel electrode 82 so that a constant storage capacitance is obtained. The shape and arrangement of the storage wiring 28 may be modified in various forms within a range that satisfies the conditions for forming the).

The gate wirings 22, 26a and 26b and the storage wiring 28 include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper (Cu) and copper alloys, and the like. It may be made of a copper-based metal, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta). In addition, the gate wirings 22, 26a, and 26b and the storage wiring 28 may have a multilayer structure including two conductive films (not shown) having different physical properties. One of these conductive films is a low resistivity metal such as aluminum-based metal, silver-based metal, or copper to reduce signal delay or voltage drop in the gate wirings 22, 26a, 26b and storage wiring 28. It is made of a series metal and the like. Alternatively, the other conductive film may be made of a material having excellent contact properties with other materials, particularly ITO (indium tin oxide) and IZO (indium zinc oxide), such as molybdenum metal, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film, an aluminum top film, an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate wirings 22, 26a and 26b and the storage wiring 28 may be made of various metals and conductors.

A gate insulating film 30 made of silicon nitride (SiNx), silicon oxide (SiOx), or the like is formed on the gate wirings 22, 26a and 26b and the storage wiring 28.

A pair of semiconductor layers 40a and 40b made of hydrogenated amorphous silicon, polycrystalline silicon, or the like are formed on the gate insulating film 30. The semiconductor layers 40a and 40b may have various shapes, such as island shapes and linear shapes. For example, the semiconductor layers 40a and 40b may be formed in island shapes on the gate electrodes 26a and 26b as shown in FIG. 1. In another embodiment of the present invention, when the semiconductor layers 40a and 40b are linearly formed, the semiconductor layers 40a and 40b may be disposed below the first and second data lines 62a and 62b to extend above the gate electrodes 26a and 26b. It may have a shape.

On the semiconductor layers 40a and 40b, ohmic contact layers 55a and 56a made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration. 56b) are formed respectively. The ohmic contact layers 55a and 56a may have various shapes, such as islands and linear shapes. For example, when the ohmic contact layers 55a and 56a are island types, the ohmic contact layers 55a and 56a may be island shapes. 56a may be located under the drain electrode 66a and the source electrode 65a. In addition, in another embodiment of the present invention, when the ohmic contact layer is linear, the ohmic contact layer may be formed to extend below the first and second data lines 62a and 62b.

First and second data lines 62a and 62b and first and second drain electrodes 66a and 66b are formed on the ohmic contact layers 55a and 56a and the gate insulating layer 30. The first and second data lines 62a and 62b extend in parallel to each other, for example, in a vertical direction, and cross the gate line 22 to define pixels. The first and second data lines 62a and 62b are connected to first and second source electrodes 65a and 65b extending from the branch to the top of the semiconductor layers 40a and 40b. . The first and second drain electrodes 66a and 66b are separated from the first and second source electrodes 65a and 65b, respectively, and the first and second source electrodes 65a and 26b are formed around the gate electrodes 26a and 26b, respectively. It is located above the semiconductor layers 40a and 40b so as to face 65b).

The first drain electrode 66a is connected to the pixel electrode 82 through the first contact hole 76a, and the second drain electrode 66b is connected to the control electrode 182 through the second contact hole 76b. The voltages applied from the first and second data lines 62a and 62b are transferred to the pixel electrode 82 and the control electrode 182, respectively.

The first and second data lines 62a and 62b, the first and second source electrodes 65a and 65b, and the first and second drain electrodes 66a and 66b are referred to as first and second data lines.

The data lines 62, 65, and 66 are preferably made of refractory metals such as chromium, molybdenum-based metals, tantalum, and titanium, and include a lower layer (not shown) such as a refractory metal and an upper layer of low resistance material (not shown). It may have a multilayer film structure consisting of a). Examples of the multilayer structure include a triple layer of a molybdenum film-aluminum film-molybdenum film in addition to the chromium lower film and the aluminum upper film or the aluminum lower film and the molybdenum upper film.

The first and second source electrodes 65a and 65b overlap at least a portion of the semiconductor layers 40a and 40b, and the first and second drain electrodes 66a and 66b are formed around the gate electrodes 26a and 26b. The first and second source electrodes 65a and 65b face each other and at least partially overlap the semiconductor layers 40a and 40b. Here, the ohmic contact layers 55a and 56a may include the semiconductor layers 40a and 40b, the first and second source electrodes 65a and 65b, and the semiconductor layers 40a and 40b and the first and second drain electrodes 66a and Interposed between 66b) to lower the contact resistance therebetween.

A passivation layer 70 made of an insulating layer is formed on the first and second data lines 62a and 62b, the first and second drain electrodes 66a and 66b, and the exposed semiconductor layers 40a and 40b. Here, the protective layer 70 may be formed of an inorganic material such as silicon nitride or silicon oxide, an organic material having excellent planarization characteristics and photosensitivity, or an a-Si: C: O (silicon oxide) film formed by plasma enhanced chemical vapor deposition (PECVD) , a-Si: O: F, or the like. The protective layer 70 may have a bilayer structure of a lower inorganic layer and an upper organic layer to protect the exposed semiconductor layers 40a and 40b while making good use of the organic layer.

In the passivation layer 70, first and second contact holes 76a and 76b exposing the first and second drain electrodes 66a and 66b, respectively, are formed.

On the passivation layer 70, a pixel electrode 82 electrically connected to the first drain electrode 66a is formed in each pixel through the first contact hole 76a. That is, the pixel electrode 82 is physically and electrically connected to the first drain electrode 66a through the first contact hole 76a to receive a data voltage from the first drain electrode 66a. The pixel electrode 82 is made of a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The pixel electrode 82 is partitioned by a plurality of domain forming means 83. The domain forming means 83 may be, for example, a gap formed by patterning the pixel electrode 82, but may also be a protrusion shape, but is not limited thereto.

As shown in FIG. 1, the domain forming means 83 has a horizontal portion formed in a horizontal direction at a position that half-divides the pixel electrode 82 up and down, and diagonally in upper and lower portions of the half-divided pixel electrode 82, respectively. It includes an oblique portion formed by. Here, the upper and lower diagonal portions are perpendicular to each other to distribute the horizontal electric field evenly in four directions. The diagonal portion includes a portion that is substantially 45 ° to the gate line 22 and a portion that is -45 °, and the domain forming means 83 is upper with respect to a line (parallel with the gate line) that bisects the pixel area up and down. And a structure in which the lower portion is substantially mirror symmetric. For example, as shown in FIG. 1, an oblique portion of the domain forming means 83 that is substantially 45 ° with the gate line 22 is formed in the pixel electrode 82 positioned above the center of the pixel. An oblique portion of the domain forming means 83 that is substantially -45 ° with the gate line 22 may be formed in the pixel electrode 82 positioned below the center of the gate electrode 22. However, the present invention is not limited thereto, and the shape and arrangement of the diagonal portion of the domain forming means 83 may be in various forms in a range in which the diagonal portion of the domain forming means 83 is substantially 45 ° or −45 ° with the gate line 22. It can be modified.

When the domain forming means 83 of the pixel electrode 82 and the control electrode 182 described later are used, the display area of the pixel electrode 82 is the liquid crystal included in the liquid crystal layer 300 (see 310 in FIG. 5). The main director of is divided into a number of domains according to the direction in which the electric field is arranged. Here, the domain refers to a region formed of liquid crystals in which the directors of the liquid crystals are inclined in a specific direction by an electric field formed between the pixel electrode 82 and the common electrode 140.

A voltage for driving the liquid crystal display is applied to the pixel electrode 82, and a voltage lower than the voltage of the control electrode 182, which will be described later, is preferably applied.

Hereinafter, an insulating film, a control electrode, a vertical alignment layer, and a common electrode display panel included in the liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 3. 3 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line B-B ′ of the thin film transistor array panel of FIG. 1.

1 and 3, a pixel electrode insulating layer 170 is formed on the pixel electrode 82.

The pixel electrode insulating layer 170 may be made of an inorganic material such as silicon nitride or silicon oxide or an organic material such as acrylic resin. The pixel electrode insulating layer 170 is disposed between the control electrode 182 and the pixel electrode 82 to prevent the two electrodes 82 and 182 from being shorted. Since the pixel electrode insulating layer 170 is for preventing a short circuit between the pixel electrode 82 and the control electrode 182, the pixel electrode insulating layer 170 may be formed as thin as possible with a thickness of 5 to 200 nm as long as the short circuit can be prevented. It is preferable. The pixel electrode insulating layer 170 of the present exemplary embodiment is formed on the pixel electrode 82 and the passivation layer 70 so as to cover the entire surface of the first insulating substrate 10. Accordingly, the process of patterning the pixel electrode insulating layer 170 is not required, so that an increase in process time can be minimized.

The control electrode 182 is disposed on the pixel electrode insulating layer 170 and insulated from the pixel electrode 82. The control electrode 182 includes a horizontal portion that is formed in the horizontal direction at a position that divides the pixel electrode 82 up and down, and an oblique portion that is formed in the diagonal direction on the upper and lower portions of the half divided pixel electrode 82, respectively. . In this specification, the control electrode 182 generally means an oblique portion. The control electrode 182 is disposed between the plurality of domain forming means 83 and preferably positioned at the center of the pixel electrode 82 positioned between the domain forming means 83 adjacent to each other. Specifically, it is preferable that the diagonal portions of the domain forming means 83 and the diagonal portions of the control electrode 182 are alternately arranged at substantially equal intervals.

The control electrode 182 is made of the same transparent conductor as the pixel electrode 82. Accordingly, even if the separate control electrode 182 is disposed on the pixel electrode 82, the aperture ratio of the liquid crystal display is not reduced. However, in order to minimize the area where the texture is generated, the control electrode 182 may have a width of 1 to 12 μm (see W _{1 in} FIG. 5).

The control electrode 182 is connected to the second drain electrode 66b through the second contact hole 76b. The voltage applied from the second data line 62b is transferred to the control electrode 182 via the second source electrode 65b and the second drain electrode 66b. Since the pixel electrode 82 is also cut at a portion where the second contact hole 76b is formed, the pixel electrode 82 and the control electrode 182 are not electrically connected to each other. The voltage applied from the second data line 62b to the control electrode 182 is higher than the voltage applied from the first data line 62a to the pixel electrode 82. For example, the voltage applied to the pixel electrode 82 may be 6V, the voltage applied to the control electrode may be 8V, and the voltage difference between the two electrodes may be controlled as soon as the texture is described later, so that the texture is transferred to the pixel electrode 82. It is preferably about 2V to prevent the transition.

A first vertical alignment layer 92 may be formed on the control electrode 182 and the pixel electrode insulating layer 170 according to the present exemplary embodiment. The first vertical alignment layer 92 orients the liquid crystals vertically together with the second vertical alignment layer 152. Accordingly, when the driving voltage is not applied to the liquid crystal display, a clear black color is implemented in the liquid crystal display. The first vertical alignment layer 92 may be formed of a material including, for example, polyimide as a main chain and a side chain.

A polarizing plate (not shown) may be formed on the first insulating substrate 10. In more detail, the polarizer may be formed on the first insulating substrate 10 on the surface opposite to the surface on which the pixel electrode 82 or the like is formed. The polarization axes of the polarizing plates formed on the first insulating substrate 10 are perpendicular to the polarization axes of the polarizing plates formed on the second insulating substrate 110.

The common electrode display panel 200 includes a common electrode 140 formed on the second insulating substrate 110 and not patterned, and is disposed to face the thin film transistor array panel 100. The common electrode 140 of this embodiment is not patterned. Since the process for patterning the common electrode 140 is not required for the common electrode display panel 200 according to the present exemplary embodiment, misalignment may be prevented from occurring when the thin film transistor array panel 100 and the common electrode display panel 200 are assembled. It does not need to be anti-static treatment, the transmittance is high and the manufacturing cost can be reduced.

A second vertical alignment layer 152 that vertically aligns the liquid crystals is formed on the common electrode 140. A spacer may be interposed between the thin film transistor array panel 100 and the common electrode panel 200 to maintain a cell gap, which is a gap between the two display panels.

On the second insulation substrate 110, a polarizer may be disposed on a surface opposite to a surface on which the common electrode 140 is formed, which is perpendicular to the polarization axis of the polarizer formed on the first insulating substrate 10.

The liquid crystal layer 300 formed from the liquid crystal 310, the UV curable monomer, and the UV curing initiator is interposed between the thin film transistor array panel 100 and the common electrode display panel 200 facing each other.

The liquid crystal 310 included in the liquid crystal layer 300 may have negative dielectric anisotropy, and may be, for example, the nematic liquid crystal 310. The UV curable monomer may be, for example, an acrylate-based monomer, the initiator for UV curing may be made of a material that can be absorbed in the UV region.

Hereinafter, referring to FIGS. 1, 4, and 5, the control electrodes, notches, and alignment of liquid crystals thereof included in the liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail. 4 is a partially enlarged view of a control electrode having a notch included in the liquid crystal display according to the first exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line CC ′ of the thin film transistor array panel of FIG. 1.

1 and 4, the control electrode 182 may be provided with a plurality of notches 183a and 183b. The notches 183a and 183b are formed along at least one side of the control electrode 182 and may be formed along both sides of the control electrode 182. The notches 183a and 183b may be convex notches 183a protruding from both sides of the control electrode 182 toward the domain forming means 83 or concave notches 183b recessed from both sides of the control electrode 182. The notches 183a and 183b formed on the control electrode 182 may be made of only the convex notches 183a, or may be made of only the concave notches 183b, and the convex notches 183a and the concave notches 183b may be mixed and disposed. have. In this case, the convex notches 183a and the concave notches 183b may be alternately arranged along one or both sides of the control electrode 182. The notches 183a and 183b formed on the oblique portions of one control electrode 182 are preferably formed at intervals L ₁ of 20 to 50 μm along at least one side of the control electrode 182. The notches 183a and 183b formed on one side of the control electrode 182 and the notches 183a and 183b formed on the other side of the control electrode 182 preferably face each other. In the case of a pair of concave notches 183b facing each other, the concave notches 183b may be spaced apart to have a width of 3 to 5 μm W ₂ . In this case, of course, the width W ₁ of the control electrode 182 should be wider than this.

The shapes of the notches 183a and 183b may be polygons such as triangles, squares, rhombuses, or the like, or may be semicircular, but they form singular points (P, Q) to control the orientation of the liquid crystal (see 310 in FIG. 5). As long as it can, it is not limited to such a shape.

Referring to FIG. 4, after the electric field is applied to the pixel electrode 82 and the common electrode (see 140 of FIG. 5), the initial and final arrangements of the liquid crystal (310 of FIG. 5) will be described. By intentionally forming a singular point (P, Q) where the directors of the liquid crystal are gathered in one place on the control electrode 182, the elastic energy of the liquid crystal located near the singular point (P, Q) is largely accumulated to The head arrangement direction A is predetermined.

For example, in the region where the concave notch 183b is formed, a negative singular point P is formed in which the head arrangement direction A of the liquid crystal molecules converges and partially diverges. In the region where the convex notch 183a is formed, a bipolar singularity Q in which the head arrangement direction A of the liquid crystal molecules converges is formed. Accordingly, the concave notches 183b and the convex notches 183a are alternately arranged so that the heads of the liquid crystal molecules disposed at the domain boundary are directed from the negative singular point P to the bipolar singular point Q. The liquid crystal can receive the array driving force B by determining A) in advance. By determining the arrangement direction of the liquid crystal disposed in the domain boundary, that is, the control electrode 182 by the notches 183a and 183b, the arrangement distortion of the liquid crystal molecules at the domain boundary is changed as the application time of the driving voltage elapses. The phenomenon of widening to the inside of the electrode 82 can be suppressed.

Accordingly, the liquid crystals arranged in the control electrode 182 can be stably and regularly arranged through the notches 183a and 183b, so that the textures generated at the domain boundary can be stabilized quickly, and the luminance generated after applying the driving voltage is reduced. It can also stabilize quickly.

Although not shown, the width of the control electrode 182 is preferably formed to decrease or increase in a predetermined direction with respect to a predetermined section in order to more quickly stabilize the texture generated at the domain boundary. For example, the width of the control electrode 182 preferably increases from the concave notch 183b to the convex notch 183a. In this case, an array driving force (B direction) is further directed such that the heads of the liquid crystal molecules are directed from the negative singular point P formed in the concave notch 183b to the bipolar singular point Q formed in the convex notch 183a. It becomes bigger. Accordingly, the liquid crystal molecules disposed in the control electrode 182 may be arranged in a predetermined direction within a shorter time, and the texture may be stabilized at a higher speed.

Referring to FIG. 5, when an electric field is formed in the pixel electrode 82 and the common electrode 140, the liquid crystal 310 has different directions in a plurality of domains formed by the domain forming means 83. However, control is performed between the domain forming means 83 in order to minimize the generation of texture by determining the arrangement direction of the liquid crystal 310 in one domain, that is, in the pixel electrode 82 between the domain forming means 83. The electrode 182 is disposed. Since the voltage higher than the pixel electrode 82 is applied to the control electrode 182 as described above, the upper portion of the control electrode 182 has a higher potential than the upper portion of the other pixel electrode 82, and as a result, the liquid crystal of FIG. 5. An equipotential surface such as a line connecting the 310 is formed. Accordingly, the alignment directions of the liquid crystals 310 on the left and right sides of the control electrode 182 are reversed with respect to the control electrode 182, and the domains in the pixel electrode 82 are bisected to reduce generation of texture.

Since the control electrode 182 is disposed above the pixel electrode 82 and receives a voltage through different paths, the liquid crystal 310 can minimize the voltage difference between the voltage of the control electrode 182 and the pixel electrode 82. By controlling the orientation of, the texture can be stabilized quickly, and the texture can be prevented from being transferred into the pixel electrode 82. In addition, since the control electrode 182 is positioned above the pixel electrode 82, the voltage difference between both electrodes can be maintained even if the thickness of the pixel electrode insulating layer 170 interposed therebetween can be stabilized, so that the texture can be stabilized quickly. . On the other hand, the width of the control electrode 182 (see W _{1 in} FIG. 4) can be adjusted without lowering the aperture ratio, which is advantageous in the design of the control electrode 182.

6A to 7B, the texture control effect of the liquid crystal display according to the first exemplary embodiment including the notched control electrode will be described in comparison with the liquid crystal display without the notch. 6A to 7B are photographs comparing the texture generation degree of the liquid crystal display according to the first exemplary embodiment of the present invention including the notch with no notch.

As shown in FIG. 6A, in the liquid crystal display according to the present embodiment including the control electrode having the notch, the singular point is accurately fixed to the position of the notch when 50 ms after the driving voltage is applied, and the texture is stabilized quickly. have. In addition, as shown in FIG. 7A, in the liquid crystal display of the present embodiment, even when 1500 ms elapses after the driving voltage is applied, the texture is still stabilized and does not transition into the pixel electrode. On the other hand, as shown in FIG. 6B, the liquid crystal display including only the control electrode without the notch has an irregular texture when 50 ms elapses after the driving voltage is applied and 50 ms elapses after the driving voltage is applied. As described above, it can be seen that the texture transitions into the pixel electrode after 1500 ms after the driving voltage is applied.

In addition, although not shown, the liquid crystal display according to the present exemplary embodiment including the control electrode having the notch also quickly stabilized the luminance deterioration occurring after the driving voltage was applied, and the transmittance was also high.

The liquid crystal display is formed by disposing a backlight assembly including a lamp under the thin film transistor array panel 100, the common electrode display panel 200, and the liquid crystal layer 300 interposed therebetween.

Hereinafter, the liquid crystal display according to the second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9. 8 is a layout view of a thin film transistor array panel included in a liquid crystal display according to a second exemplary embodiment of the present invention. FIG. 9 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line D-D ′ of the thin film transistor array panel of FIG. 8. In the following embodiments, the same reference numerals are used for the same elements as those of the first embodiment of the present invention for convenience of description, and the description thereof will be omitted or simplified.

8 and 9, in the liquid crystal display of the present exemplary embodiment, the control electrode 184 is electrically connected to the pixel electrode 82.

In the thin film transistor array panel 101 included in the liquid crystal display of the present embodiment, one data line 62a is formed for each pixel differently from the first embodiment of the present invention. As a result, one source electrode 65a and one drain electrode 66a are formed for each pixel, and these constitute a data line.

The signal applied from the data line 62a is transferred to the drain electrode 66a, and the drain electrode 66a is connected to the pixel electrode 82 through the first contact hole 76a formed in the passivation layer 70. The signal applied from the data line 62a is transferred to the pixel electrode 82.

The pixel electrode insulating layer 171 is formed on the pixel electrode 82 and on the pixel electrode 82 and the passivation layer 70 so as to cover the entire surface of the first insulating substrate 10. The pixel electrode insulating layer 171 of the present embodiment serves to maintain the voltage difference between the pixel electrode 82 and the control electrode 184. That is, in order for the control electrode 184 disposed on the pixel electrode 82 to form a strong electric field to form a new domain in the pixel electrode 82, the voltage of the control electrode 184 is higher than the voltage of the pixel electrode 82. Since the same voltage is applied to the pixel electrode 82 and the control electrode 184, the voltage difference can be maintained by the voltage drop caused by the pixel electrode insulating layer 171. A second contact hole 77b for connecting the pixel electrode 82 and the control electrode 184 is formed in the pixel electrode insulating layer 171.

The control electrode 184 is connected to the pixel electrode 82 through the second contact hole 77b formed in the pixel electrode insulating layer 171. Accordingly, the signal applied from the data line 62a is transferred to the control electrode 184 via the pixel electrode 82. However, as described above, even when the control electrode 184 and the pixel electrode 82 receive a signal from the same data line 62a, the control electrode 184 is not connected to the pixel electrode due to the voltage drop caused by the pixel electrode insulating layer 171. It has a higher voltage than 82). On the other hand, since the control electrode 184 does not need to receive a voltage from a separate data line, it is not necessary to cut the pixel electrode 82 to connect the control electrode 184 to a separate data line.

In the control electrode 184 of the present embodiment, a convex notch 185a or a concave notch 185b is formed, so that the thickness of the pixel electrode insulating film 171 is thinner than when the notches 185a and 185b are not formed. You can control the texture.

Hereinafter, a liquid crystal display according to a third exemplary embodiment of the present invention will be described in detail with reference to FIGS. 10 and 11. 10 is a layout view of a thin film transistor array panel included in a liquid crystal display according to a third exemplary embodiment of the present invention. FIG. 11 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line E-E ′ of the thin film transistor array panel of FIG. 10.

10 and 11, the pixel electrode insulating layer included in the thin film transistor array panel 102 of the present exemplary embodiment may be a pixel electrode insulating pattern 172 patterned along the control electrode 186.

The pixel electrode insulating pattern 172 is formed to protrude above the pixel electrode 82 to prevent the pixel electrode 82 and the control electrode 186 from being shorted or to maintain a voltage difference therebetween. The height of the pixel electrode insulation pattern 172 may be adjusted in relation to the voltage applied to the pixel electrode 82 and the control electrode 186. That is, as shown in FIG. 10, when the control electrode 186 and the pixel electrode 82 receive a voltage from the second and first data lines 62b and 62a which are different from each other, the pixel electrode insulating pattern 172 The height can be formed as thin as possible. In this case, an area larger than the second contact hole 76b may be cut in the pixel electrode 82 so as not to be shorted with the control electrode 186. On the other hand, unlike the illustration, the pixel electrode 82 and the control electrode 186 are applied with the same signal from one data line (not shown), and the pixel electrode 82 is controlled by the pixel electrode insulating pattern 172. When the voltage is lower than the control electrode 186, the thickness of the pixel electrode insulating pattern 172 may be somewhat thicker. However, even in this case, since the control electrode 186 of the present embodiment includes a convex notch 187a and a concave notch 187b for controlling the texture, the thickness of the pixel electrode insulating pattern 172 is not important.

The width of the pixel electrode insulating pattern 172 may be wider than that of the control electrode 186, and the material thereof is substantially the same as that of the pixel electrode insulating layer (see 170 of FIG. 2) of the first embodiment of the present invention.

Hereinafter, a liquid crystal display according to a fourth exemplary embodiment of the present invention will be described in detail with reference to FIGS. 12 and 13. 12 is a layout view of a thin film transistor array panel included in a liquid crystal display according to a fourth exemplary embodiment of the present invention. FIG. 13 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel along the line F-F ′ of the thin film transistor array panel of FIG. 12.

12 and 13, the pixel electrode 82 included in the thin film transistor array panel 103 according to the present exemplary embodiment includes a slit disposed between the plurality of domain forming means 83 and the plurality of domain forming means 83. 88). The slits 88 are arranged side by side alternately with the domain forming means 83.

The control electrode 188 of the present embodiment is positioned inside the slit 88 so as not to contact the pixel electrode 82. To this end, the width of the control electrode 188 is formed to be narrower than the width of the slit 88, when the convex notch 189a is formed in the control electrode 188, the sum of the widths of the control electrode 188 and the convex notch 189a. It is formed narrower than the width of this slit 88. When the width of the control electrode 188 is, for example, 1 to 12 μm, the width of the slit 88 is formed to maintain a predetermined distance from the convex notch 189a in consideration of the width of the convex notch 189a.

The control electrode 188 of the present exemplary embodiment may be positioned on the same layer as the pixel electrode 82. In addition, the control electrode 188 and the pixel electrode 82 may be made of the same material. Accordingly, the pixel electrode 82 and the control electrode 188 may be formed in one process by patterning the same transparent conductor. The control electrode 188 may be formed with a concave notch 189b and a convex notch 189a having substantially the same arrangement interval, spacing width, shape, and the like as the first embodiment of the present invention. The control electrode 188 and the notches 189a and 189b formed thereon are spaced apart from the edge of the slit 88 so as not to be shorted with the pixel electrode 82.

The control electrode 188 of the present embodiment is not electrically connected to the pixel electrode 82, and receives a higher voltage than the pixel electrode 82 to control the texture.

 While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: first insulating substrate 22: gate line
26a and 26b: gate electrode 28: storage wiring
30: gate insulating film 40a, 40b: semiconductor layer
55a, 55b, 56a, 56b: ohmic contact layers 62a, 62b: data line
65a, 65b: source electrode 66a, 66b: drain electrode
70: protective film 76a: first contact hole
76a and 77b: second contact hole 82: pixel electrode
83: domain forming means 88: slit
92, 152: vertical alignment layer
100, 101, 102, 103: thin film transistor array panel
110: second insulating substrate 120: black matrix
130: color filter 135: overcoat layer
140: common electrode 170 and 171: pixel electrode insulating film
172: pixel electrode insulation patterns 182, 184, 186, 188: control electrode
183a, 183b, 185a, 185b, 187a, 187b, 189a, 189b: notch
200: common electrode panel 300: liquid crystal layer
310: liquid crystal

Claims (10)

A first insulating substrate;
A pixel electrode disposed on the first insulating substrate and partitioned by a plurality of domain forming means;
A pixel electrode insulating film disposed on the pixel electrode; And
And a control electrode disposed on the pixel electrode insulating film between the plurality of domain forming means so as to be insulated from the pixel electrode, and having a plurality of notches. The method of claim 1,
The thickness of the pixel electrode insulating film is 5 ~ 200nm,
The pixel electrode insulating layer is formed to cover the entire surface of the first insulating substrate. 3. The method of claim 2,
The control electrode is not electrically connected to the pixel electrode, and the voltage applied to the control electrode is higher than the voltage applied to the pixel electrode. 3. The method of claim 2,
A first data line including a first data line formed on the first insulating substrate; And
A second data line including a second data line formed in parallel with the first data line;
The pixel electrode receives a voltage from the first data line, and the control electrode receives a voltage from the second data line. 3. The method of claim 2,
And the control electrode is electrically connected to the pixel electrode. 3. The method of claim 2,
The pixel electrode insulating layer is a pixel electrode insulating pattern patterned along the control electrode. The method according to claim 6,
The width of the pixel electrode insulating pattern is wider than the width of the control electrode. The method of claim 1,
The control electrode is made of the same transparent conductor as the pixel electrode,
The control electrode has a width of 1 ~ 12㎛. The method of claim 1,
And the domain forming means is a gap formed by patterning the pixel electrode. The method of claim 1,
And a second insulating substrate disposed to face the first insulating substrate and including a non-patterned common electrode.

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