KR101529943B1 - Liquid crystal display - Google Patents

Abstract

There is provided a liquid crystal display device in which a stabilization speed of a texture is improved. The liquid crystal display device includes a first insulating substrate, a pixel electrode arranged on the first insulating substrate and partitioned by a plurality of domain forming means, a pixel electrode insulating film disposed on the pixel electrode, and a plurality And a control electrode disposed on the pixel electrode insulating film between the domain forming means of the pixel electrode.

Description

[0001] Liquid crystal display [0002]

The present invention relates to a liquid crystal display device.

2. Description of the Related Art [0002] A liquid crystal display device is one of the most widely used flat panel display devices, and is composed of two display panels having field generating electrodes such as a pixel electrode and a common electrode, and a liquid crystal layer interposed therebetween, To generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among them, the vertical alignment mode liquid crystal display device in which the long axis of the liquid crystal is arranged so as to be perpendicular to the upper and lower display panels in a state in which no electric field is applied has been spotlighted because of its large contrast ratio and easy implementation of a wide reference viewing angle. Vertical Alignment Mode As a means for realizing a wide viewing angle in a liquid crystal display device, there is a method of arranging a domain forming means such as a gap or a projection on an electric field generating electrode.

On the other hand, a liquid crystal display device provided with gaps in both the upper and lower display panels is vulnerable to static electricity and has a disadvantage in that an align miss occurs. Thus, a pattern is formed only on the lower display panel, Leased VA (Patternless VA) mode liquid crystal display devices are being studied. However, the patternless VA mode liquid crystal display also has a problem in that a texture is generated at the boundaries of domains.

In order to control this, a method of arranging a separate control electrode (DCE) on the pixel electrode has been studied, but this also has a problem that the texture is not easily stabilized.

Therefore, it is necessary to improve the stabilization speed of the texture.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device having improved texture stabilization speed.

The technical problems of the present invention are not limited to the technical matters mentioned above, and other technical problems which are not mentioned can be understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a liquid crystal display comprising a first insulating substrate, a pixel electrode arranged on the first insulating substrate and divided by a plurality of domain forming means, A pixel electrode insulating film disposed on the pixel electrode, and a control electrode disposed on the pixel electrode insulating film between the plurality of domain forming means to be insulated from the pixel electrode and having a plurality of notches.

The details of other embodiments are included in the detailed description and drawings.

As described above, the liquid crystal display according to the embodiments of the present invention has one or more of the following effects.

First, by including a notch in the control electrode, the texture formed on the control electrode can be quickly stabilized.

Secondly, when the control electrode is disposed on the upper portion of the pixel electrode, the texture can be quickly stabilized even if the thickness of the pixel electrode insulating film is reduced.

Thirdly, when the control electrode is disposed above the pixel electrode, the aperture ratio can be improved.

1 is a layout diagram of a thin film transistor panel included in a liquid crystal display according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line A-A 'of the thin film transistor panel of FIG.
FIG. 3 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line B-B 'of the thin film transistor panel of FIG.
4 is a partially enlarged view of a control electrode having a notch included in the liquid crystal display device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line C-C 'of the thin film transistor panel of FIG.
Figs. 6A and 7B are photographs comparing the degree of texture generation of the liquid crystal display device according to the first embodiment of the present invention including a notch with a case where there is no notch. Fig.
8 is a layout diagram of a thin film transistor panel included in a liquid crystal display device according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line D-D 'of the thin film transistor panel of FIG.
10 is a layout diagram of a thin film transistor panel included in a liquid crystal display device according to a third embodiment of the present invention.
11 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along the line E-E 'of the thin film transistor panel of FIG.
12 is a layout diagram of a thin film transistor panel included in a liquid crystal display according to a fourth embodiment of the present invention.
13 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line F-F 'of the thin film transistor panel of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation.

Hereinafter, a liquid crystal display according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a layout diagram of a thin film transistor panel included in a liquid crystal display according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line A-A 'of the thin film transistor panel of FIG.

The liquid crystal display device of this embodiment includes a thin film transistor display panel 100 and a common electrode display panel 200 arranged to face each other and a liquid crystal layer 300 interposed between the two display panels 100 and 200.

Referring to FIGS. 1 and 2, a color filter 130, a pixel electrode 82, and the like may all be formed on the thin film transistor display panel 100 included in the liquid crystal display device of the present embodiment. The liquid crystal display of the present embodiment may be an array on color filter (AOC) structure in which a thin film transistor array such as a gate wiring is formed on a color filter 130, or a color filter on (COA) in which a color filter 130 is formed on a thin film transistor array. Array) structure. For the sake of convenience, a liquid crystal display device having an AOC structure will be described as an example.

The thin film transistor display panel 100 of the liquid crystal display of the AOC structure is formed with a black matrix 120 which defines a pixel region immediately above the first insulating substrate 10 and prevents light leakage to improve image quality. For example, the black matrix 120 may be formed of a metal (metal oxide) such as chromium (Cr), chromium oxide, or an organic black resist. The black matrix 120 may be formed to overlap the gate and / or data lines to maximize the aperture ratio.

In the pixel region defined by the black matrix 120, red, green, and blue color filters 130 are sequentially arranged. These color filters 130 serve to pass only light of a specific wavelength band.

The color filter 130 may be made of a photosensitive organic material, for example, a photoresist. The color filters 130 may be formed to have the same thickness, or may have a constant step.

On the color filter 130, an overcoat layer 135 may be formed to planarize the stepped portions.

On the overcoat layer 135, for example, a gate line 22 extending in the transverse direction and transmitting a gate signal is formed. One gate line 22 is allocated to one pixel. A pair of protruding first and second gate electrodes 26a and 26b are formed in the gate line 22. [ The gate line 22 and the first and second gate electrodes 26a and 26b are referred to as gate wirings.

Furthermore, on the first insulating substrate 10, there is formed a storage wiring 28 extending in the transverse direction substantially parallel to the gate line 22. The storage wiring 28 is formed so as to overlap with a part of the pixel electrode 82 to be described later in the pixel. 1, the storage line 28 is disposed at the center of the pixel, but the present invention is not limited thereto. The storage line 28 overlaps the pixel electrode 82 to form a storage capacitance The shape and arrangement of the storage wiring 28 can be modified into various forms.

The gate wirings 22, 26a and 26b and the storage wirings 28 may be formed of aluminum metal such as aluminum (Al) and aluminum alloy, metals of the silver and silver alloy such as silver, copper (Cu) Such as molybdenum metal, chromium (Cr), titanium (Ti), and tantalum (Ta), such as copper, molybdenum and molybdenum alloys. Further, the gate wirings 22, 26a, 26b and the storage wirings 28 may have a multi-film structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having a low resistivity such as an aluminum-based metal, a silver-based metal, a copper-based metal, or the like so as to reduce signal delays and voltage drop of the gate wirings 22, 26a, 26b and the storage wirings 28. [ Based metal or the like. Alternatively, the other conductive film may be made of a material having excellent contact properties with other materials, particularly ITO (indium tin oxide) and IZO (indium zinc oxide), such as molybdenum metal, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film, an aluminum top film, an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate wirings 22, 26a, 26b and the storage wirings 28 may be made of various metals and conductors.

A gate insulating film 30 made of silicon nitride (SiNx), silicon oxide (SiOx) or the like is formed on the gate wirings 22, 26a, 26b and the storage wirings 28. [

A pair of semiconductor layers 40a and 40b made of hydrogenated amorphous silicon, polycrystalline silicon, or the like is formed on the gate insulating film 30. The semiconductor layers 40a and 40b may have a variety of shapes such as a island shape and a linear shape, and may be formed in a island shape on the gate electrodes 26a and 26b, for example, as shown in FIG. In another embodiment of the present invention, when the semiconductor layers 40a and 40b are linearly formed, the first and second data lines 62a and 62b are formed to extend to the top of the gate electrodes 26a and 26b Shape.

On the semiconductor layers 40a and 40b are formed ohmic contact layers 55a and 56a (55b and 55b in FIG. 3) made of a material such as silicide or n + hydrogenated amorphous silicon highly doped with n-type impurities, 56b) are respectively formed. The ohmic contact layers 55a and 56a may have various shapes such as a island shape and a linear shape. For example, as shown in FIG. 2, when the ohmic contact layers 55a and 56a are island-shaped, 56a may be positioned below the drain electrode 66a and the source electrode 65a. In another embodiment of the present invention, when the ohmic contact layer is linear, the ohmic contact layer may extend down to the first and second data lines 62a and 62b.

The first and second data lines 62a and 62b and the first and second drain electrodes 66a and 66b are formed on the ohmic contact layers 55a and 56a and the gate insulating film 30, respectively. The first and second data lines 62a and 62b extend in parallel to each other, for example, in the vertical direction, and intersect the gate line 22 to define pixels. First and second source electrodes 65a and 65b are extended from the first and second data lines 62a and 62b to the upper portions of the semiconductor layers 40a and 40b in a branched form . The first and second drain electrodes 66a and 66b are separated from the first and second source electrodes 65a and 65b and are connected to the first and second source electrodes 65a and 65b around the gate electrodes 26a and 26b. 40b so as to face the semiconductor layers 40a, 40b.

The first drain electrode 66a is connected to the pixel electrode 82 through the first contact hole 76a and the second drain electrode 66b is connected to the control electrode 182 through the second contact hole 76b. And the voltages applied from the first and second data lines 62a and 62b are transmitted to the pixel electrode 82 and the control electrode 182, respectively.

The first and second data lines 62a and 62b, the first and second source electrodes 65a and 65b and the first and second drain electrodes 66a and 66b are referred to as first and second data lines.

The data lines 62, 65, and 66 are preferably made of a refractory metal such as chromium, molybdenum, tantalum, and titanium, and may be formed of a lower film (not shown) such as a refractory metal, Lt; RTI ID = 0.0 > Si). ≪ / RTI > Examples of the multilayer structure include a triple layer of a molybdenum film-aluminum film-molybdenum film in addition to the chromium lower film and the aluminum upper film or the aluminum lower film and the molybdenum upper film.

The first and second source electrodes 65a and 65b are at least partially overlapped with the semiconductor layers 40a and 40b and the first and second drain electrodes 66a and 66b are formed around the gate electrodes 26a and 26b The semiconductor layers 40a and 40b and the first and second source electrodes 65a and 65b are overlapped with each other. The ohmic contact layers 55a and 56a are formed on the semiconductor layers 40a and 40b and the first and second source electrodes 65a and 65b and the semiconductor layers 40a and 40b and the first and second drain electrodes 66a and 66b, 66b so as to lower the contact resistance therebetween.

A protective film 70 made of an insulating film is formed on the first and second data lines 62a and 62b, the first and second drain electrodes 66a and 66b and the exposed semiconductor layers 40a and 40b. Here, the protective layer 70 may be formed of an inorganic material such as silicon nitride or silicon oxide, an organic material having excellent planarization characteristics and photosensitivity, or an a-Si: C: O (silicon oxide) film formed by plasma enhanced chemical vapor deposition (PECVD) , a-Si: O: F, or the like. The protective layer 70 may have a bilayer structure of a lower inorganic layer and an upper organic layer to protect the exposed semiconductor layers 40a and 40b while making good use of the organic layer.

The protection film 70 is formed with first and second contact holes 76a and 76b for exposing the first and second drain electrodes 66a and 66b, respectively.

A pixel electrode 82 electrically connected to the first drain electrode 66a is formed on the passivation layer 70 through a first contact hole 76a for each pixel. That is, the pixel electrode 82 is physically and electrically connected to the first drain electrode 66a through the first contact hole 76a, and receives the data voltage from the first drain electrode 66a. The pixel electrode 82 is made of a transparent conductor such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

The pixel electrode 82 is partitioned by a plurality of domain forming means 83. The domain forming means 83 may be, for example, a gap formed by patterning the pixel electrode 82, but may be in the form of a projection and is not limited to such a shape.

1, the domain forming means 83 includes a lateral portion formed in a lateral direction at a position where the pixel electrode 82 is vertically divided into two portions, and a lateral portion formed in the upper and lower portions of the bisected pixel electrode 82, As shown in Fig. Here, the upper and lower oblique lines are perpendicular to each other in order to evenly distribute the direction of the horizontal electric field in four directions. The hatched portion includes a portion that forms a 45-degree angle with the gate line 22 at a substantially 45-degree angle, and the domain forming means 83 includes a portion that divides the pixel region vertically (line parallel to the gate line) And the lower portion is substantially mirror symmetric. For example, as shown in FIG. 1, the pixel electrode 82 positioned above the center of the pixel is formed with a diagonal line portion of the domain forming means 83 substantially at 45 degrees to the gate line 22, The pixel electrode 82 located below the center of the gate line 22 may be formed with a slanting line of the domain forming means 83 substantially at -45 degrees to the gate line 22. [ However, the present invention is not limited to this, and the shape and arrangement of the hatched portions of the domain forming means 83 in the range where the hatched portions of the domain forming means 83 substantially form the angle of 45 [deg.] Or -45 [ It can be deformed.

When the domain forming means 83 of the pixel electrode 82 and the control electrode 182 to be described later are used, the display region of the pixel electrode 82 is separated from the liquid crystal (see 310 in FIG. 5) included in the liquid crystal layer 300, Is divided into a plurality of domains in accordance with the direction in which the main director of the field effect transistor is arranged when the electric field is applied. Here, the term " domain " refers to a region consisting of liquid crystals in which a director of a liquid crystal is inclined in a specific direction by an electric field formed between the pixel electrode 82 and the common electrode 140.

A voltage for driving the liquid crystal display is applied to the pixel electrode 82 and a voltage lower than a voltage of the control electrode 182 described later is applied.

Hereinafter, the insulating film, the control electrode, the vertical alignment film, and the common electrode panel included in the liquid crystal display device according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 3. FIG. FIG. 3 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line B-B 'of the thin film transistor panel of FIG.

Referring to FIGS. 1 and 3, a pixel electrode insulating layer 170 is formed on the pixel electrode 82.

The pixel electrode insulating film 170 may be made of an inorganic material such as silicon nitride or silicon oxide, or an organic material such as acrylic resin. The pixel electrode insulating film 170 is disposed between the control electrode 182 and the pixel electrode 82 so that the two electrodes 82 and 182 are not shorted. Since the pixel electrode insulating film 170 is provided to prevent the short circuit between the pixel electrode 82 and the control electrode 182, the thickness of the pixel electrode insulating film 170 is preferably as thin as 5 to 200 nm . The pixel electrode insulating film 170 of this embodiment is formed on the pixel electrode 82 and the protective film 70 so as to cover the entire surface of the first insulating substrate 10. Thus, the step of patterning the pixel electrode insulating film 170 is not required, so that an increase in the processing time can be minimized.

The control electrode 182 is disposed on the pixel electrode insulating film 170 and insulated from the pixel electrode 82. The control electrode 182 includes a horizontal portion formed in a horizontal direction at a position where the pixel electrode 82 is divided into upper and lower portions and a shaded portion formed in an oblique direction at upper and lower portions of the divided pixel electrode 82 . Herein, the control electrode 182 usually refers to an oblique portion. It is preferable that the control electrode 182 is disposed between the plurality of domain forming means 83 and located at the center of the pixel electrode 82 located between the adjacent domain forming means 83. [ Specifically, the shaded portions of the domain forming means 83 and the shaded portions of the control electrode 182 are preferably arranged alternately at substantially equal intervals.

The control electrode 182 is made of the same transparent conductor as the pixel electrode 82. [ Accordingly, even if a separate control electrode 182 is disposed on the pixel electrode 82, the aperture ratio of the liquid crystal display device is not reduced. However, in order to minimize the area where the texture is generated, the control electrode 182 may have a width of 1 to 12 μm (see W _{1 in} FIG. 5).

The control electrode 182 is connected to the second drain electrode 66b through the second contact hole 76b. The voltage applied from the second data line 62b is transmitted to the control electrode 182 via the second source electrode 65b and the second drain electrode 66b. The pixel electrode 82 is also cut off at the portion where the second contact hole 76b is formed so that the pixel electrode 82 and the control electrode 182 are not electrically connected to each other. The voltage applied to the control electrode 182 from the second data line 62b is higher than the voltage applied to the pixel electrode 82 from the first data line 62a. For example, the voltage applied to the pixel electrode 82 may be 6V, the voltage applied to the control electrode may be 8V, and the voltage difference between the two electrodes may be controlled by a texture to be described later, It is preferable that the voltage is about 2 V so as to prevent transition.

A first vertical alignment film 92 capable of aligning liquid crystals may be formed on the control electrode 182 and the pixel electrode insulating film 170 of the present embodiment. The first vertical alignment film 92 vertically aligns the liquid crystals together with the second vertical alignment film 152. Accordingly, when no driving voltage is applied to the liquid crystal display device, a clear black color is realized in the liquid crystal display device. The first vertical alignment layer 92 may be made of a material having a polyimide as a main chain and a side chain.

A polarizing plate (not shown) may be formed on the first insulating substrate 10. Specifically, the polarizing plate may be formed on the first insulating substrate 10 opposite to the surface on which the pixel electrodes 82 and the like are formed. The polarization axis of the polarizing plate formed on the first insulating substrate 10 is perpendicular to the polarization axis of the polarizing plate formed on the second insulating substrate 110.

The common electrode display panel 200 includes a common electrode 140 formed on the second insulating substrate 110 and not patterned and arranged to face the thin film transistor display panel 100. The common electrode 140 of this embodiment is not patterned. Since the process for patterning the common electrode 140 is not required in the common electrode panel 200 of the present embodiment, misalignment can be prevented from occurring when the thin film transistor panel 100 and the common electrode panel 200 are assembled And it is possible to reduce the manufacturing cost because the anti-static treatment is not required and the transmittance is high.

On the common electrode 140, a second vertical alignment layer 152 for vertically aligning liquid crystals is formed. Between the thin film transistor display panel 100 and the common electrode panel 200, spacers or the like for maintaining a cell gap between the two display panels may be interposed.

A polarizing plate may be disposed on the second laminated substrate 110 on the opposite side of the surface on which the common electrode 140 is formed and is perpendicular to the polarizing axis of the polarizing plate formed on the first insulating substrate 10.

A liquid crystal layer 300 formed from a liquid crystal 310, a UV curable monomer, and a UV curing initiator is interposed between the thin film transistor display panel 100 and the common electrode panel 200 facing each other.

The liquid crystal 310 included in the liquid crystal layer 300 may have a negative dielectric anisotropy and may be, for example, a nematic liquid crystal 310. [ The UV curable monomer can be, for example, an acrylate based monomer, and the UV curing initiator can be made of a material that can be absorbed in the UV region.

Hereinafter, with reference to FIG. 1, FIG. 4, and FIG. 5, the control electrode, the notch and the orientation of the liquid crystal by the control electrode, the notch, and the like included in the liquid crystal display device according to the first embodiment of the present invention will be described in detail. 4 is a partially enlarged view of a control electrode having a notch included in the liquid crystal display device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line C-C 'of the thin film transistor panel of FIG.

As shown in FIGS. 1 and 4, the control electrode 182 may be provided with a plurality of notches 183a and 183b. The notches 183a and 183b are formed along at least one side of the control electrode 182 and may be formed along both sides of the control electrode 182. [ The notches 183a and 183b may be convex notches 183a protruded from both sides of the control electrode 182 toward the domain forming means 83 or may be concave notches 183b recessed from both sides of the control electrode 182. [ The notches 183a and 183b formed in the control electrode 182 may be formed of only the convex notch 183a or only the concave notch 183b and the convex notch 183a and the concave notch 183b may be mixed have. In this case, the convex notch 183a and the concave notch 183b may be alternately arranged along one or both sides of the control electrode 182. [ It is preferable that the notches 183a and 183b formed in the shaded portion of one control electrode 182 are formed every interval L ₁ of 20 to 50 μm along at least one side of the control electrode 182. The notches 183a and 183b formed on one side of the control electrode 182 and the notches 183a and 183b formed on the other side of the control electrode 182 are preferably opposed to each other. In the case of a pair of concave notches 183b facing each other, these concave notches 183b may be spaced to have a width of 3 to 5 mu m (W ₂ ). In this case, it is needless to say that the width W ₁ of the control electrode 182 must be wider.

The shape of the notches 183a and 183b may be a polygon such as a triangle, a quadrangle, a rhombus, or the like, or may be semicircular, but forms a singular point (P, Q) The present invention is not limited to such a shape.

Referring to FIG. 4, when the electric field is applied to the pixel electrode 82 and the common electrode (see 140 in FIG. 5), the notches 183a and 183b (P, Q) in which the directors of the liquid crystal are gathered are intentionally formed on the control electrode 182 to accumulate the elastic energy of the liquid crystals located around the singular points P and Q so that the liquid crystal The head arrangement direction A is determined in advance.

For example, in the region where the concave notch 183b is formed, a negative-polarity singular point P in which the head alignment direction A of the liquid crystal molecules partially converges and partly diverges is formed. In the area in which the convex notch 183a is formed, a bipolar singular point Q in which the head alignment direction A of the liquid crystal molecules converge is formed. The concave notch 183b and the convex notch 183a are arranged alternately so that the heads of the liquid crystal molecules disposed at the domain boundary are directed from the negative polarity P to the positive polarity odd point Q A) is determined in advance so that the liquid crystal can receive the arrangement driving force B. The arrangement direction of the liquid crystal arranged in the control electrode 182 is determined in advance by the notches 183a and 183b so that the arrangement distortion of the liquid crystal molecules at the domain boundary becomes longer as the application time of the driving voltage elapses, It is possible to suppress the phenomenon of spreading to the inside of the electrode 82.

Accordingly, the liquid crystal arranged in the control electrode 182 can be stably and regularly arranged through the notches 183a and 183b, so that the texture generated at the domain boundary can be quickly stabilized, Can be stabilized at an early stage.

Although not shown, it is preferable that the width of the control electrode 182 is formed so as to be reduced or increased in a constant direction with respect to a predetermined section in order to stabilize the texture generated at the domain boundary more quickly. For example, the width of the control electrode 182 preferably extends from the concave notch 183b to the convex notch 183a. In this case, an arrangement driving force (direction B) in which the heads of the liquid crystal molecules are directed to the positive specific point Q formed in the convex notch 183a from the negative polarity point P of the negative polarity formed on the concave notch 183b . Therefore, the liquid crystal molecules disposed in the control electrode 182 can be arranged in a predetermined direction in a shorter time, and the texture is stabilized at a higher speed.

5, when an electric field is formed in the pixel electrode 82 and the common electrode 140, the liquid crystal 310 has different directions in a plurality of domains formed by the domain forming means 83. However, in order to minimize the generation of textures by previously determining the arrangement direction of the liquid crystals 310 in the pixel electrode 82 between the domain forming means 83 in one domain, control is performed between the domain forming means 83 The electrode 182 is disposed. The upper portion of the control electrode 182 has a higher potential than the upper portion of the other pixel electrode 82 because the voltage higher than the pixel electrode 82 is applied to the control electrode 182 as described above, (310). ≪ / RTI > Accordingly, the alignment directions of the liquid crystal 310 on the left and right sides of the control electrode 182 are opposite to each other with respect to the control electrode 182, and the domains in the pixel electrode 82 are divided so that the generation of the texture is reduced.

The control electrode 182 is disposed above the pixel electrode 82 and the voltage is applied to the liquid crystal 310 while minimizing the voltage difference between the voltage of the control electrode 182 and the pixel electrode 82. Therefore, The texture can be stabilized at a high speed and the texture can be prevented from being transferred into the pixel electrode 82. Since the control electrode 182 is located above the pixel electrode 82, even if the thickness of the pixel electrode insulating film 170 interposed therebetween is reduced, the voltage difference between the electrodes can be maintained, and the texture can be stabilized at a high speed . On the other hand, the width of the control electrode 182 (see W _{1 in} FIG. 4) can be adjusted without lowering the aperture ratio, which is also advantageous for the design of the control electrode 182.

6A to 7B, the texture control effect of the liquid crystal display device according to the first embodiment of the present invention including the notched control electrodes is compared with a liquid crystal display device having no notch. Figs. 6A and 7B are photographs comparing the degree of texture generation of the liquid crystal display device according to the first embodiment of the present invention including a notch with a case where there is no notch. Fig.

As shown in FIG. 6A, in the liquid crystal display device including the control electrode having the notch, when the elapse of 50 ms after application of the driving voltage, it is confirmed that the singular point is accurately fixed to the position of the notch and the texture is stabilized at a rapid have. In addition, as shown in FIG. 7A, the liquid crystal display device of this embodiment can confirm that the texture is still stabilized even after the elapse of 1500 ms after application of the driving voltage, and the transition to the pixel electrode is not performed. On the other hand, as shown in FIG. 6B, in the liquid crystal display device including only the control electrode without the notch, the texture is irregular at 50 ms after application of the driving voltage and at 50 ms after application of the driving voltage, As a result, it is confirmed that the texture is transferred into the pixel electrode after 1500 ms after the driving voltage is applied.

In addition, although not shown, the liquid crystal display device of the present embodiment including the control electrode having the notch was quickly stabilized in the luminance lowering phenomenon generated after application of the driving voltage, and the transmittance was also high.

The liquid crystal display device is formed by disposing a backlight assembly including a lamp below the thin film transistor display panel 100, the common electrode panel 200, and the liquid crystal layer 300 interposed therebetween.

Hereinafter, a liquid crystal display device according to a second embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9. FIG. 8 is a layout diagram of a thin film transistor panel included in a liquid crystal display device according to a second embodiment of the present invention. FIG. 9 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line D-D 'of the thin film transistor panel of FIG. In the following embodiments, the same reference numerals are used for the same constituent elements as those of the first embodiment of the present invention for convenience of description, and the description thereof is omitted or simplified.

8 and 9, in the liquid crystal display device of this embodiment, the control electrode 184 is electrically connected to the pixel electrode 82. [

In the thin film transistor display panel 101 included in the liquid crystal display device of the present embodiment, one data line 62a is formed for each pixel different from the first embodiment of the present invention. Accordingly, one source electrode 65a and one drain electrode 66a are formed for each pixel, and these form a data wiring.

The signal applied from the data line 62a is transferred to the drain electrode 66a and the drain electrode 66a is connected to the pixel electrode 82 through the first contact hole 76a formed in the protective film 70, And the signal applied from the data line 62a is transmitted to the pixel electrode 82. [

A pixel electrode insulating film 171 is formed on the pixel electrode 82 and the protective film 70 to cover the entire surface of the first insulating substrate 10. The pixel electrode insulating film 171 of this embodiment serves to maintain a voltage difference between the pixel electrode 82 and the control electrode 184. [ That is, in order for the control electrode 184 disposed on the pixel electrode 82 to form a strong electric field to form a new domain in the pixel electrode 82, the voltage of the control electrode 184 is higher than the voltage of the pixel electrode 82 The voltage difference can be maintained by the voltage drop by the pixel electrode insulating film 171 even when the same voltage is applied to the pixel electrode 82 and the control electrode 184. [ A second contact hole 77b for connecting the pixel electrode 82 and the control electrode 184 is formed in the pixel electrode insulating film 171.

The control electrode 184 is connected to the pixel electrode 82 through a second contact hole 77b formed in the pixel electrode insulating film 171. [ The signal applied from the data line 62a is transmitted to the control electrode 184 via the pixel electrode 82. [ Even if a signal is applied from the same data line 62a to the control electrode 184 and the pixel electrode 82 as described above, the voltage drop by the pixel electrode insulating film 171 causes the control electrode 184 to be electrically connected to the pixel electrode 82). Since the control electrode 184 does not receive a voltage from another data line, it is not necessary to cut the pixel electrode 82 to connect the control electrode 184 to another data line.

The control electrode 184 of the present embodiment is provided with the convex notch 185a or the concave notch 185b so that even when the thickness of the pixel electrode insulating film 171 is thinner than the case where these notches 185a and 185b are not formed You can control the texture.

Hereinafter, a liquid crystal display device according to a third embodiment of the present invention will be described in detail with reference to FIGS. 10 and 11. FIG. 10 is a layout diagram of a thin film transistor panel included in a liquid crystal display device according to a third embodiment of the present invention. 11 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along the line E-E 'of the thin film transistor panel of FIG.

10 and 11, the pixel electrode insulating layer included in the thin film transistor panel 102 of the present embodiment may be a pixel electrode insulating pattern 172 patterned along the control electrode 186.

The pixel electrode insulation pattern 172 protrudes above the pixel electrode 82 to prevent the pixel electrode 82 and the control electrode 186 from being short-circuited or to maintain a voltage difference therebetween. The height of the pixel electrode insulation pattern 172 can be adjusted in relation to the voltage applied to the pixel electrode 82 and the control electrode 186. 10, when a voltage is applied from the second and first data lines 62b and 62a, which are different from the control electrode 186 and the pixel electrode 82, The height can be as thin as possible. In this case, the pixel electrode 82 may be wider than the second contact hole 76b so as not to be short-circuited with the control electrode 186. [ The pixel electrode 82 and the control electrode 186 receive the same signal from one data line (not shown) and are electrically connected to the pixel electrode 82 When the voltage is lower than the control electrode 186, the thickness of the pixel electrode insulation pattern 172 may be formed to be somewhat thick. However, even in this case, the thickness of the pixel electrode insulating pattern 172 is not important because the control electrode 186 of this embodiment includes the convex notch 187a and the concave notch 187b for controlling the texture.

The width of the pixel electrode insulating pattern 172 may be larger than the width of the control electrode 186 and the material thereof is substantially the same as the pixel electrode insulating film (see 170 in FIG. 2) of the first embodiment of the present invention.

Hereinafter, a liquid crystal display according to a fourth embodiment of the present invention will be described in detail with reference to FIGS. 12 and 13. FIG. 12 is a layout diagram of a thin film transistor panel included in a liquid crystal display according to a fourth embodiment of the present invention. 13 is a cross-sectional view of a liquid crystal display including a thin film transistor panel along a line F-F 'of the thin film transistor panel of FIG.

12 and 13, the pixel electrode 82 included in the thin film transistor panel 103 of the present embodiment includes a plurality of domain forming means 83 and a plurality of slits (not shown) disposed between the plurality of domain forming means 83 88). ≪ / RTI > The slits 88 are alternately arranged in parallel with the domain forming means 83.

The control electrode 188 of this embodiment is located inside the slit 88 so as not to be in contact with the pixel electrode 82. [ The width of the control electrode 188 is formed narrower than the width of the slit 88. When the convex notch 189a is formed in the control electrode 188, the sum of the widths of the control electrode 188 and the convex notch 189a Is narrower than the width of the slit (88). When the width of the control electrode 188 is, for example, 1 to 12 占 퐉, the width of the slit 88 is formed so as to maintain a predetermined distance from the convex notch 189a in consideration of the width of the convex notch 189a.

The control electrode 188 of this embodiment can be located on the same layer as the pixel electrode 82. [ In addition, the control electrode 188 and the pixel electrode 82 may be formed of the same material. Accordingly, the pixel electrode 82 and the control electrode 188 may be formed in one process by patterning the same transparent conductor. The control electrode 188 may be formed with a concave notch 189b and a convex notch 189a having substantially the same arrangement interval, spacing width, and shape as the first embodiment of the present invention. The control electrode 188 and the notches 189a and 189b formed therein are disposed apart from the edge of the slit 88 so as not to be short-circuited with the pixel electrode 82. [

The control electrode 188 of this embodiment is not electrically connected to the pixel electrode 82 but receives a voltage higher than that of the pixel electrode 82 to control the texture.

 While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: first insulating substrate 22: gate line
26a, 26b: gate electrode 28: storage wiring
30: gate insulating film 40a, 40b: semiconductor layer
55a, 55b, 56a, and 56b: ohmic contact layers 62a and 62b:
65a, 65b: source electrode 66a, 66b: drain electrode
70: Protective layer 76a: First contact hole
76a, 77b: second contact hole 82: pixel electrode
83: Domain forming means 88: Slit
92, 152: vertical alignment film
100, 101, 102, and 103: thin film transistor display panel
110: second insulating substrate 120: black matrix
130: Color filter 135: Overcoat layer
140: common electrode 170, 171: pixel electrode insulating film
172: pixel electrode insulation pattern 182, 184, 186, 188: control electrode
183a, 183b, 185a, 185b, 187a, 187b, 189a, 189b:
200: common electrode panel 300: liquid crystal layer
310: liquid crystal

Claims (19)

A first insulating substrate;
A pixel electrode arranged on the first insulating substrate and partitioned by a plurality of domain forming means;
A pixel electrode insulating film disposed on the pixel electrode; And
And a control electrode disposed on the pixel electrode insulating film between the plurality of domain forming means to be insulated from the pixel electrode and having a plurality of notches,
The notch
A control electrode formed along at least one side of the control electrode,
Wherein the control electrode is not electrically connected to the pixel electrode, and a voltage applied to the control electrode is higher than a voltage applied to the pixel electrode. The method according to claim 1,
The thickness of the pixel electrode insulating film is 5 to 200 nm,
And the pixel electrode insulating film covers the entire surface of the first insulating substrate. delete 3. The method of claim 2,
A first data line including a first data line formed on the first insulating substrate; And
And a second data line including a second data line formed in parallel with the first data line,
Wherein the pixel electrode receives a voltage from the first data line and the control electrode receives a voltage from the second data line. delete 3. The method of claim 2,
Wherein the pixel electrode insulating film is a pixel electrode insulating pattern patterned along the control electrode. The method according to claim 6,
Wherein a width of the pixel electrode insulating pattern is larger than a width of the control electrode. The method according to claim 1,
Wherein the control electrode is made of the same transparent conductor as the pixel electrode,
Wherein the control electrode has a width of 1 to 12 mu m. The method according to claim 1,
And the domain forming means is a gap formed by patterning the pixel electrode. The method according to claim 1,
And a second insulating substrate disposed to face the first insulating substrate and including a non-patterned common electrode. The method according to claim 1,
Wherein the notches are formed at intervals of 20 to 50 mu m along at least one side of the control electrode. The method according to claim 1,
Wherein the notch is formed along both sides of the control electrode, and the notch formed at one side of the control electrode and the notch formed at the other side of the control electrode are a concave notch or a convex notch. 13. The method of claim 12,
Wherein the pair of notches opposed to each other is a concave notch and the opposed concave notches are spaced apart to have a width of 3 to 5 mu m. A first insulating substrate;
A pixel electrode arranged on the first insulating substrate and divided by a plurality of domain forming means and a slit disposed between the plurality of domain forming means; And
And a control electrode disposed inside the slit so as not to be in contact with the pixel electrode, the control electrode having a plurality of notches,
The notch
A control electrode formed along at least one side of the control electrode,
Wherein the control electrode is not electrically connected to the pixel electrode, and a voltage applied to the control electrode is higher than a voltage applied to the pixel electrode. 15. The method of claim 14,
Wherein the notches are formed at intervals of 20 to 50 mu m along at least one side of the control electrode. 15. The method of claim 14,
Wherein the notch is formed along both sides of the control electrode, and the notch formed at one side of the control electrode and the notch formed at the other side of the control electrode are a concave notch or a convex notch. 17. The method of claim 16,
Wherein the pair of notches opposed to each other is a concave notch and the opposed concave notches are spaced apart to have a width of 3 to 5 mu m. 15. The method of claim 14,
And the control electrode is located on the same layer as the pixel electrode. delete

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