KR20120064308A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to prevent damage to a separation film by forming a barrier layer on a sidewall after a primary open part is formed. CONSTITUTION: A sacrificing layer is formed on an upper portion of a substrate(10). A primary open part is formed by partially etching the sacrificing layer at a constant height. A barrier layer(17A) is formed on a sidewall of the primary open part. A secondary open part(16A) is formed by etching the rest of the sacrificing layer on a lower portion of the primary open part. The secondary open part exposes the substrate.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing capacitors in semiconductor devices.

The area occupied by capacitors is decreasing with increasing integration, miniaturization, and speed of semiconductor devices. Although the semiconductor device is highly integrated and miniaturized, the capacitance of the capacitor for driving the semiconductor device should be at least secured.

Recently, as the size of a semiconductor device is reduced to an ultra-small sized device, the height of the capacitor is increasing to secure the capacity of the capacitor in the development process of the semiconductor device. That is, over 50 high aspect ratio contacts are formed to overcome the reduction in storage capacity due to the reduction in line width.

However, various problems arise when forming high aspect ratio contacts.

First, when sufficient separator thickness is left to secure a bridge margin between neighboring storage nodes, an etch line width is too small to cause an open fail. In addition, when a process such as excessive etching is performed in order to prevent the open fail of the contact, there is a problem that bridges are generated between the storage nodes because a sufficient separator thickness between the storage nodes is not secured.

As described above, the bridging margin and contact open are difficult to meet both in the trade-off relationship.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and has an object of the present invention to provide a method of manufacturing a semiconductor device which prevents contact open failure while securing bridge margins between storage nodes.

A semiconductor device manufacturing method according to an embodiment of the present invention for achieving the above object comprises the steps of forming a sacrificial film on the substrate; Partially etching the sacrificial layer to a predetermined height to form a first open portion; Forming a barrier film on sidewalls of the primary open portion; And etching the remaining sacrificial layer under the first open part to form a second open part exposing the substrate.

In particular, before the forming of the sacrificial layer, forming an interlayer insulating layer on the substrate; Forming a storage node contact plug penetrating the interlayer insulating film and connected to the substrate; Recessing the interlayer insulating film to a predetermined height; The method may further include forming an etch stop layer on the resultant product including the storage node contact plug.

The forming of the barrier film on the sidewall of the primary open part may include forming a barrier conductive film along a step of a resultant product including the primary open part; And etching back the barrier conductive film on the sidewalls of the primary open portion.

In addition, after the forming of the secondary open portion, forming a conductive film for the electrode along the step of the resultant including the first and secondary open portion; Separating the electrode conductive film to form a lower electrode; Forming a dielectric film along the resultant material including the lower electrode; And forming an upper electrode on the dielectric layer.

The barrier layer may be formed of the same material as the electrode conductive layer, and the barrier layer may be formed of a titanium nitride layer (TiN).

A semiconductor device manufacturing method according to another embodiment of the present invention for achieving the above object comprises the steps of forming a first sacrificial film on the substrate; Forming a second sacrificial film having a slower wet etching rate than the first sacrificial film; Etching the first sacrificial layer to form a first open portion; Forming a barrier film on sidewalls of the primary open portion; And forming a second open part exposing the substrate by etching the second sacrificial film and the etch stop layer under the first open part.

In particular, before the step of forming the first sacrificial film, forming an interlayer insulating film on the substrate; Forming a storage node contact plug penetrating the interlayer insulating film and connected to the substrate; Recessing the interlayer insulating film to a predetermined height; The method may further include forming an etch stop layer on the resultant product including the storage node contact plug.

In addition, the first and second sacrificial films are formed of an oxide film, the first sacrificial film includes PSG (Phosphorus Silicate Glass) or BPSG (Boron Phosphorus Silicate Glass), and the second sacrificial film includes TEOS (Tetra Ethyle Ortho Silicate) Characterized in that.

In the method of manufacturing a semiconductor device according to the embodiment of the present invention described above, after forming the first open portion, a barrier film is formed on the sidewall to prevent damage to the separator, and sufficient transient etching is possible to secure bridge margin between capacitors and poor contact open. It has a protective effect.

In addition, the thickness of the interlayer insulating layer is recessed, and the thickness of the etch stop layer is increased by the thickness, thereby preventing the lower electrode from falling down and preventing the dipout solution from penetrating into the interlayer insulating layer during the dipout.

1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;
2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

((Example 1))

1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 1A, an interlayer insulating film 11 is formed on the substrate 10. The substrate 10 may be a semiconductor (silicon) substrate on which a DRAM process is performed. Before the interlayer insulating film 11 is formed, a predetermined process such as a gate and a bit line is performed on the substrate 10.

The interlayer insulating film 11 is for interlayer insulation between the substrate 10 and the upper layer, and is preferably formed of an oxide film. The oxide film is HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, BSG (Boron Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate) film Glass (FSG), Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film, or any one selected from the group consisting of a laminated film of at least two or more layers can be formed have. Alternatively, the film may be formed by a spin coating method such as a spin on dielectric (SOD) film.

Subsequently, a storage node contact plug 12 connected to the substrate 10 through the interlayer insulating layer 11 is formed. The storage node contact plug 12 forms a contact hole for exposing the substrate 10 by etching the interlayer insulating layer 11, and then filling a conductive material in the contact hole, and then forming a surface of the interlayer insulating layer 11. The exposed target is formed by polishing and etching the conductive material. In this case, the conductive material is formed of any one selected from the group consisting of a transition metal film, a rare earth metal film, an alloy film thereof, and a silicide film thereof. Also, a polysilicon film doped with impurity ions is formed. In addition, the conductive materials may be formed in a laminated structure in which at least two layers are stacked.

As shown in FIG. 1B, the interlayer insulating film 11 (see FIG. 1A) is recessed to a predetermined thickness. The recessed interlayer insulating film 11 (refer to FIG. 1A) is hereinafter referred to as 'interlayer insulating film 11A'.

Accordingly, the storage node contact plug 12 protrudes a predetermined thickness above the interlayer insulating layer 11 (see FIG. 1A). The interlayer insulating film 11A may be recessed through dry etching or wet etching, and the thickness of the interlayer insulating film 11A to be etched may be adjusted to 100 kW to 1500 kW.

Dry etching for recessing the interlayer insulating film 11A may use gas plasma containing fluorine (F), and wet etching may use a mixed chemical containing 0.01% to 10% HF. .

As described above, the interlayer insulating layer 11A is recessed to a predetermined thickness to expose not only the upper side of the storage node contact plug 12 but also the sidewalls to prevent misalignment of subsequent capacitors, and to increase the contact area with the capacitor to reduce the contact resistance. It has the advantage of being.

As illustrated in FIG. 1C, an etch stop layer 12 is formed on a resultant product including the storage node contact plug 12. The etch stop layer 12 may be formed to have a thickness such that the interlayer insulating layer 11A fills the recessed thickness, that is, the protrusion portion of the storage node contact plug 12 is not exposed.

The etch stop layer 12 serves as an etch stop during the formation of a subsequent open portion to prevent loss of the lower layer, and is formed of a material having a selectivity with the interlayer insulating layer 11A and the subsequent sacrificial layer, and the interlayer insulating layer 11A and When the sacrificial layer is an oxide film, the etch stop film 12 is preferably formed of, for example, a nitride film.

In addition, since the thickness of the etch stop layer becomes thicker as the thickness of the interlayer insulating layer 11A is recessed, it is possible to prevent the falling of the lower electrode in the subsequent dip out process, and to prevent the interlayer insulating layer 11A in the dipout process. ) To prevent damage.

As shown in FIG. 1D, the sacrificial layer 14 is formed on the etch stop layer 12. The sacrificial layer 14 provides a space for forming the lower electrode.

The sacrificial layer 14 may be formed of a material having an etch selectivity with respect to the etch stop layer 12, and may be formed of an oxide layer.

In addition, a support layer (not shown) may be further formed on the sacrificial layer 14 to prevent the subsequent lower electrode from falling down.

Subsequently, a mask pattern 15 is formed on the sacrificial layer 14. The mask pattern 15 may be used to etch the sacrificial layer 14. The mask pattern 15 may be formed as a photoresist pattern, and a hard mask such as amorphous carbon may be additionally formed to secure an etching margin before forming the photoresist pattern.

As illustrated in FIG. 1E, the sacrificial layer 14 (see FIG. 1D) is partially etched using the mask pattern 15 as an etch barrier to form the primary open part 16. The thickness of the etched sacrificial layer 14 (see FIG. 1D) is preferably adjusted to be at least half the total thickness of the sacrificial layer 14 (see FIG. 1D).

The etched sacrificial layer 14 (refer to FIG. 1D) is hereinafter referred to as 'sacrificial layer 14A'.

The critical dimension of the sacrificial film 14A, which acts as a separator between the primary openings 16, is that there is no possibility of bridging between subsequent lower electrodes, and the minimum thickness at which subsequent dielectric and upper electrodes can be deposited. It is preferable to adjust so that.

At this time, the line width of the sacrificial film 14A acting as the separator is preferably adjusted to be at least 10 nm.

As shown in FIG. 1F, the barrier conductive film 17 is formed along the step difference of the resultant product including the primary open part 16. The barrier conductive layer 17 is to protect the sacrificial layer 14A used as a separation layer in the subsequent formation of the second open portion, and is preferably formed of a material having an etching selectivity with respect to the sacrificial layer 14A.

In particular, the barrier conductive layer 17 may be formed of the same material as a subsequent lower electrode material. That is, when the lower electrode material is formed of a titanium nitride film (TiN), the barrier conductive film 17 is also formed of a titanium nitride film.

As described above, if the barrier conductive film 17 has an etching selectivity with respect to the sacrificial film 14A and is formed of the same titanium nitride film as the lower electrode material, the damage of the sacrificial film 14A is prevented when forming the second open portion. In addition, since the material is the same as that of the lower electrode material, the removal process may be omitted.

The barrier conductive film 17 is formed to a minimum thickness that can prevent damage to the sacrificial film 14A, and is preferably deposited to several tens of nm or less.

As shown in FIG. 1G, the barrier conductive film 17 (see FIG. 1F) is etched to form a barrier film 17A remaining only on the sidewall of the primary opening 16. Accordingly, the barrier conductive film 17 (see FIG. 1F) formed on the mask pattern 15 on the sacrificial film 14A used as the separator and the bottom of the primary open part 16 is also removed.

As shown in FIG. 1H, the sacrificial layer 14A (see FIG. 1G) is etched at the bottom of the primary opening 16 (see FIG. 1G), and the etch stop layer (see FIG. 1G) is etched to the storage node. A secondary open portion 16A exposing the contact plug 12 is formed.

The sacrificial film 14A (see FIG. 1G) providing the secondary open portion 16A is hereinafter referred to as the 'sacrificial film 14B'.

When forming the secondary open portion 16A, the barrier layer 17A formed on the sidewall of the primary open portion 16 (refer to FIG. 1G) serves as a protective layer to prevent damage to the sacrificial layer 14B and thus is used as a separator. The line width of 14B can be maintained as it is.

In addition, due to the barrier layer 17A, sufficient overetching may be performed when the sacrificial layer 14B is etched, thereby preventing contact opening failure of the secondary opening 16A.

The transient etching proceeds to an etching target of 20% or more of the total height of the sacrificial film 14B. At this time, since the barrier film 17A has sufficient protection of the sacrificial film 14B, the etching property can be performed under excellent etching characteristics. For example, the transient etching may be performed at a high temperature of at least 10 ° C. by applying a low pressure of at least 20 mTorr or less, a high voltage of at least 5000 kPa, and using a C ₄ F ₈ gas.

As described above, the barrier layer 17A is formed on the sidewall of the primary open portion 16 (see FIG. 1G) to protect the sacrificial layer 14B used as the separator, and thus, the secondary open portion ( 16A) has the advantage of preventing contact open failure.

As illustrated in FIG. 1I, an electrode conductive film 18 connected to the storage node contact plug 12 is formed on the front surface of the resultant including the secondary opening 16A. The electrode conductive film 18 is for forming a lower electrode, and may be formed of the same material as the barrier film 17A, and preferably formed of a titanium nitride film.

As shown in FIG. 1J, the lower conductive electrode SN including the barrier layer 17A is etched by etching the conductive layer 18 (see FIG. 1I) for the electrode on the sacrificial layer 14B (see FIG. 1I). Form.

Next, the sacrificial film 14B (see FIG. 1I) is removed. The sacrificial film 14B (see FIG. 1I) is removed by dip out. In particular, the etch stop layer 13A is formed to be as thick as the interlayer insulating layer 11A is recessed to prevent the lowering of the lower electrode SN, and at the same time, the dip-out solution penetrates the interlayer insulating layer 11A. There is an advantage to prevent.

Subsequently, a dielectric film 19 is formed along the resulting product including the cylindrical lower electrode SN formed by removing the sacrificial film 14B (see FIG. 1I), and the upper electrode 20 is formed on the dielectric film 19. To form a cylindrical capacitor.

((Example 2))

2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 2A, an interlayer insulating film 31 is formed on the substrate 30. The substrate 30 may be a semiconductor (silicon) substrate on which a DRAM process is performed. Before the interlayer insulating film 31 is formed, a predetermined process such as a gate and a bit line is performed on the substrate 30.

The interlayer insulating film 31 is for interlayer insulation between the substrate 30 and the upper layer, and is preferably formed of an oxide film. The oxide film is HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, BSG (Boron Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate) film Glass (FSG), Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film, or any one selected from the group consisting of a laminated film of at least two or more layers can be formed have. Alternatively, the film may be formed by a spin coating method such as a spin on dielectric (SOD) film.

Subsequently, a storage node contact plug 32 connected to the substrate 30 through the interlayer insulating layer 31 is formed. The storage node contact plug 32 forms a contact hole to expose the substrate 30 by etching the interlayer insulating layer 31, and then fills a conductive material in the contact hole, and then forms a surface of the interlayer insulating layer 31. The exposed target is formed by polishing and etching the conductive material. In this case, the conductive material is formed of any one selected from the group consisting of a transition metal film, a rare earth metal film, an alloy film thereof, and a silicide film thereof. Also, a polysilicon film doped with impurity ions is formed. In addition, the conductive materials may be formed in a laminated structure in which at least two layers are stacked.

As shown in FIG. 2B, the interlayer insulating film 31 (see FIG. 2A) is recessed to a predetermined thickness. The recessed interlayer insulating film 31 (see FIG. 2A) is hereinafter referred to as 'interlayer insulating film 31A'.

Accordingly, the storage node contact plug 32 protrudes a predetermined thickness above the interlayer insulating layer 31 (see FIG. 2A). The interlayer insulating layer 31A may be recessed through dry etching or wet etching, and the thickness of the interlayer insulating layer 31A to be etched may be adjusted to 100 μs to 1500 μs.

Dry etching for recessing the interlayer insulating film 31A may use gas plasma containing fluorine (F), and wet etching may use a mixed chemical containing 0.01% to 10% HF. .

As described above, the interlayer insulating layer 31A is recessed to a predetermined thickness to expose not only the upper side of the storage node contact plug 32 but also the sidewalls to prevent misalignment of subsequent capacitors, and to increase the contact area with the capacitor to reduce the contact resistance. It has the advantage of being.

As shown in FIG. 2C, an etch stop layer 32 is formed on the resultant including the storage node contact plug 32. The etch stop layer 32 may be formed to have a thickness such that the interlayer insulating layer 31A fills the recessed thickness, that is, the protrusion portion of the storage node contact plug 32 is not exposed.

The etch stop layer 32 serves to stop the loss of the lower layer by forming an etch stop when forming a subsequent open part, and is formed of a material having a selectivity with the interlayer insulating film 31A and the subsequent sacrificial layer, and the interlayer insulating film 31A and When the sacrificial layer is an oxide film, the etch stop film 32 is preferably formed of, for example, a nitride film.

In addition, since the thickness of the etch stop layer becomes thicker as the thickness of the interlayer insulating layer 31A is recessed, the delamination of the lower electrode is prevented in the subsequent dip out process, and the interlayer insulating layer 31A in the dipout process. ) To prevent damage.

As shown in FIG. 2D, the first and second sacrificial films 34 and 35 are stacked on the etch stop layer 32.

The first and second sacrificial films 34 and 35 may be formed of a material having an etching selectivity with respect to the etch stop layer 32, and may be formed of an oxide film. In particular, the second sacrificial film 35 is formed of an oxide film having a wet etching rate lower than that of the first sacrificial film 34.

For example, the first sacrificial layer 34 is formed of a PSG (Phosphorus Silicate Glass) or BPSG (Boron Phosphorus Silicate Glass) film having a relatively high wet etching rate, and the second sacrificial layer 35 has a relatively wet etching rate. It is formed of a slow TEOS (Tetra Ethyle Ortho Silicate) film.

When the first and second sacrificial films 34 and 35 are formed of oxide films having different wet etch rates, it is easy to catch an etch target when forming the first open portion for subsequent barrier film formation, and the wet type when forming the second open portion. By using the difference in etching speed, the lower line width of the open part can be increased.

Subsequently, a supporting film 36 is formed on the second sacrificial film 35. The support layer 36 is to prevent the lower electrode from falling due to surface stress in a subsequent dip out process for forming the cylindrical lower electrode, and the first and second sacrificial layers 34, It is preferable to form a material having an etching selectivity with respect to 35), that is, a material having a slow wet etch rate than the first and second sacrificial films 34 and 35.

The support film 36 is formed of a nitride film and is adjusted to a thickness that can resist surface stress in the dipout process.

Next, the protective film 37 is formed on the support film 36. The passivation layer 37 is to protect the support layer 36 from being damaged in the subsequent planarization process for forming the lower electrode. The passivation layer 37 is formed of a material having an etching selectivity with respect to the support layer 36, for example, an oxide layer. . The passivation layer 37 may be formed to a thickness such that the support layer 36 is not exposed during the planarization process, and may be formed to a thickness of, for example, 100 μs to 1500 μs.

Subsequently, a mask pattern 38 is formed on the protective film 37. The mask pattern 38 is used to etch the passivation layer 37, the support layer 36, and the first and second sacrificial layers 34 and 35 and is formed in the photoresist layer pattern. Before forming the mask pattern 38, a hard mask such as amorphous carbon may be further formed to secure an etching margin.

As shown in FIG. 2E, the protective layer 37 (see FIG. 2D), the support layer 36 (see FIG. 2D), and the second sacrificial layer 35 (see FIG. 2D) are etched using the mask pattern 38 as an etch barrier. The primary open part 39 is formed.

The etched protective film 37 (see FIG. 2D), the supporting film 36 (see FIG. 2D) and the second sacrificial film 35 (see FIG. 2D) are hereinafter referred to as 'protective film 37A', 'supporting film 36A' and The second sacrificial film (35A) is called.

The critical dimension of the second sacrificial layer 35A, which serves as a separator between the primary openings 39, is that there is no possibility of bridging between subsequent lower electrodes, and the minimum that a subsequent dielectric film and upper electrode can be deposited. It is preferable to adjust so that it may become the thickness of.

At this time, the line width of the second sacrificial membrane 35A serving as the separator is preferably adjusted to be at least 10 nm.

As shown in FIG. 2F, the barrier conductive film 40 is formed along the step difference of the resultant product including the primary open part 39. The barrier conductive film 40 is to protect the second sacrificial film 35A used as a separator in the subsequent formation of the second open portion, and provides an etch selectivity with respect to the first and second sacrificial films 34 and 35A. It is preferable to form with the substance which has.

In particular, the barrier conductive layer 40 may be formed of the same material as the material of the subsequent lower electrode. That is, when the lower electrode material is formed of a titanium nitride film (TiN), the barrier conductive film 40 is also formed of a titanium nitride film.

As described above, when the barrier conductive film 40 has an etch selectivity with respect to the first and second sacrificial films 34 and 35A and is formed of the same titanium nitride film as the lower electrode material, the sacrificial film is formed when the second open portion is formed. Damage to 35A is prevented, and the removal process can be omitted since it is the same material as the lower electrode material.

The barrier conductive film 40 is formed to a minimum thickness that can prevent damage to the second sacrificial film 35A, and is preferably deposited to several tens of nm or less.

As shown in FIG. 2G, the barrier conductive film 40 (see FIG. 2F) is etched to form the barrier film 40A remaining only on the sidewall of the primary opening 39. Accordingly, the barrier conductive film 40 (see FIG. 2F) formed on the mask pattern 38 on the bottom of the first open part 39 and on the second sacrificial film 35A used as the separator is also removed.

As shown in FIG. 2H, the first sacrificial layer 34 (see FIG. 2G) is etched on the bottom of the primary opening 39 (see FIG. 2G), and the etch stop layer 33 (see FIG. 2G) is etched. A secondary open portion 39A exposing the storage node contact plug 32 is formed.

The etched first sacrificial film 34 (see FIG. 2G) is hereinafter referred to as 'first sacrificial film 34A'.

When forming the secondary open portion 39A, the barrier film 40A formed on the sidewall of the primary open portion 39 (refer to FIG. 1G) serves as a protective film to prevent damage to the second sacrificial film 35A, and thus used as a separator. The line width of the second sacrificial film 35A can be maintained as it is.

In addition, due to the barrier film 40A, sufficient transient etching is possible when the first sacrificial film 34A is etched, thereby preventing contact opening failure of the second opening 39A.

The transient etching proceeds to an etching target of 20% or more of the total height of the first and second sacrificial films 34A and 35A. At this time, since the barrier film 40A protects the second sacrificial film 35A, the etching characteristics are excellent. You can proceed with the conditions. For example, the transient etching may be performed at a high temperature of at least 10 ° C. by applying a low pressure of at least 20 mTorr or less, a high voltage of at least 5000 kPa, and using a C ₄ F ₈ gas.

As described above, the barrier film 40A is formed on the sidewall of the primary open part 39 (see FIG. 1G) to protect the second sacrificial film 35A used as the separator, and thus, the secondary open is possible because sufficient transient etching is possible. There is an advantage of preventing contact open failure of the portion 39A.

After the second open part 39A is formed, wet cleaning may be performed. Due to the difference in the wet etching speeds of the first and second sacrificial films 34A and 35A during wet cleaning, the sidewalls of the first sacrificial film 34A are etched to increase the lower line width of the second open part 39A. .

As shown in FIG. 2I, the conductive film 41 for electrodes connected to the storage node contact plug 32 is formed on the front surface of the resultant including the secondary open part 39A. The electrode conductive film 41 is for forming the lower electrode, and may be formed of the same material as the barrier film 40A. Preferably, the electrode conductive film 41 is formed of a titanium nitride film.

As shown in FIG. 2J, the conductive layer 41 (see FIG. 2I) for the electrode on the passivation layer 37A (see FIG. 2I) is etched to form a lower electrode SN including the barrier layer 40A. do.

Subsequently, the first and second sacrificial films 34A and 35A (see FIG. 2I) and the protective film 37A and FIG. 2I are removed. The first and second sacrificial films 34A, 35A (see FIG. 2I) and the protective film 37A (see FIG. 2I) are removed by dip out. At this time, the etch stop layer 33A is formed to be as thick as the interlayer insulating layer 31A is recessed to prevent the lowering of the lower electrode SN. There is an advantage to prevent. In addition, during the dip out, the support layer 36A remains as it is to prevent the lower electrode SN from falling over.

Subsequently, a dielectric film 42 is formed along the resultant product including the cylindrical lower electrode SN formed by the removal of the first and second sacrificial films 14B (see FIG. 1I), and the upper electrode (on the dielectric film 42 is formed). 43) to form a cylindrical capacitor.

Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

10 substrate 11 interlayer insulating film
12: storage node contact 13: etch barrier
14: sacrificial film 15: mask pattern
16: primary opening 17A: barrier film
16A: secondary open portion 18: conductive film for electrode
19 dielectric film 20 upper electrode

Claims (15)

Forming a sacrificial layer on the substrate;
Partially etching the sacrificial layer to a predetermined height to form a first open portion;
Forming a barrier film on sidewalls of the primary open portion; And
Forming a second open part exposing the substrate by etching the remaining sacrificial layer under the first open part;
≪ / RTI >
The method of claim 1,
Before forming the sacrificial layer,
Forming an interlayer insulating film on the substrate;
Forming a storage node contact plug penetrating the interlayer insulating film and connected to the substrate;
Recessing the interlayer insulating film to a predetermined height;
Forming an etch stop layer on a resultant product including the storage node contact plug;
A semiconductor device manufacturing method further comprising.
The method of claim 1,
Forming a barrier film on the sidewall of the first open portion,
Forming a barrier conductive film along a step of the resultant product including the first open part; And
Etching back the barrier conductive film and remaining on the sidewalls of the primary opening;
≪ / RTI >
The method of claim 1,
After forming the secondary open portion,
Forming a conductive film for an electrode along a step of the resultant product including the first and second open parts;
Separating the electrode conductive film to form a lower electrode;
Forming a dielectric film along the resultant material including the lower electrode; And
Forming an upper electrode on the dielectric layer
≪ / RTI >
The method of claim 4, wherein
And the barrier film is formed of the same material as the electrode conductive film.
The method of claim 1,
And the barrier film is formed of a titanium nitride film (TiN).
Forming a first sacrificial layer on the substrate;
Forming a second sacrificial film having a slower wet etching rate than the first sacrificial film;
Etching the first sacrificial layer to form a first open portion;
Forming a barrier film on sidewalls of the primary open portion; And
Forming a second open part exposing the substrate by etching the second sacrificial layer and the etch stop layer under the first open part;
≪ / RTI >
The method of claim 7, wherein
Before forming the first sacrificial film,
Forming an interlayer insulating film on the substrate;
Forming a storage node contact plug penetrating the interlayer insulating film and connected to the substrate;
Recessing the interlayer insulating film to a predetermined height;
Forming an etch stop layer on a resultant product including the storage node contact plug;
A semiconductor device manufacturing method further comprising.
The method of claim 7, wherein
Forming a barrier film on the sidewall of the first open portion,
Forming a barrier conductive film along a step of the resultant product including the first open part; And
Etching back the barrier conductive film and remaining on the sidewalls of the primary opening;
≪ / RTI >
The method of claim 7, wherein
After forming the secondary open portion,
Forming a conductive film for an electrode along a step of the resultant product including the first and second open parts;
Separating the electrode conductive film to form a lower electrode;
Forming a dielectric film along the resultant material including the lower electrode; And
Forming an upper electrode on the dielectric layer
A semiconductor device manufacturing method further comprising.
The method of claim 10,
And the barrier film is formed of the same material as the electrode conductive film.
The method of claim 7, wherein
And the barrier film is formed of a titanium nitride film (TiN).
The method of claim 7, wherein
The first sacrificial film and the second sacrificial film are formed of an oxide film. The method of claim 7, wherein
The first sacrificial film includes a phosphosilicate glass (PSG) or boron phosphorus silicate glass (BPSG).
The method of claim 7, wherein
The second sacrificial film includes a TEOS.

Images