KR20100101413A - Test pattern for semiconductor device and for manufacturing the same - Google Patents

Abstract

PURPOSE: A test pattern for a semiconductor device and a manufacturing method of the same is stabilizing the production yield and quality of a semiconductor device by preventing the electrical characteristic change of a transistor according to the alignment error of a recess gate and an active area. CONSTITUTION: A dummy device separation film(110) is formed in a semiconductor substrate to define a plurality of dummy active regions. The test pattern of the semiconductor device comprises one side of a dummy active region and also includes a dummy recess region(120) which is overlapped with the other side of the dummy active region. The test pattern is formed with PN joint diode.

Description

Test pattern for semiconductor device and manufacturing method therefor {Test pattern for Semiconductor Device and for Manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern of a semiconductor device and a method of manufacturing the same, and more particularly, to a test pattern of a semiconductor device and a method of manufacturing the same that can monitor the degree of alignment between semiconductor devices.

As the integration of semiconductor devices progresses, so-called short channel effects are generated in which the threshold voltage (Vt) decreases rapidly as the channel length of the transistor decreases.

Accordingly, a method of implementing a semiconductor device having various types of recess channels capable of securing an effective channel length when manufacturing a device having a thickness of 90 nm or less has been proposed.

Hereinafter, a method of manufacturing a semiconductor device having a conventional recess channel will be briefly described.

First, a trench is formed by etching the device isolation region of a semiconductor substrate partitioned into an active region including a gate formation region and a device isolation region, and then an insulating film is deposited to fill the trench, thereby forming a device isolation layer. Form.

Subsequently, a pad oxide film and a polysilicon film are sequentially formed on the semiconductor substrate including the device isolation film, and then, the polysilicon film and the pad oxide film are etched to form a recess mask that exposes a gate formation region of an active region of the semiconductor substrate. do.

Subsequently, a portion of the gate formation region of the exposed substrate is etched using the recess mask as an etch mask to form a recess gate groove, and the recess mask is removed.

Thereafter, a gate insulating film is deposited on the entire surface of the substrate including the gate groove, and a gate conductive film and a hard mask film are sequentially deposited so as to fill the gate groove on the gate insulating film, and then the hard mask film and the gate conductive film; The gate insulating film is patterned in order to form a recess gate on the gate groove.

Next, spacer layers are formed on both sidewalls of the recess gate, and an ion implantation process is performed in both substrates of the recess gate to form source / drain regions.

Subsequently, a subsequent known process is sequentially performed to fabricate a semiconductor device having a recess channel.

On the other hand, since the one-dimensional channel is formed when the conventional planar type device is applied, the electrical characteristics of the transistor change according to the channel length. However, when manufacturing a semiconductor device having the recess channel, more variables are used. This causes a change in the electrical characteristics of the transistor.

For example, the electrical characteristics of the transistor and the overall characteristics of the semiconductor device change according to variables such as the length of the recess gate channel, the recess depth of the substrate, and the characteristics of the gate insulating layer. Therefore, in order to secure the characteristics and reliability of the semiconductor device, it is very important to accurately measure the cause affecting the electrical characteristics of the transistor.

Recently, according to the trend of higher integration of semiconductor devices, the DRAM device has a three-dimensional structure, and according to the alignment of the recess gate and the active region as well as the channel length of the recess gate and the characteristics of the gate insulating layer, The characteristics are changing a lot. In order to prevent such a change in the characteristics of the transistor, various methods for monitoring the alignment between the devices have been sought. However, there is no test pattern for monitoring the alignment between the recess gate and the active region.

In order to solve the above-mentioned conventional problems, the present invention forms a test pattern for monitoring the alignment of the recess gate and the active region on a semiconductor substrate, thereby forming an electrical circuit of the transistor according to the alignment error of the recess gate and the active region. Provided are a test pattern of a semiconductor device and a method of manufacturing the same, which can prevent characteristic changes and stabilize the yield and quality of a semiconductor device.

The present invention provides a test pattern of a semiconductor device including a dummy device isolation layer formed on a semiconductor substrate to define a plurality of dummy active regions, and a dummy recess gate formed to overlap one side of the dummy active region and one side of the other dummy active region. To provide.

Preferably, the dummy recess gate and the dummy active region may be implemented using a PN junction diode to monitor an alignment state.

Preferably, the PN junction diode is implemented, and the alignment state is monitored by using a current or resistance flowing with a forward voltage applied thereto.

Preferably, the dummy active region is formed of a P-type polysilicon layer.

Preferably, the dummy recess gate is formed of an N-type polysilicon layer.

The present invention also provides a method of forming a dummy device isolation layer that defines a plurality of dummy active regions on a semiconductor substrate, and forming a dummy recess gate to overlap one side of the dummy active region with one side of the dummy active region. It provides a method of manufacturing a test pattern of a semiconductor device comprising.

Preferably, the forming of the dummy recess gate may include the dummy active region and the dummy active mask using a line-shaped dummy recess mask exposing a portion of one side of the dummy active region different from one side of the dummy active region. Etching the dummy device isolation layer to form a dummy recess region, forming a gate insulating layer and a gate conductive layer on the entire surface including the dummy recess region, and using the dummy recess gate mask to form the gate insulating layer and the gate conductive layer. Etching the membrane.

Preferably, the dummy recess gate and the dummy active region may be implemented using a PN junction diode to monitor an alignment state.

Preferably, the PN junction diode is implemented, and the alignment state is monitored by using a current or resistance flowing with a forward voltage applied thereto.

Preferably, the dummy active region is formed of a P-type polysilicon layer.

Preferably, the dummy recess gate is formed of an N-type polysilicon layer.

The present invention forms a test pattern for monitoring the alignment of a recess gate and an active region on a semiconductor substrate, thereby preventing a change in electrical characteristics of the transistor due to an alignment error between the recess gate and the active region, and increasing the yield of a semiconductor device. Has the advantage of stabilizing the quality.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a test pattern and a method of manufacturing the semiconductor device according to the present invention.

Referring to FIG. 1, a bar-type dummy active region 100 is defined to be formed in an island type on a semiconductor substrate, and the dummy device isolation layer 110 is disposed in a region between the dummy active regions 100. Is formed. In this case, the dummy active region 100 and the dummy device isolation layer 110 of the test pattern may be simultaneously formed when the active region (not shown) and the device isolation layer (not shown) of the main chip are formed.

Thereafter, after forming a photoresist film (not shown) on the entire surface including the dummy active region 100 and the dummy device isolation layer 110, one side of the dummy active region 100 and the other side of the dummy active region 100 are formed. A photosensitive film pattern (not shown) is formed by an exposure and development process using a line-shaped dummy recess mask that exposes a portion. The dummy active region 100 and the dummy device isolation layer 110 are etched using the photoresist pattern as a mask to form a dummy recess region (not shown).

Next, a gate insulating film (not shown) and a gate conductive film (not shown) are formed on the entire surface including the dummy recess area, and then the gate conductive film and the gate insulating film are patterned in sequence to dummy on the dummy recess area. The recess gate 120 is formed. In this case, the dummy recess gate 120 preferably has a line shape that overlaps one side of the dummy active region 100 and a part of one side of the other dummy active region 100 at the same time.

Subsequently, after the test pattern including the dummy active region 100 and the dummy recess gate 120 is completed, a voltage is applied to the dummy recess gate 120 and the dummy active region 100 is grounded. Bring it to state and measure the current. Here, the dummy recess gate 120 is formed with an N-type polysilicon layer, and the dummy active region 100 is formed with a P-type polysilicon layer to generate a PN junction diode flow in a forward direction. Here, the alignment of the dummy recess gate 120 and the dummy active region 100 may be checked by measuring the resistance of the PN junction diode in the forward direction. The alignment between the recess gate (not shown) and the active region (not shown) of the main chip may be confirmed using the alignment state of the dummy test patterns 100 and 120. Here, when the resistance between the dummy recess gate 120 and the dummy active region 100 is low, the alignment between the dummy recess gate 120 and the dummy active region 100 is good.

In a subsequent process, a contact 130 is formed in the dummy active region 100, the contact 130 is connected to a bit line (not shown), and a metal wire (not shown) is connected to the bit line to form a pad. Connect to (Pad).

As described above, the present invention forms a test pattern for monitoring the alignment between the recess gate and the active region, and is formed between the main chip and the chip, thereby forming a test pattern of the transistor according to the alignment error of the recess gate and the active region. It has the advantage of preventing electrical property changes and stabilizing the yield and quality of semiconductor devices.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 is a plan view showing a test pattern and a method of manufacturing the semiconductor device according to the present invention.

Claims (11)

A dummy device isolation layer formed on the semiconductor substrate to define a plurality of dummy active regions; And And a dummy recess gate formed to overlap one side of the dummy active region and one side of the other dummy active region. The method of claim 1, And the dummy recess gate and the dummy active region are implemented by a PN junction diode to monitor an alignment state. The method of claim 2, Implemented as the PN junction diode, the test pattern of the semiconductor device, characterized in that for monitoring the alignment state by the current or resistance flowing in the forward voltage is applied. The method of claim 2, And the dummy active region is formed of a P-type polysilicon layer. The method of claim 2, The dummy recess gate is formed of an N-type polysilicon layer. Forming a dummy device isolation layer on the semiconductor substrate, the dummy device isolation layer defining a plurality of dummy active regions; And Forming a dummy recess gate to overlap one side of the dummy active region and one side of the other dummy active region Method of manufacturing a test pattern of a semiconductor device comprising a. The method of claim 6, Forming the dummy recess gate, A dummy recess region is formed by etching the dummy active region and the dummy device isolation layer by using a line-shaped dummy recess mask that exposes a portion of one side of the dummy active region and a portion of the other side of the dummy active region. step; Forming a gate insulating film and a gate conductive film on the entire surface including the dummy recess region; And And etching the gate insulating film and the gate conductive film using a dummy recess gate mask. The method of claim 6, And monitoring the alignment state by implementing the dummy recess gate and the dummy active region with a PN junction diode. The method of claim 6, Implemented as the PN junction diode, the method of manufacturing a test pattern of a semiconductor device, characterized in that for monitoring the alignment state by the current or resistance flowing in the forward voltage is applied. The method of claim 6, And said dummy active region is formed of a p-type polysilicon layer. The method of claim 6, The dummy recess gate is formed of an N-type polysilicon layer.

Images