KR20100123446A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR20100123446A
KR20100123446A KR1020090042670A KR20090042670A KR20100123446A KR 20100123446 A KR20100123446 A KR 20100123446A KR 1020090042670 A KR1020090042670 A KR 1020090042670A KR 20090042670 A KR20090042670 A KR 20090042670A KR 20100123446 A KR20100123446 A KR 20100123446A
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KR
South Korea
Prior art keywords
interlayer insulating
forming
hole
insulating film
region
Prior art date
Application number
KR1020090042670A
Other languages
Korean (ko)
Inventor
김영모
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090042670A priority Critical patent/KR20100123446A/en
Publication of KR20100123446A publication Critical patent/KR20100123446A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

PURPOSE: A method of manufacturing a semiconductor device is provided to improve the reliability of a semiconductor device by suppressing a metal foreign material in etching. CONSTITUTION: A gate line(202) is formed on the top of a semiconductor substrate(200). Gate lines are formed in a die(DI) region. The gate lines are formed in various forms according to the kind of the semiconductor. A junction area is formed on the semiconductor between the gate lines and electrically connects the gate lines.

Description

Method of manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for suppressing generation of impurities in a process of simultaneously etching a die region and a scribe lane region.

The wafer on which the semiconductor device is formed includes a plurality of dies, each of which is divided into a scribe lane. Each die is formed with a semiconductor element, and a scribe lane is formed with a key for aligning a mask used in the manufacturing process of the semiconductor element.

The semiconductor element included in the die and the key included in the scribe lane are executed simultaneously. For example, when the gate lines are formed in the die and the first and second interlayer insulating films are formed, the first and second interlayer insulating films are simultaneously formed in the scribe lane region. Subsequently, when the first metal wiring (for example, the bit line) is formed in the die region, the first metal wiring is also formed in the scribe lane. The reason for forming the first metal wiring in the scribe lane is to adjust the position for forming the mask according to the step of the key formed in the scribe lane area. Specifically, a photoresist film is formed on the layer to be etched and the patterning position is adjusted using an exposure apparatus, wherein the exposure apparatus is configured to control the position of the key formed in the scribe lane. Adjust the position by measuring the step.

Meanwhile, the amount of impurities generated from the metal wiring may increase as the exposed area of the metal wiring (or metal material) formed in the scribe lane area during the etching process is increased during the manufacturing process of the semiconductor device. have. Increasing the amount of impurities may reduce the cleanliness of the interior of the chamber during the subsequent process, and in particular, the electrical characteristics of the semiconductor device may be degraded, thereby reducing the reliability of the semiconductor device.

An object of the present invention is to produce a reticle so that a scribe lane area is not exposed during an exposure process for forming a metal line for bit lines. As a result, the bit line metal wiring is formed only in the die region, and the metal wiring is not formed in the scribe lane region, thereby preventing the exposure of a large area of the metal wiring during the subsequent etching process. have.

In the semiconductor device manufacturing method according to the present invention, a first interlayer insulating film, a second interlayer insulating film, and a third interlayer insulating film are sequentially formed on a die region and a scribe lane region of a wafer. A trench is formed in the third interlayer insulating film formed on the die region. Metal wiring is formed inside the trench. A fourth interlayer insulating film is formed on the metal wiring and the third interlayer insulating film. A method of fabricating a semiconductor device comprising performing an etching process for simultaneously forming a second hole on the die region and a third hole on the scribe lane region.

Prior to forming the first interlayer insulating film, forming gate lines on the die region.

Before forming the third interlayer insulating layer, a first hole is formed in the second and first interlayer insulating layers between the drain select lines among the gate lines, and a drain contact plug is formed by filling a conductive material in the first hole. It includes a step. In this case, the trench is formed to expose the upper portion of the drain contact plug.

Forming the trench may include sequentially forming a hard mask film and a photoresist film on the third interlayer insulating film, and forming an opening in the photoresist film on the die region to form a photoresist pattern. The method may further include etching the exposed hard mask layer and the third interlayer dielectric layer using the photoresist pattern.

The exposure process is performed using a reticle as a mask. The reticle is formed in a structure in which a chrome pattern is laminated on a transparent substrate. In the chrome pattern, an opening is formed only in the die area, and no opening is formed in the scribe lane area.

The etching process for simultaneously forming the second hole and the third hole stops when the metal wiring is exposed to the inside of the second hole.

The difference between the width of the second hole and the width of the third hole is 1:50 to 1: 200, and the metal wiring is a bit line.

In the present invention, since the bit line metal wiring is formed only in the die region and the bit line metal wiring is not formed in the scribe lane region, the metal wiring is exposed to a large area in a subsequent etching process. Can be prevented. As a result, impurities in the metal component may be suppressed during the etching process, thereby improving reliability of the semiconductor device.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

1 is a diagram for explaining a wafer.

The wafer 100 includes a plurality of dies DI formed on which semiconductor devices are formed. Each die DI is divided into a scribe lane SC. The scribe lane SC becomes an area that is finally cut when the manufacturing process of the semiconductor device is completed. That is, among the dies DI and scribe lanes SC formed on the wafer, the portion used for the product becomes the die DI.

Specifically, the die DI includes a plurality of memory cells for storing data and a plurality of transistors for transmitting a driving voltage, and a plurality of metal wires for electrical operation between the memory cells and the transistors. The scribe lane SC includes a key (not shown) for aligning a position of a mask or the like during the manufacturing process of the semiconductor device.

The key is formed at the same time as the semiconductor element is formed in the die area. In particular, the key of the scribe lane SC area is formed in the process of forming the metal line for the bit line in the die area. ) Do not form metal wiring. Specifically, it is as follows.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, some cross sections of the die (DI) region and the scribe lane (SC) region are shown. Specifically, the illustrated die DI area is a cross sectional view of the drain contact area, and the illustrated scribe lane SC area is a cross sectional view of a region where a key is formed.

Gate lines 202 are formed on the semiconductor substrate 200. Gate lines 202 are formed in the die (DI) region. The gate lines may be formed in various structures according to the type of semiconductor device, and in the case of a nonvolatile memory device, a gate insulating film, a floating gate, a dielectric film, and a control gate may be formed in a stacked structure. A junction region 200a is formed in the semiconductor substrate 200 between the gate lines 202 so that the gate lines 202 may be electrically connected to each other.

Since the cross section of the illustrated die area DI is a drain contact region, the gate line 202 is formed with the drain select lines DSL adjacent to each other, and the word lines WL are formed with the respective drain select lines DSL. Formed adjacently.

Referring to FIG. 2B, a first interlayer insulating layer 204 and a second interlayer insulating layer 206 are formed on the semiconductor substrate 200 including the gate lines 202. Specifically, after the first interlayer insulating film 204 is formed, a source contact plug (not shown) is formed in a source contact region not shown in the figure. Next, a second interlayer insulating film is formed over the first interlayer insulating film 204 and the source contact plug (not shown). In this case, the first and second interlayer insulating films 204 and 206 are formed on both the die (DI) region and the scribe lane (SC) region.

Referring to FIG. 2C, a portion of the second and first interlayer insulating layers 206 and 204 formed between the drain select lines (DSLs of FIG. 2A) among the gate lines 202 may be removed to form the first hole H1. Form. The first hole H1 is a drain contact hole and is formed to expose a portion of the junction region 200a between the drain select lines DSL. Next, the first conductive film 208 is filled in the first hole H1. In detail, the first conductive layer 208 is formed to fill the first hole H1, and the second interlayer insulating layer 206 is formed to cover the inside of the first hole H1. Subsequently, a chemical mechanical polishing (CMP) process is performed to expose the second interlayer insulating layer 206 so that the first conductive layer 208 remains only inside the first hole H1. In this case, the first conductive layer 208 may be formed of a conductive material such as tungsten, copper, or polysilicon. In the first hole H1

Referring to FIG. 2D, the first barrier layer 210, the third interlayer insulating layer 212, and the second barrier layer 214 are sequentially disposed on the first conductive layer 208 and the second interlayer insulating layer 206. Form. The first and second barrier films 210 and 214 may be formed of a nitride film. The third interlayer insulating film 212 may be formed of an oxide film.

Referring to FIG. 2E, a first hard mask film for the first hard mask pattern 216 and a photoresist film for the photoresist pattern 218 are sequentially formed on the second barrier film 214. Subsequently, an exposure process is performed to form the photoresist pattern 218 according to the region where the bit line is to be formed. The exposure process is specifically explained as follows.

The exposure process uses a reticle 220 to form the photoresist pattern 218 in a desired pattern. The reticle 220 may be formed in a structure in which a chrome pattern 220b having a desired pattern is stacked on a transparent substrate 220a through which a light source can pass.

In particular, the chrome pattern 220b for forming the bit line pattern forms the opening A only in the die DI area, and the chrome pattern corresponding to the area where the key is to be formed in the scribe line SC area ( 220b) An opening is not formed in the region B. This is because the bit line metal film is formed in a subsequent process according to the pattern formed by the exposure process, so that the metal film is not formed in the scribe lane (SC) region.

The photoresist film is exposed to light using the reticle 220 described above, and the photoresist pattern 218 having the opening pattern for the bit line is formed only in the die region by developing the region irradiated with the light source. Form.

Subsequently, the hard mask layer exposed by the photoresist pattern 218 is etched to form a hard mask pattern 216. A trench TR is formed by sequentially etching the exposed second barrier layer 214, the third interlayer insulating layer 212, and the first barrier layer 210 according to the hard mask pattern 216. In this case, after the hard mask pattern 216 is formed, a cleaning process for removing the photoresist pattern 218 may be further performed.

As a result, the trench TR in which the bit line is to be formed may be formed only in the die region. In this case, the trench TR may be formed to expose the first conductive layer 208. After the formation of the trench TR, a cleaning process for removing the remaining photoresist pattern 218 is performed.

Referring to FIG. 2F, a second conductive layer 222 is filled in the trench TR. Specifically, it is preferable that the second conductive layer 222 is formed so as to cover all the upper portions of the hard mask pattern 216 of FIG. 2E in order to sufficiently fill the inside of the trench TR. Next, a planarization (CMP) process is performed to expose the second barrier layer 214. As a result, the second conductive layer 222 may remain only in the trench TR to form a bit line metal wiring.

In particular, the second conductive layer 222 is formed only in the die (DI) region to become a bit line metal wiring, and does not remain in the scribe lane (SC) region.

Referring to FIG. 2G, a fourth interlayer insulating layer 224 is formed on the second conductive layer 222 and the second barrier layer 214. The fourth interlayer insulating film 224 may be formed of an oxide film.

Referring to FIG. 2H, a second hard mask pattern 226 is formed on the fourth interlayer insulating layer 224. The second hard mask pattern 226 has an opening in each of the die (DI) region and the scribe lane (SC) region, and the opening of the die (DI) region becomes an opening for forming a contact hole and the scribe lane ( The opening of the SC) region becomes an opening for key formation.

An etching process is performed according to the second hard mask pattern 226 to simultaneously form the second hole H2 and the third hole H3 in the fourth interlayer insulating layer 224. Specifically, the etching process is performed by a dry etching process, it is preferable to perform the anisotropic dry etching process to form a desired pattern on the fourth interlayer insulating film 224. In addition, the etching process stops when the second conductive layer 222 is exposed through the second hole H2 in the die area DI, thereby overwriting the third interlayer insulating layer 212 exposed in the scribe lane SC area. Prevent etching. Accordingly, a second hole H2 for a contact hole is formed in the die DI area, and a third hole H3 for a key is formed in the scribe lane SC area.

In particular, the first width W1 of the second hole H2 is very narrow compared to the second width W2 of the third hole H3. In the drawings, for convenience of description, the difference between the first width W1 of the second hole H2 and the second width W2 of the third hole H3 is not large. It has a difference (W1: W2) from: 50 to 1: 200. For example, when the first width W1 of the second hole H2 is 0.2 μm, the second width W2 of the third hole H3 is 20 μm.

As described above, since the area of the second conductive film 222 exposed through the second hole H2 in the die DI area is very narrow compared to that of the scribe line SC area, the generation of impurities in the metal component is not large. As a result, it is possible to suppress an increase in contamination of the wafer including the inside of the chamber.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a diagram for explaining a wafer.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

100: wafer DI: die

SC: scribe lane 200: semiconductor substrate

200a: junction area 202: gate line

204: First interlayer insulating film 206: Second interlayer insulating film

208: first conductive film 210: first barrier film

212: third interlayer insulating film 214: second barrier film

216: first hard mask pattern 218: photoresist pattern

220: reticle 220a: transparent substrate

220b: Chrome pattern 222: Second conductive film

224: fourth interlayer insulating film 226: second hard mask pattern

H1: first hole H2: second hole

H3: 3rd hole TR: trench

Claims (11)

Sequentially forming a first interlayer insulating film, a second interlayer insulating film, and a third interlayer insulating film on a die region and a scribe lane region of the wafer; Forming a trench in the third interlayer insulating film formed on the die region; Forming metal wirings in the trench; Forming a fourth interlayer insulating film on the metal wiring and the third interlayer insulating film; And And etching to simultaneously form a second hole on the die region and a third hole on the scribe lane region. The method of claim 1, wherein before forming the first interlayer insulating film, Forming gate lines on the die region. The method of claim 2, wherein before forming the third interlayer insulating film, Forming a first hole in the second and first interlayer insulating layers between the drain select lines among the gate lines; And And filling a conductive material in the first hole to form a drain contact plug. The method of claim 3, And forming the trench so that an upper portion of the drain contact plug is exposed. The method of claim 1, wherein the forming of the trench comprises: Sequentially forming a hard mask film and a photoresist film on the third interlayer insulating film; Performing an exposure process and a developing process for forming an opening in the photoresist film on the die region to form a photoresist pattern; And And etching the exposed hard mask layer and the third interlayer dielectric layer using the photoresist pattern. The method of claim 5, The exposure process is a semiconductor device manufacturing method using a reticle (reticle) as a mask. The method of claim 6, The reticle is a semiconductor device manufacturing method of forming a structure in which a chromium pattern is laminated on a transparent substrate. The method of claim 7, wherein The chromium pattern has an opening formed only in the die region, the opening is not formed in the scribe lane region. The method of claim 1, The etching process for simultaneously forming the second hole and the third hole is stopped when the metal wiring is exposed to the inside of the second hole. The method of claim 1, And a width difference between the width of the second hole and the width of the third hole is 1:50 to 1: 200. The method of claim 1, The metal wiring is a bit line (bit-line) manufacturing method of a semiconductor device.
KR1020090042670A 2009-05-15 2009-05-15 Method of manufacturing semiconductor device KR20100123446A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011051694A1 (en) 2010-12-06 2012-06-06 Hyundai Motor Co. Variable valve lift

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011051694A1 (en) 2010-12-06 2012-06-06 Hyundai Motor Co. Variable valve lift

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