KR20100096909A - Stack package - Google Patents

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KR20100096909A
KR20100096909A KR1020090015996A KR20090015996A KR20100096909A KR 20100096909 A KR20100096909 A KR 20100096909A KR 1020090015996 A KR1020090015996 A KR 1020090015996A KR 20090015996 A KR20090015996 A KR 20090015996A KR 20100096909 A KR20100096909 A KR 20100096909A
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semiconductor chips
semiconductor
substrate
stack
package
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KR1020090015996A
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Korean (ko)
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조재호
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주식회사 하이닉스반도체
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Publication of KR20100096909A publication Critical patent/KR20100096909A/en

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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A stacked package is provided to reduce the thickness of the entire package by simultaneously implementing a planar vertical structure and a vertical stack structure. CONSTITUTION: A first semiconductor chip(106a,106b) is arranged on the upper side of a substrate in a planar stack form. A first connection member(114) electrically interlinks the first semiconductor chips. A second semiconductor chip is stacked on each first semiconductor chip. A second connection element(116) electrically interlinks the second semiconductor chips. A third connection element mutually and electrically interlinks the second semiconductor chips, the first semiconductor chips, and substrates. The first semiconductor chips and the second semiconductor chips are arranged to be spaced apart, respectively.

Description

스택 패키지{STACK PACKAGE}Stack Package {STACK PACKAGE}

본 발명은 스택 패키지에 관한 것으로, 보다 상세하게는, 수직적(Vertical) 스택 구조와 수평적(Planar) 스택 구조를 동시에 구현한 스택 패키지에 관한 것이다.The present invention relates to a stack package, and more particularly, to a stack package which simultaneously implements a vertical stack structure and a horizontal stack structure.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전 되고 있다. 예컨대, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장 작업의 효율성 및 실장 후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다. In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technologies for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

또한, 전기·전자 제품의 소형화와 더불어 고 성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. In addition, as miniaturization of electric and electronic products and high performance are required, various technologies for providing a high capacity semiconductor module have been researched and developed.

고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. As a method for providing a high capacity semiconductor module, there is a high integration of a memory chip, which can be realized by integrating a larger number of cells in a limited space of the semiconductor chip.

그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선 폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 스택(Stack) 기술이 제안되었다. However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

상기와 같은 스택 기술은 스택 된 2개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징 된 2개의 단품의 패키지를 스택하는 방법이 있다. 그러나, 상기와 같이 2개의 단품의 패키지를 스택하는 방법은 전기·전자 제품의 소형화되는 추세와 더불어 그에 따른 반도체 패키지의 높이의 한계가 있다.The stack technology described above includes a method of embedding two stacked chips in one package and stacking two packaged packages. However, the method of stacking two single packages as described above has a limit of height of the semiconductor package with the trend of miniaturization of electrical and electronic products.

따라서, 하나의 패키지의 2∼3개의 반도체 칩들을 탑재시키는 스택 패키지(Stack Package) 및 멀티 칩 패키지(Multi Chip Package)에 대한 연구가 최근 들어 활발하게 진행되고 있다. Therefore, research on a stack package and a multi chip package in which two or three semiconductor chips of one package are mounted has been actively conducted in recent years.

그러나, 자세하게 도시하고 설명하지는 않았지만, 전술한 종래 기술의 경우에는, 기판 상에 반도체 칩들이 수직적으로 스택됨에 따라 반도체 칩과 기판 간을 부착시키거나, 또는, 수직적으로 스택되는 상기 각 반도체 칩 간을 부착시키는 접착층의 두께와 상기 반도체 칩 자체의 두께 마진으로 인해 전체 패키지의 두께를 증가시게 된다.However, although not shown and described in detail, in the above-described prior art, as the semiconductor chips are vertically stacked on the substrate, the semiconductor chips and the substrate are attached to each other, or between the vertically stacked semiconductor chips. The thickness of the entire package is increased due to the thickness of the adhesive layer to be attached and the thickness margin of the semiconductor chip itself.

예컨대, 상기와 같은 접착층 한 개의 두께가 약 150㎛이고, 상기 반도체 칩의 각 두께가 50㎛인 경우에 있어서, 상기와 같은 접착층 및 상기 반도체 칩을 8개 스택하여 스택 패키지를 제작할 경우, 전체 패키지의 두께는 약 1.5㎜가 되게 된다.For example, in the case where the thickness of one adhesive layer is about 150 μm and the thickness of each of the semiconductor chips is 50 μm, when the stack of eight adhesive layers and the semiconductor chips is stacked to manufacture a stack package, the entire package The thickness of will be about 1.5 mm.

이와 같이 상기와 같은 접착층 두께 및 반도체 칩 자체의 두께로 인해 전체 패키지의 두께가 증가하게 되며, 더욱이, 이러한 두께는 양산성 측면에서 패키지로 서의 가치가 없게 된다.As described above, the thickness of the entire package is increased due to the thickness of the adhesive layer and the thickness of the semiconductor chip itself, and furthermore, such thickness is not valuable as a package in terms of mass productivity.

본 발명은 용량을 향상시킴과 아울러, 전체 패키지의 두께를 감소시킨 스택 패키지를 제공한다.The present invention provides a stack package that improves capacity and reduces the thickness of the overall package.

본 발명의 실시예에 따른 스택 패키지는, 기판; 상기 기판 상면에 플래나(Planar) 스택 타입으로 배치된 적어도 둘 이상의 제1반도체 칩들; 상기 제1반도체 칩들 간을 전기적으로 연결하는 제1접속 부재; 상기 각 제1반도체 칩들 상에 스택된 적어도 하나 이상의 제2반도체 칩들; 상기 제2반도체 칩들 간을 전기적으로 연결하는 제2접속 부재; 및 상기 제2반도체 칩들, 제1반도체 칩들 및 기판 간을 상호 전기적으로 연결하는 제3접속 부재;를 포함한다.Stack package according to an embodiment of the present invention, the substrate; At least two first semiconductor chips disposed in a planar stack type on an upper surface of the substrate; A first connection member electrically connecting the first semiconductor chips; At least one second semiconductor chip stacked on each of the first semiconductor chips; A second connection member electrically connecting the second semiconductor chips; And a third connection member electrically connecting the second semiconductor chips, the first semiconductor chips, and the substrate to each other.

상기 제1반도체 칩들 및 상기 제2반도체 칩들 간은 각각 서로 이격 배치된 것을 특징으로 한다.The first semiconductor chips and the second semiconductor chips may be spaced apart from each other.

상기 제1반도체 칩들과 기판 사이 및 제1반도체 칩들과 제2반도체 칩들 사이에 각각 개재된 접착 부재를 더 포함한다.The semiconductor device may further include an adhesive member interposed between the first semiconductor chips and the substrate and between the first semiconductor chips and the second semiconductor chips.

상기 제1, 제2 및 제3접속 부재는 각각 전도성 폴리머(Polymer)를 포함한다.The first, second and third connection members each include a conductive polymer.

상기 제1, 제2 및 제3접속 부재는 각각 전도성 테이프를 포함한다.The first, second and third connection members each comprise a conductive tape.

상기 제3접속 부재는 관통 전극을 포함한다.The third connecting member includes a through electrode.

상기 제1 및 제2반도체 칩들은 각각 동일하거나 또는 서로 상이한 종류로 이 루어진 것을 특징으로 한다.Each of the first and second semiconductor chips may be the same or different types.

본 발명은 내부에 다수의 반도체 칩 간을 스택하는 스택 패키지 형성시, 플래나 구조 및 수직적 스택 구조를 동시에 구현함으로써, 종래의 수직적 구조만을 갖는 스택 패키지보다 그의 용량을 향상시키면서도, 전체 패키지의 두께를 감소시킬 수 있다.According to the present invention, when a stack package stacking a plurality of semiconductor chips therein, the planar structure and the vertical stack structure are simultaneously implemented, thereby improving the capacity of the entire package while improving its capacity than the stack package having only the conventional vertical structure. Can be reduced.

이하에서는 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1은 본 발명의 실시예에 따른 스택 패키지를 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.1 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도시된 바와 같이 본 발명의 실시예에 따른 스택 패키지(100)는, 기판(102), 다수의 제1반도체 칩들(106a, 106b), 제1접속 부재(114), 다수의 제2반도체 칩들(110a, 110b), 제2접속 부재(116), 제3접속 부재(118), 봉지 부재(120) 및 외부 접속 단자(122)를 포함한다.As shown, the stack package 100 according to the embodiment of the present invention may include a substrate 102, a plurality of first semiconductor chips 106a and 106b, a first connection member 114, and a plurality of second semiconductor chips ( 110a, 110b, a second connection member 116, a third connection member 118, an encapsulation member 120, and an external connection terminal 122.

기판(102)은 상면에 배치된 다수의 본드핑거(104)를 포함한다.The substrate 102 includes a plurality of bond fingers 104 disposed on the top surface.

또한, 이러한 기판(102)의 상면에는 본드핑거(104)를 노출시키는 접착제(124)가 부착된다.In addition, an adhesive 124 exposing the bond finger 104 is attached to the upper surface of the substrate 102.

제1반도체 칩들(106a, 106b)은 이러한 기판(102) 상면에 부착된 접착제(124)의 상면에 적어도 둘 이상 배치된다.At least two first semiconductor chips 106a and 106b are disposed on an upper surface of the adhesive 124 attached to the upper surface of the substrate 102.

이때, 이러한 제1반도체 칩들(106a, 106b)은 서로 이격되거나 또는 맞닿도록 플래나(Planar) 스택 타입으로 배치된다.In this case, the first semiconductor chips 106a and 106b may be arranged in a planar stack type to be spaced apart from or in contact with each other.

또한, 이러한 제1반도체 칩들(106a, 106b)은 각각 상면에 배치된 제1본딩패드들(108a, 108b)을 포함한다.In addition, each of the first semiconductor chips 106a and 106b includes first bonding pads 108a and 108b disposed on an upper surface thereof.

이때, 이러한 제1본딩패드들(108a, 108b)은 에지(Edge) 패드 타입을 포함할 수 있으며, 또한, 이러한 제1본딩패드들(108a, 108b)이 센터(Center) 패드 타입일 경우, 재배선(RDL : Redistrubution Layer)이 이용되어 칩 가장자리 부분으로 배치될 수 있다.In this case, the first bonding pads 108a and 108b may include an edge pad type, and when the first bonding pads 108a and 108b are a center pad type, cultivation may be performed. Lines (RDLs) can be used to place the chip edges.

제1접속 부재(114)는 서로 이격되거나 또는 맞닿도록 배치된 제1반도체 칩들(106a, 106b)의 내측에 배치된 각 제1본딩패드들(108a, 108b) 간을 전기적으로 연결한다.The first connection member 114 electrically connects the first bonding pads 108a and 108b disposed inside the first semiconductor chips 106a and 106b spaced apart from or in contact with each other.

여기서, 이러한 제1반도체 칩들(106a, 106b)의 각 제1본딩패드들(108a, 108b) 간을 전기적으로 연결하는 제1접속 부재(114)는 예를 들면 전도성 폴리머(Polymer)를 포함한다.Here, the first connection member 114 electrically connecting the first bonding pads 108a and 108b of the first semiconductor chips 106a and 106b includes, for example, a conductive polymer.

제2반도체 칩들(110a, 110b)은 접착제(124)를 매개로 하여 이러한 각각의 제1반도체 칩들(106a, 106b) 상에 적어도 둘 이상 배치된다.At least two second semiconductor chips 110a and 110b are disposed on each of the first semiconductor chips 106a and 106b through the adhesive 124.

이때, 이러한 제2반도체 칩들(110a, 110b)은 제1반도체 칩들(106a, 106b) 상에 부착된 접착제(124)의 상면에 서로 이격되거나 또는 맞닿도록 수직적인 스택 타입으로 배치된다.In this case, the second semiconductor chips 110a and 110b may be disposed in a vertical stack so as to be spaced apart or abutted on top surfaces of the adhesive 124 attached on the first semiconductor chips 106a and 106b.

또한, 이러한 제2반도체 칩들(110a, 110b)은 각각 상면에 배치된 제2본딩패 드들(112a, 112b)을 포함한다.In addition, the second semiconductor chips 110a and 110b include second bonding pads 112a and 112b disposed on an upper surface thereof, respectively.

이때, 이러한 제2본딩패드들(112a, 112b)은 에지(Edge) 패드 타입을 포함할 수 있으며, 또한, 이러한 제2본딩패드들(112a, 112b)은 센터(Center) 패드 타입일 경우, 재배선(RDL : Redistrubution Layer)이 이용되어 칩 가장자리 부분으로 배치될 수 있다.In this case, the second bonding pads 112a and 112b may include an edge pad type, and when the second bonding pads 112a and 112b are a center pad type, cultivation may be performed. Lines (RDLs) can be used to place the chip edges.

한편, 스택된 제1반도체 칩들(106a, 106b) 및 제2반도체 칩들(110a, 110b)은 각각 동일하거나 또는 서로 상이한 종류의 칩으로 이루어질 수 있다.Meanwhile, the stacked first semiconductor chips 106a and 106b and the second semiconductor chips 110a and 110b may be made of the same or different kinds of chips, respectively.

제2접속 부재(116)는 서로 이격되거나 또는 맞닿도록 배치된 제2반도체 칩들(110a, 110b)의 내측의 각 제2본딩패드들(112a, 112b) 간을 전기적으로 연결한다.The second connection member 116 electrically connects each of the second bonding pads 112a and 112b inside the second semiconductor chips 110a and 110b to be spaced apart from or in contact with each other.

여기서, 이러한 제2반도체 칩들(110a, 110b)의 각 제2본딩패드들(112a, 112b) 간을 전기적으로 연결하는 제2접속 부재(116)는 예를 들면 전도성 폴리머(Polymer)를 포함한다.Here, the second connection member 116 electrically connecting the respective second bonding pads 112a and 112b of the second semiconductor chips 110a and 110b includes, for example, a conductive polymer.

제3접속 부재(118)는 이러한 제2반도체 칩들(110a, 110b)의 제2본딩패드들(112a, 112b), 제1반도체 칩들(106a, 106b)의 제1본딩패드들(108a, 108b) 및 기판(102)의 본드핑거(104) 간을 상호 전기적으로 연결한다.The third connection member 118 may include the second bonding pads 112a and 112b of the second semiconductor chips 110a and 110b and the first bonding pads 108a and 108b of the first semiconductor chips 106a and 106b. And the bond fingers 104 of the substrate 102 are electrically connected to each other.

이때, 이러한 제2반도체 칩들(110a, 110b)의 제2본딩패드들(112a, 112b), 제1반도체 칩들(106a, 106b)의 제1본딩패드들(108a, 108b) 및 기판(102)의 본드핑거(104) 간을 상호 전기적으로 연결하는 제3접속 부재(118)는 전술한 제1 및 제2접속 부재(114, 116)와 동일하게 전도성 폴리머(Polymer)를 포함한다.At this time, the second bonding pads 112a and 112b of the second semiconductor chips 110a and 110b, the first bonding pads 108a and 108b of the first semiconductor chips 106a and 106b and the substrate 102 may be formed. The third connecting member 118 electrically connecting the bond fingers 104 to each other includes the same conductive polymer as the first and second connecting members 114 and 116 described above.

한편, 제3접속 부재(118)는 각 반도체 칩들(106a, 106b, 110a, 110b)를 관통하여 기판(102)의 본드핑거(104)와 전기적으로 연결되는 관통 전극(126)을 포함할 수 있다.The third connection member 118 may include a through electrode 126 that penetrates through the semiconductor chips 106a, 106b, 110a, and 110b and is electrically connected to the bond finger 104 of the substrate 102. .

봉지 부재(120)는 제1반도체 칩들(106a, 106b), 제2반도체 칩들(110a, 110b) 및 제1, 제2 및 제3접속 부재(114, 116, 118)를 외부의 스트레스로부터 보호하기 위해 이러한 제1반도체 칩들(106a, 106b), 제2반도체 칩들(110a, 110b) 및 제1, 제2 및 제3접속 부재(114, 116, 118)를 포함하는 기판(102)의 상면을 덮도록 밀봉된다.The encapsulation member 120 protects the first semiconductor chips 106a and 106b, the second semiconductor chips 110a and 110b, and the first, second and third connection members 114, 116 and 118 from external stress. To cover the top surface of the substrate 102 including the first semiconductor chips 106a and 106b, the second semiconductor chips 110a and 110b, and the first, second and third connection members 114, 116 and 118. To be sealed.

이러한 봉지 부재(120)는 예를 들면 EMC(Epoxy Molding Compound)를 포함한다.The encapsulation member 120 includes, for example, an epoxy molding compound (EMC).

외부 접속 단자(122)는 기판(102) 타면의 볼 랜드(도시안됨)에 실장 수단으로서 다수 개 부착되며, 이러한 실장 수단으로서 다수 개 부착된 외부 접속 단자(122)는 예를 들면 솔더 볼을 포함한다.A plurality of external connection terminals 122 are attached to the ball lands (not shown) on the other surface of the substrate 102 as mounting means, and the external connection terminals 122 attached to a plurality of such mounting means include solder balls, for example. do.

한편, 도 2는 본 발명의 다른 실시예에 따른 스택 패키지를 설명하기 위해 도시한 단면도로서, 본 발명의 다른 실시예에 따른 스택 패키지(200)는, 전술한 본 발명의 실시예에 따른 스택 패키지(100)와 거의 유사하며, 다만, 각 반도체 칩들(206a, 210b) 간 및 각 반도체 칩들(206a, 210b)과 기판(202) 간을 전기적으로 연결하는 제1, 제2 및 제3접속 부재(224)가 전도성 테이프로 형성될 수 있다.2 is a cross-sectional view illustrating a stack package according to another embodiment of the present invention. The stack package 200 according to another embodiment of the present invention is a stack package according to the above-described embodiment of the present invention. The first, second and third connecting members electrically connecting the semiconductor chips 206a and 210b and between the semiconductor chips 206a and 210b and the substrate 202 are similar to those of the substrate 100. 224 may be formed of a conductive tape.

또한, 도 3은 본 발명의 또 다른 실시예에 따른 스택 패키지를 설명하기 위해 도시한 단면도로서, 본 발명의 다른 실시예에 따른 스택 패키지(300)는, 전술한 본 발명의 실시예에 따른 스택 패키지(100) 및 본 발명의 다른 실시예에 따른 스택 패키지(200)와 거의 유사하며, 다만, 각 반도체 칩들(306a, 310b)과 기판(302) 간을 전기적으로 연결하는 제3접속 부재가 각 반도체 칩들(306a, 310b) 내에 형성된 관통 전극(326)을 포함할 수 있다.3 is a cross-sectional view illustrating a stack package according to another embodiment of the present invention. The stack package 300 according to another embodiment of the present invention is a stack according to the above-described embodiment of the present invention. Almost similar to the package 100 and the stack package 200 according to another embodiment of the present invention, except that each of the third connection members electrically connecting the semiconductor chips 306a and 310b to the substrate 302. It may include a through electrode 326 formed in the semiconductor chips (306a, 310b).

이하의 나머지 구성 요소는 전술한 본 발명의 실시예에 따른 스택 패키지(100)와 동일하며, 여기서는 그 설명은 생략하도록 한다.The remaining components are the same as the stack package 100 according to the embodiment of the present invention described above, the description thereof will be omitted.

전술한 바와 같이 본 발명은, 상기와 같이 플래나 구조 및 수직적 구조를 동시에 내부에 구현하여 스택 패키지를 형성함으로써, 종래의 수직적 구조만을 갖는 스택 패키지보다 그의 용량을 향상시킬 수 있음과 아울러, 전체 패키지의 두께를 감소시킬 수 있다.As described above, the present invention, by implementing a planar structure and a vertical structure at the same time as described above to form a stack package, it is possible to improve its capacity than the stack package having a conventional vertical structure, as well as the entire package Can reduce the thickness.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 본 발명의 실시예에 따른 스택 패키지를 설명하기 위해 도시한 단면도.1 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도 2는 본 발명의 다른 실시예에 따른 스택 패키지를 설명하기 위해 도시한 단면도.2 is a cross-sectional view illustrating a stack package according to another embodiment of the present invention.

도 3은 본 발명의 또 다른 실시예에 따른 스택 패키지를 설명하기 위해 도시한 단면도.3 is a cross-sectional view illustrating a stack package according to another embodiment of the present invention.

Claims (7)

기판;Board; 상기 기판 상면에 플래나(Planar) 스택 타입으로 배치된 적어도 둘 이상의 제1반도체 칩들;At least two first semiconductor chips disposed in a planar stack type on an upper surface of the substrate; 상기 제1반도체 칩들 간을 전기적으로 연결하는 제1접속 부재;A first connection member electrically connecting the first semiconductor chips; 상기 각 제1반도체 칩들 상에 스택된 적어도 하나 이상의 제2반도체 칩들;At least one second semiconductor chip stacked on each of the first semiconductor chips; 상기 제2반도체 칩들 간을 전기적으로 연결하는 제2접속 부재; 및A second connection member electrically connecting the second semiconductor chips; And 상기 제2반도체 칩들, 제1반도체 칩들 및 기판 간을 상호 전기적으로 연결하는 제3접속 부재;A third connection member electrically connecting the second semiconductor chips, the first semiconductor chips, and the substrate to each other; 를 포함하는 것을 특징으로 하는 스택 패키지.Stack package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제1반도체 칩들 및 상기 제2반도체 칩들 간은 각각 서로 이격 배치된 것을 특징으로 하는 스택 패키지.And the first semiconductor chip and the second semiconductor chip are spaced apart from each other. 제 1 항에 있어서,The method of claim 1, 상기 제1반도체 칩들과 기판 사이 및 제1반도체 칩들과 제2반도체 칩들 사이에 각각 개재된 접착 부재를 더 포함하는 것을 특징으로 하는 스택 패키지.And a bonding member interposed between the first semiconductor chips and the substrate and between the first semiconductor chips and the second semiconductor chips, respectively. 제 1 항에 있어서,The method of claim 1, 상기 제1, 제2 및 제3접속 부재는 각각 전도성 폴리머(Polymer)를 포함하는 것을 특징으로 하는 스택 패키지.The first, second and third connection member, each stack package, characterized in that it comprises a conductive polymer (Polymer). 제 1 항에 있어서,The method of claim 1, 상기 제1, 제2 및 제3접속 부재는 각각 전도성 테이프를 포함하는 것을 특징으로 하는 스택 패키지.And the first, second and third connection members each comprise a conductive tape. 제 1 항에 있어서,The method of claim 1, 상기 제3접속 부재는 관통 전극을 포함하는 것을 특징으로 하는 스택 패키지.And the third connecting member includes a through electrode. 제 1 항에 있어서,The method of claim 1, 상기 제1 및 제2반도체 칩들은 각각 동일하거나 또는 서로 상이한 종류로 이루어진 것을 특징으로 하는 스택 패키지.And the first and second semiconductor chips are the same or different types.
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