KR20020042958A - Stack chip package - Google Patents
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- KR20020042958A KR20020042958A KR1020000072322A KR20000072322A KR20020042958A KR 20020042958 A KR20020042958 A KR 20020042958A KR 1020000072322 A KR1020000072322 A KR 1020000072322A KR 20000072322 A KR20000072322 A KR 20000072322A KR 20020042958 A KR20020042958 A KR 20020042958A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로, 더욱 상세하게는 두 개 이상의 반도체 칩이 적층된 적층 칩 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a stacked chip package in which two or more semiconductor chips are stacked.
일반적인 반도체 웨이퍼(semiconductor wafer)는 평면이기 때문에, 한 평면내에 반도체 소자의 집적도를 향상시키는 데 한계가 있다. 또한 집적도를 향상시키는 데도 많은 설비투자가 필요한 실정이다. 따라서, 현재 반도체 패키지의 고집적화를 위하여 많은 회사들 및 학계에서 고밀도 3차원 칩, 3차원 패키지의 적층 방법을 연구하고 있다. 즉, 반도체 웨이퍼를 개별 반도체 소자로 절삭한 이후에 집적도를 높이는 방법을 연구하고 있다.Since a typical semiconductor wafer is a plane, there is a limit to improving the integration degree of a semiconductor device in one plane. In addition, a lot of facility investment is required to improve the density. Therefore, many companies and academia are investigating stacking method of high density 3D chip and 3D package for high integration of semiconductor package. That is, a method of increasing the degree of integration after cutting a semiconductor wafer into individual semiconductor devices is being studied.
복수개의 단위 패키지를 3차원으로 적층하여 제조된 3차원 적층 패키지는 고집적화를 이룰 수 있는 반면에, 두께가 두꺼워 반도체 제품의 경박단소화에 대한 대응성이 떨어지는 문제점을 안고 있다.The three-dimensional stacked package manufactured by stacking a plurality of unit packages in three dimensions may achieve high integration, but has a problem in that the thickness thereof is inferior to light and thin shortening of a semiconductor product.
복수개의 반도체 소자를 3차원으로 적층하여 제조된 3차원 적층 칩 패키지는 고집적화를 이룰 수 있는 동시에 반도체 제품의 경박단소화에 대한 대응성도 뛰어나다.The three-dimensional stacked chip package manufactured by stacking a plurality of semiconductor devices in three dimensions can achieve high integration and excellent response to light and thin reduction of semiconductor products.
종래기술의 일 실시예에 따른 두 개의 반도체 칩(12, 13)이 적층된 적층 칩패키지(10)를 도 1을 참조하여 설명하면, 적층 칩 패키지(10)는 기판(14)의 두께를 활용한 반도체 패키지로서, 기판(14)의 중심 부분에 형성된 칩 실장 홈(15)에 두 개의 반도체 칩(12, 13)이 차례로 적층된 구조를 갖는다.Referring to FIG. 1, a stacked chip package 10 in which two semiconductor chips 12 and 13 are stacked, according to an exemplary embodiment, the stacked chip package 10 utilizes a thickness of a substrate 14. As one semiconductor package, two semiconductor chips 12 and 13 are sequentially stacked in the chip mounting groove 15 formed in the central portion of the substrate 14.
이와 같은 적층 칩 패키지(10)는 칩 실장 홈(15)이 형성된 기판(14)의 상부면에 수지 봉합부(16)가 형성되기 때문에, 패키지의 두께가 증가하고 패키지 휨(warpage)이 발생될 우려가 크다.Since the resin encapsulation portion 16 is formed on the upper surface of the substrate 14 on which the chip mounting groove 15 is formed, the stacked chip package 10 may increase the thickness of the package and generate package warpage. There is great concern.
전술된 바와 같은 패키지 두께의 증가 및 패키지 휨을 억제할 수 적층 칩 패키지(20)가 도 2에 도시되어 있다. 즉, 적층 칩 패키지(20)는 기판(24)의 중심부분에 칩 실장 구멍(25)을 형성하고, 그 칩 실장 구멍(25)에 두 개의 반도체 칩(22, 23)의 배면이 서로 마주보도록 적층된 구조를 갖는다. 그리고, 두 개의 반도체 칩(22, 23)은 접착제(27)에 의해 부착된다.A multilayer chip package 20 is shown in FIG. 2 that can suppress the increase in package thickness and package warpage as described above. That is, the stacked chip package 20 forms chip mounting holes 25 in the central portion of the substrate 24, and the rear surfaces of the two semiconductor chips 22 and 23 face each other in the chip mounting holes 25. It has a laminated structure. Then, the two semiconductor chips 22 and 23 are attached by the adhesive 27.
이와 같은 적층 칩 패키지(20)는 두 반도체 칩(22, 23) 사이의 접착 공정이 복잡하고, 반도체 칩 접착 공정과 와이어 본딩 공정에서 지지되는 반도체 칩(22)의 활성면이 손상될 우려가 크다. 즉, 하나의 반도체 칩(22; 이하, '제 1 칩'이라 한다)에 대한 와이어 본딩 공정이 완료된 이후에, 제 1 칩(22)에 새로운 반도체 칩(23; 이하, '제 2 칩'이라 한다)을 부착하는 공정과 와이어 본딩 공정을 진행할 때 지지되는 면이 제 1 칩(22)의 활성면이기 때문에, 제 1 칩(22)의 활성면을 지지하는 지지수단에 의해 활성면이 손상될 수 있다.Such a laminated chip package 20 has a complicated bonding process between the two semiconductor chips 22 and 23, and the active surface of the semiconductor chip 22 supported in the semiconductor chip bonding process and the wire bonding process is likely to be damaged. . That is, after the wire bonding process for one semiconductor chip 22 (hereinafter, referred to as a “first chip”) is completed, a new semiconductor chip 23 (hereinafter referred to as “second chip”) is added to the first chip 22. Since the surface supported during the process of attaching and wire bonding is the active surface of the first chip 22, the active surface may be damaged by the support means for supporting the active surface of the first chip 22. Can be.
그리고, 제 1 칩(22) 및 제 2 칩(22)은 기판(24)에 부착되지 못하고 떠 있는 구조를 갖기 때문에, 제 1 칩(22)에 대한 와이어 본딩 공정, 제 2 칩(23)에 대한부착 공정, 와이어 본딩 공정 등의 패키지 조립 공정시 취급이 용이하지 못하고, 종래의 칩 부착 기술을 사용할 수 없는 문제점도 안고 있다.Since the first chip 22 and the second chip 22 have a floating structure that cannot be attached to the substrate 24, the wire bonding process for the first chip 22 and the second chip 23 are performed. There is also a problem in that handling is not easy in a package assembly process such as a Korean attaching process or a wire bonding process, and a conventional chip attaching technique cannot be used.
따라서, 본 발명의 목적은 기판의 두께를 효과적으로 이용하여 적층 칩 패키지의 두께를 줄일 수 있는 있고, 종래의 칩 실장 기술을 그대로 이용할 수 있도록 하는 데 있다.Accordingly, it is an object of the present invention to reduce the thickness of a laminated chip package by effectively using the thickness of the substrate, and to use the conventional chip mounting technology as it is.
도 1은 종래기술의 일 실시예에 따른 두 개의 반도체 칩이 적층된 적층 칩 패키지를 보여주는 단면도,1 is a cross-sectional view showing a laminated chip package in which two semiconductor chips are stacked according to an embodiment of the prior art;
도 2는 종래기술의 다른 실시예에 따른 두 개의 반도체 칩이 적층된 적층 칩 패키지를 보여주는 단면도,2 is a cross-sectional view showing a laminated chip package in which two semiconductor chips are stacked according to another embodiment of the prior art;
도 3은 본 발명의 제 1 실시예에 따른 두 개의 반도체 칩이 적층된 적층 칩 패키지를 보여주는 단면도,3 is a cross-sectional view illustrating a stacked chip package in which two semiconductor chips according to a first embodiment of the present invention are stacked;
도 4는 본 발명의 제 2 실시예에 따른 두 개의 반도체 칩이 적층된 적층 칩 패키지를 보여주는 단면도,4 is a cross-sectional view illustrating a stacked chip package in which two semiconductor chips according to a second embodiment of the present invention are stacked;
도 5는 본 발명의 제 3 실시예에 따른 다수개의 반도체 칩이 적층된 적층 칩 패키지를 보여주는 단면도이다.5 is a cross-sectional view illustrating a stacked chip package in which a plurality of semiconductor chips according to a third embodiment of the present invention is stacked.
* 도면의 주요 부분에 대한 설명 *Description of the main parts of the drawing
31, 51, 71 : 기판 32, 52, 72 : 제 1 칩31, 51, 71: substrate 32, 52, 72: the first chip
33, 43, 73, 63, 73, 83 : 접착제33, 43, 73, 63, 73, 83: adhesive
34, 44, 54, 64, 74, 84 : 본딩 와이어34, 44, 54, 64, 74, 84: bonding wire
35, 55, 75 : 제 1 칩 실장 구멍 35a, 55a, 75a : 단차면35, 55, 75: first chip mounting holes 35a, 55a, 75a: stepped surface
36, 56, 76 : 수지 봉합부 40, 60, 80 : 적층 칩 패키지36, 56, 76: resin seal 40, 60, 80: laminated chip package
42, 62, 82 : 제 2 칩 45, 65, 85 : 제 2 칩 실장 구멍42, 62, 82: 2nd chip 45, 65, 85: 2nd chip mounting hole
47, 57, 97 : 솔더볼47, 57, 97: Solder Ball
상기 목적을 달성하기 위하여, 적층 칩 패키지로서, 상부면과, 상기 상부면에 반대되는 하부면을 가지며, 상기 상부면의 중심 부분을 관통하여 단차지게 칩 실장 구멍이 형성된 기판과; 상기 기판의 상부면을 통하여 단차진 면에 부착되며, 상기 기판과 전기적으로 연결되는 제 1 칩과; 상기 기판의 하부면을 통하여 상기 칩 실장 구멍에 노출된 상기 제 1 칩에 부착되며, 상기 기판과 전기적으로 연결되는 제 2 칩과; 및 상기 칩 실장 구멍에 실장된 제 1 칩과 제 2 칩을 봉합하여 형성한 수지 봉합부;를 포함하는 것을 특징으로 하는 적층 칩 패키지를 제공한다. 이때, 제 1 칩의 상부면에 다수개의 반도체 칩을 더 부착하고, 제 2 칩의 상부면에 다수개의 반도체 칩을 더 부착할 수도 있다.In order to achieve the above object, a laminated chip package comprising: a substrate having an upper surface and a lower surface opposite to the upper surface, the chip mounting hole being stepped through a central portion of the upper surface; A first chip attached to the stepped surface through an upper surface of the substrate and electrically connected to the substrate; A second chip attached to the first chip exposed through the lower surface of the substrate to the chip mounting hole and electrically connected to the substrate; And a resin encapsulation portion formed by sealing the first chip and the second chip mounted in the chip mounting hole. In this case, a plurality of semiconductor chips may be further attached to the upper surface of the first chip, and a plurality of semiconductor chips may be further attached to the upper surface of the second chip.
본 발명의 바람직한 한 실시 양태에 따른 적층 칩 패키지는, 기판의 하부면에 형성된 외부접속단자;를 더 포함하며, 외부접속단자는 기판의 하부면에 형성된 수지 봉합부의 하부면보다는 아래에 형성된다.The multilayer chip package according to an exemplary embodiment of the present invention further includes an external connection terminal formed on the bottom surface of the substrate, and the external connection terminal is formed below the bottom surface of the resin encapsulation portion formed on the bottom surface of the substrate.
그리고, 본 발명의 바람직한 다른 실시 양태에 따른 적층 칩 패키지는, 기판의 상부면에 형성된 외부접속단자;를 더 포함하며, 외부접속단자는 기판의 상부면에 형성된 수지 봉합부의 상부면보다는 높게 형성된다.The multilayer chip package according to another exemplary embodiment of the present invention further includes an external connection terminal formed on an upper surface of the substrate, and the external connection terminal is formed higher than an upper surface of the resin encapsulation portion formed on the upper surface of the substrate. .
이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.
도 3은 본 발명의 제 1 실시예에 따른 두 개의 반도체 칩이 적층된 적층 칩 패키지를 보여주는 단면도이다. 도 3을 참조하면, 적층 칩 패키지(40)는 칩 실장 구멍(35, 45)을 갖는 기판(31)과, 기판의 칩 실장 구멍(35, 45)에 실장된 제 1 및 제 2 칩(32, 42)과, 칩 실장 구멍(35, 45)에 실장된 제 1 및 제 2 칩(32, 42)을 봉합하여 형성한 수지 봉합부(36)로 구성된다. 그리고, 외부접속단자인 솔더볼(47)이 기판(31) 하부면의 수지 봉합부(36) 둘레에 형성되어 있다.3 is a cross-sectional view illustrating a stacked chip package in which two semiconductor chips according to a first embodiment of the present invention are stacked. Referring to FIG. 3, the stacked chip package 40 includes a substrate 31 having chip mounting holes 35 and 45, and first and second chips 32 mounted in chip mounting holes 35 and 45 of the substrate. And 42, and a resin encapsulation portion 36 formed by sealing the first and second chips 32, 42 mounted in the chip mounting holes 35, 45. And the solder ball 47 which is an external connection terminal is formed around the resin sealing part 36 of the lower surface of the board | substrate 31. As shown in FIG.
제 1 실시예에 따른 적층 칩 패키지(40) 구조를 좀더 상세히 설명하면 다음과 같다.The structure of the stacked chip package 40 according to the first embodiment will be described in more detail as follows.
기판(31)은 상부면과, 상부면에 반대되는 하부면을 가지며, 상부면의 중심 부분을 관통하여 단차지게 칩 실장 구멍(35, 45)이 형성되어 있다. 기판(31)의 상부면쪽의 칩 실장 구멍(35; 이하, '제 1 칩 실장 구멍'이라 한다)은 기판(31)의 하부면쪽의 칩 실장 구멍(45; 이하, '제 2 칩 실장 구멍'이라 한다)보다는 넓게 형성된다. 기판(31)으로는 인쇄회로기판, 세라믹 기판, 테이프 배선기판 등이 사용될 수 있다. 도면부호 35a는 칩 실장 구멍(35, 45)의 내부에 형성된 단차면을 가리킨다.The substrate 31 has an upper surface and a lower surface opposite to the upper surface, and chip mounting holes 35 and 45 are formed to step through the center portion of the upper surface. The chip mounting hole 35 (hereinafter referred to as 'first chip mounting hole') on the upper surface side of the substrate 31 is the chip mounting hole 45 (hereinafter referred to as 'second chip mounting hole' on the lower surface side of the substrate 31). It is wider than). As the substrate 31, a printed circuit board, a ceramic substrate, a tape wiring board, or the like may be used. Reference numeral 35a denotes a stepped surface formed inside the chip mounting holes 35 and 45.
제 1 칩(32)은 제 1 칩 실장 구멍(35)을 통하여 단차면(35a)에 접착제(33)가개재된 상태에서 부착되며, 본딩 와이어(34)에 의해 기판(31) 상부면에 형성된 배선 패턴과 전기적으로 연결된다. 제 1 칩(32)으로는 상부면의 가장자리 둘레에 전극 패드가 형성된 에지 패드형 반도체 칩을 사용하는 것이 바람직하다. 이때, 제 1 칩(32)이 단차면(35a)에 부착될 수 있도록, 제 1 칩(32)은 제 1 칩 실장 구멍(35)보다는 작고 제 2 칩 실장 구멍(45)보다는 크다. 그리고, 접착제(33)가 단차면(35a)에 도포된 상태에서 제 1 칩(32)을 부착하는 공정을 진행하기 때문에, 종래와 동일한 방법으로 제 1 칩(32)을 부착하는 공정을 진행할 수 있다.The first chip 32 is attached to the stepped surface 35a through the first chip mounting hole 35 with the adhesive 33 interposed therebetween, and formed on the upper surface of the substrate 31 by the bonding wire 34. It is electrically connected to the wiring pattern. It is preferable to use an edge pad type semiconductor chip having electrode pads formed around the edge of the upper surface as the first chip 32. At this time, the first chip 32 is smaller than the first chip mounting hole 35 and larger than the second chip mounting hole 45 so that the first chip 32 can be attached to the step surface 35a. And since the process of attaching the 1st chip 32 in the state in which the adhesive agent 33 is apply | coated to the step surface 35a is carried out, the process of attaching the 1st chip 32 can be performed by the same method as before. have.
제 2 칩(42)은 제 2 칩 실장 공간(45)을 통하여 제 2 칩 실장 공간(45)에 노출된 제 1 칩(32)의 하부면에 접착제(43)를 개재하여 부착되며, 본딩 와이어(44)에 의해 기판(31) 하부면에 형성된 배선 패턴과 전기적으로 연결된다. 제 2 칩(42)으로는 상부면의 중심부분에 전극 패드가 형성된 센터 패드형 반도체 칩을 사용하는 것이 바람직하며, 에지 패드형 반도체 칩을 사용할 수도 있다. 한편, 제 2 칩(42) 부착 공정은 제 1 칩(32)이 기판(31)에 부착된 상태에서 진행되기 때문에, 종래와 동일한 방법으로 제 2 칩(42)을 부착하는 공정을 진행할 수 있다. 물론, 제 2 칩(42)이 제 1 칩(32)의 하부면에 부착될 수 있도록, 제 2 칩(42)은 제 2 칩 실장 구멍(45)보다는 크기가 작다.The second chip 42 is attached to the lower surface of the first chip 32 exposed to the second chip mounting space 45 through the second chip mounting space 45 via an adhesive 43 and a bonding wire. 44 is electrically connected to the wiring pattern formed on the lower surface of the substrate 31. It is preferable to use the center pad type semiconductor chip in which the electrode pad was formed in the center part of the upper surface as the 2nd chip 42, An edge pad type semiconductor chip can also be used. On the other hand, since the process of attaching the second chip 42 proceeds in a state where the first chip 32 is attached to the substrate 31, the process of attaching the second chip 42 may be performed by the same method as in the related art. . Of course, the second chip 42 is smaller in size than the second chip mounting hole 45 so that the second chip 42 can be attached to the bottom surface of the first chip 32.
수지 봉합부(36)는 칩 실장 공간(35, 45)에 실장된 제 1 칩(32)과 제 2 칩(42) 및 본딩 와이어들(34, 44)을 외부환경으로부터 보호하기 위해서 액상의 성형수지로 봉합하여 형성한다.The resin encapsulation portion 36 is formed in a liquid phase to protect the first chip 32 and the second chip 42 and the bonding wires 34 and 44 mounted in the chip mounting spaces 35 and 45 from the external environment. It is formed by sealing with resin.
그리고, 외부접속단자인 솔더볼들(47)이 기판(31)의 하부면에 부착된다. 이때, 솔더볼(47)은 기판(31)의 하부면에 형성된 수지 봉합부(36)보다는 아래에 올 수 있도록 형성된다.The solder balls 47, which are external connection terminals, are attached to the lower surface of the substrate 31. At this time, the solder ball 47 is formed to be below the resin sealing portion 36 formed on the lower surface of the substrate 31.
한편, 제 1 실시예에서는 솔더볼(47)을 제 2 칩 실장 구멍(45)이 형성된 기판(31)의 면에 형성하였지만, 도 4에 도시된 제 2 실시예에서와 같이 제 1 칩 실장 구멍(55)이 형성된 기판(51)의 면에 솔더볼(57)을 형성할 수도 있다. 즉, 제 2 실시예에 따른 적층 칩 패키지(60)는 제 1 실시예에 따른 적층 칩 패키지(도 3의 40)의 기판(31) 상부면에 솔더볼이 형성된 구조를 제외하면 제 1 실시예에 따른 적층 칩 패키지와 동일한 구조를 갖는다.Meanwhile, in the first embodiment, the solder ball 47 is formed on the surface of the substrate 31 on which the second chip mounting holes 45 are formed, but as in the second embodiment shown in FIG. The solder ball 57 may be formed on the surface of the substrate 51 on which the 55 is formed. That is, the multilayer chip package 60 according to the second embodiment is the same as the first embodiment except that the solder ball is formed on the upper surface of the substrate 31 of the multilayer chip package 40 according to the first embodiment. It has the same structure as the stacked chip package.
5에 도시된 바와 같이, 제 1 칩(72)의 상부에 다수개 예컨대 2개의 반도체 칩(77, 78)을 차례로 적층하고, 제 2 칩(82)의 상부에 1개의 반도체 칩(88)을 적층하여 다수개의 반도체 칩(72, 77, 78, 82, 88)이 적층된 적층 패키지(80)로 구현할 수 있다. 이때, 솔더볼(87)은 수지 봉합부(76)의 높이가 상대적으로 낮은 기판(71)의 면 예컨대, 제 2 칩 실장 구멍(85)이 형성된 기판(71)의 면에 형성하는 것이 바람직하다.As shown in FIG. 5, a plurality of semiconductor chips 77 and 78, for example, are sequentially stacked on the first chip 72, and one semiconductor chip 88 is disposed on the second chip 82. The stack may be implemented as a stack package 80 in which a plurality of semiconductor chips 72, 77, 78, 82, and 88 are stacked. At this time, the solder ball 87 is preferably formed on the surface of the substrate 71 having a relatively low height of the resin sealing portion 76, for example, on the surface of the substrate 71 on which the second chip mounting holes 85 are formed.
도 5에서 제 1 칩(72)을 비롯한, 제 1 칩(72) 위에 적층되는 반도체 칩들(77, 78)은 모두 에지 패드형 반도체 칩이며, 제 1 칩(72)의 전극 패드 사이의 영역에 반도체 칩들(77, 78)이 상하로 부착된다. 제 2 칩(82)은 에지 패드형 반도체 칩이며, 제 2 칩(82)의 전극 패드 사이에 부착되는 반도체 칩(88)은 센터 패드형 반도체 칩이다. 물론, 제 2 칩(82)의 상부면에 에지 패드형 반도체 칩을 부착할 수도 있다. 반도체 칩들(72, 77, 78, 82, 88)과 기판(71)은 본딩 와이어(74,84)에 의해 전기적으로 연결되며, 반도체 칩들(72, 77, 78, 82, 88)이 실장된 칩 실장 구멍(75, 85)은 수지 봉합부(76)에 의해 보호된다.In FIG. 5, the semiconductor chips 77 and 78 stacked on the first chip 72, including the first chip 72, are all edge pad type semiconductor chips, and the semiconductor chips 77 and 78 are disposed in the area between the electrode pads of the first chip 72. The semiconductor chips 77 and 78 are attached up and down. The second chip 82 is an edge pad type semiconductor chip, and the semiconductor chip 88 attached between the electrode pads of the second chip 82 is a center pad type semiconductor chip. Of course, the edge pad type semiconductor chip may be attached to the upper surface of the second chip 82. The semiconductor chips 72, 77, 78, 82, 88 and the substrate 71 are electrically connected by bonding wires 74, 84, and a chip on which the semiconductor chips 72, 77, 78, 82, 88 are mounted. The mounting holes 75 and 85 are protected by the resin sealing portion 76.
한편, 본 명세서와 도면에 개시된 본 발명의 실시예들은 이해를 돕기 위해 특정 예를 제시한 것에 지나지 않으며, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예들 이외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다. 예를 들어, 제 2 칩의 상부면에 복수개의 반도체 칩을 적층할 수도 있다.On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented. For example, a plurality of semiconductor chips may be stacked on the upper surface of the second chip.
본 발명의 구조를 따르면 단차면을 갖는 칩 실장 구멍을 기판의 중심 부분에 형성함으로써, 반도체 칩의 적층에 따른 적층 칩 패키지 두께의 증가를 최소할 수 있다. 더불어 단차면에 제 1 칩을 부착한 다음 제 1 칩의 하부면에 제 2 칩을 부착할 수 있기 때문에, 종래의 칩 실장 기술을 그대로 이용할 수 있다.According to the structure of the present invention, by forming a chip mounting hole having a stepped surface in the center portion of the substrate, it is possible to minimize the increase in the thickness of the laminated chip package due to the stacking of the semiconductor chip. In addition, since the second chip may be attached to the lower surface of the first chip after the first chip is attached to the stepped surface, the conventional chip mounting technology may be used as it is.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000072322A KR20020042958A (en) | 2000-12-01 | 2000-12-01 | Stack chip package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000072322A KR20020042958A (en) | 2000-12-01 | 2000-12-01 | Stack chip package |
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| KR20020042958A true KR20020042958A (en) | 2002-06-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020000072322A KR20020042958A (en) | 2000-12-01 | 2000-12-01 | Stack chip package |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020105067A1 (en) * | 2001-02-02 | 2002-08-08 | Takahiro Oka | Semiconductor chip package |
| CN108417556A (en) * | 2018-05-23 | 2018-08-17 | 奥肯思（北京）科技有限公司 | Multichip stacking encapsulation structure |
| US11039537B1 (en) | 2019-12-16 | 2021-06-15 | Samsung Electro-Mechanics Co., Ltd. | Electronic component embedded substrate |
-
2000
- 2000-12-01 KR KR1020000072322A patent/KR20020042958A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020105067A1 (en) * | 2001-02-02 | 2002-08-08 | Takahiro Oka | Semiconductor chip package |
| US7075177B2 (en) * | 2001-02-02 | 2006-07-11 | Oki Electric Industry Co., Ltd. | Semiconductor chip package |
| US7211883B2 (en) | 2001-02-02 | 2007-05-01 | Oki Electric Industry Co., Ltd. | Semiconductor chip package |
| CN108417556A (en) * | 2018-05-23 | 2018-08-17 | 奥肯思（北京）科技有限公司 | Multichip stacking encapsulation structure |
| US11039537B1 (en) | 2019-12-16 | 2021-06-15 | Samsung Electro-Mechanics Co., Ltd. | Electronic component embedded substrate |
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