KR20020064415A - Semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package is provided to overcome a stack limit of semiconductor chips by forming electrode pads on both surface of the semiconductor chip. CONSTITUTION: A semiconductor package(100) comprises a semiconductor chip(10) mounted on a PCB(Printed Circuit Board)(20), a resin molding part(40) enclosed on the resultant structure for protecting the semiconductor chip(10) and the PCB(20) and solder balls(50) as an outer connection terminal formed on the rear surface of the PCB(20) for electrically connecting with the semiconductor chip(10). The semiconductor chip(10) further includes the first active surface(12) formed with first electrode pads(14) and the second active surface(16) formed with second electrode pads(18).

Description

Semiconductor Package {Semiconductor package}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which a semiconductor chip having electrode pads formed on both surfaces thereof is mounted.

Since a typical semiconductor wafer is a plane, there is a limit to improving the integration degree of a semiconductor device in one plane. In addition, a lot of facility investment is required to improve the density. Therefore, many companies and academia are investigating stacking method of high density 3D chip and 3D package for high integration of semiconductor package. That is, a method of increasing the degree of integration after cutting a semiconductor wafer into individual semiconductor devices is being studied.

The three-dimensional stacked package manufactured by stacking a plurality of unit packages in three dimensions may achieve high integration, but has a problem in that the thickness thereof is inferior to light and thin shortening of a semiconductor product.

The three-dimensional stacked chip package manufactured by stacking a plurality of semiconductor chips in three dimensions can achieve high integration and has excellent responsiveness to light and thin reduction of semiconductor products.

However, multilayer chip packages have the following problems. First, in the form of stacking and connecting a plurality of semiconductor chips, there is a limitation in the shape and number of stackable semiconductor chips, and if the same size semiconductor chips are stacked, electrode pads of stacked semiconductor chips are hidden and cannot be used. . Next, since all semiconductor chips to be stacked must be different in size, there is also a problem in that the maximum stacking number is limited to three or four layers. Next, since the bonding wire used as the electrical connection means between the stacked semiconductor chip and the external connection terminal becomes longer as the layer increases, problems such as wire sweeping or mechanical contact between the bonding wires occur in the forming process. Can be. In particular, in the case of a thin package using a molding resin, a plurality of semiconductor chips must be stacked in a limited space, which causes problems such as poor quality and poor workability in the molding process. As it grows longer, the package that emphasizes the problem of speed and speeding up has a disadvantage in that it is difficult to be multifunctional.

Accordingly, an object of the present invention is to provide a semiconductor package capable of overcoming stacking limitations of semiconductor chips and enabling multi-functionality and high speed.

1 is a cross-sectional view illustrating a semiconductor package in which semiconductor chips having electrode pads formed on both surfaces thereof are mounted, according to an exemplary embodiment of the present invention.

Description of the main parts of the drawing

10 semiconductor chip 12 first active surface

13: bump 14: first electrode pad

16: 2nd active surface 18: 2nd electrode pad

20: substrate 22: substrate body

24: wiring pattern layer 30: bonding wire

40: resin sealing portion 50: solder ball

100: semiconductor package

In order to achieve the above object, a semiconductor chip having a first active surface on which first electrode pads are formed and a second active surface opposite to the first active surface and on which second electrode pads are formed, each of which is conductive to the first electrode pad. A semiconductor chip having bumps formed thereon; A substrate having an upper surface on which the semiconductor chip is bump-connected by the conductive bumps and a lower surface opposite to the upper surface; Bonding wires electrically connecting the second electrode pads of the semiconductor chip to an upper surface of the substrate; A resin encapsulation portion formed by sealing a semiconductor chip and a bonding wire of the upper surface of the substrate with a molding resin; And a solder ball formed on a lower surface of the substrate and electrically connected to the semiconductor chip.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a cross-sectional view illustrating a semiconductor package 100 in which a semiconductor chip 10 having electrode pads 14 and 18 formed on both surfaces thereof according to an exemplary embodiment of the present invention is mounted. Referring to FIG. 1, the semiconductor package 100 includes a semiconductor chip 10 mounted on a printed circuit board 20, and an upper surface of the printed circuit board 20 on which the semiconductor chip 10 is mounted is a resin encapsulation unit ( 40, a solder ball 50, which is an external connection terminal electrically connected to the semiconductor chip 10, is formed on the lower surface of the printed circuit board 20.

In the semiconductor chip 10, electrode pads 14 and 18 are formed on both surfaces 12 and 16 so that the semiconductor chip 10 can cope with the limitations, the speed, and the multifunctionality of the lamination. That is, the semiconductor chip 10 may include a first active surface 12 on which first electrode pads 14 are formed, and a second active surface opposite to the first active surface 12 and on which second electrode pads 18 are formed. The first electrode pads 14 having a surface 16 and formed on the first active surface 12 may be flip chip bonded to the upper surface of the printed circuit board 20. Conductive bumps 13 are formed at predetermined heights, respectively. The conductive bump 13 according to the present embodiment is a solder bump, but may be formed of an Au plating bump or a stud bump. In particular, since integrated circuits are formed on both surfaces 12 and 16 of the semiconductor chip, it is possible to cope with multifunctionality and high speed.

The printed circuit board 20 includes a substrate body 22 having an upper surface and a lower surface, and a multilayer wiring pattern layer 24 formed on the substrate body 22. The wiring pattern layer 24 is formed on the upper wiring layer including the substrate pad 21 electrically connected to the semiconductor chip 10 mounted on the upper surface of the substrate body 22, and on the lower surface of the substrate body 22. And formed inside the solder ball pad 25 and the substrate body 22 to which the solder balls 50 are fused, and the inner wiring layer 23 connecting the substrate pad 21 and the solder ball pad 25 to each other. 24 is formed by patterning a copper foil formed on the substrate body 22. The substrate pad 21 of the upper wiring layer is formed outside the first chip pad 21a to which the conductive bumps 13 of the semiconductor chip are flip chip bonded and the flip chip bonded semiconductor chip 10, and the second electrode pad ( 18 and a second substrate pad 21b connected to the bonding wire 30. Although not shown, a solder resist layer 25 is formed on the entire surface of the printed circuit board 20 except for the solder ball pad 25 and the substrate pad 21 to which the solder ball 50 is attached.

In the embodiment of the present invention, the second electrode pad 18 and the second substrate pad 21b make electrical connection by the bonding wire 30. In order to minimize the length of the bonding wire 30, the second electrode The pad 18 is preferably formed at the edge of the second active surface 16. In order to prevent the conductive bumps 13 from tilting to either side after being flip chip bonded to the printed circuit board 20, the first electrode pad 14 may be formed rather than the center portion of the first active surface 12. It is preferable to form in the edge part. On the other hand, depending on which substrate is used as the substrate on which the semiconductor chip is mounted, the deformations of the first and second electrode pads formed at the center portion or the edge portion of the first and second active surfaces are not limited to the scope of the technical idea of the present invention. It doesn't go away.

In addition, the resin encapsulation part 40 may use an epoxy molding compound (EMC) to protect the semiconductor chip 10 and the bonding wire 30 mounted on the upper surface of the printed circuit board 20 from an external environment. It is formed by sealing with a molding resin of a liquid such as.

On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented. For example, in the exemplary embodiment of the present invention, a printed circuit board is used as a substrate on which a semiconductor chip is mounted, but a semiconductor package may be implemented using a tape wiring board, a ceramic board, a lead frame, or the like instead of a printed circuit board. . In addition, as needed, the first and second electrode pads may be formed in the central portion or the edge portion of the first and second active surfaces.

Therefore, according to the structure of the present invention, by forming electrode pads on both sides of the semiconductor chip, it is possible to exert the effect of stacking two conventional semiconductor chips with one semiconductor chip, thereby limiting the limitation of stacking existing semiconductor chips. It can be overcome. In addition, the semiconductor package can be thinned.

In addition, it is possible to provide a semiconductor package which is more versatile and faster depending on which circuit is formed on both surfaces of the semiconductor chip.

Claims (3)

A semiconductor chip having a first active surface having first electrode pads formed thereon and a second active surface opposite to the first active surface having second electrode pads formed thereon, each semiconductor chip having conductive bumps formed on the first electrode pads; A substrate having an upper surface on which the semiconductor chip is bump-connected by the conductive bumps and a lower surface opposite to the upper surface; Bonding wires electrically connecting the second electrode pads of the semiconductor chip to an upper surface of the substrate; A resin encapsulation portion formed by sealing a semiconductor chip and a bonding wire of the upper surface of the substrate with a molding resin; And And a solder ball formed on the lower surface of the substrate and electrically connected to the semiconductor chip. The semiconductor package of claim 1, wherein the first electrode pad is formed at an edge portion of the first active surface. The semiconductor package of claim 2, wherein the second electrode pad is formed at an edge portion of the second active surface.