KR20100038165A - Ｓｏｉ 기판의 제작 방법 - Google Patents

Ｓｏｉ 기판의 제작 방법 Download PDF

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Publication number
KR20100038165A
KR20100038165A KR1020090094040A KR20090094040A KR20100038165A KR 20100038165 A KR20100038165 A KR 20100038165A KR 1020090094040 A KR1020090094040 A KR 1020090094040A KR 20090094040 A KR20090094040 A KR 20090094040A KR 20100038165 A KR20100038165 A KR 20100038165A
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KR
South Korea
Prior art keywords
single crystal
crystal semiconductor
semiconductor substrate
substrate
ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020090094040A
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English (en)
Korean (ko)
Inventor
타케시 쉬이치
쥬니치 고에주카
히데토 오누마
šœ페이 야마자키
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
Publication of KR20100038165A publication Critical patent/KR20100038165A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
KR1020090094040A 2008-10-03 2009-10-01 Ｓｏｉ 기판의 제작 방법 Ceased KR20100038165A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP-P-2008-258301 2008-10-03
JP2008258301 2008-10-03
JPJP-P-2008-258290 2008-10-03
JP2008258290 2008-10-03

Publications (1)

Publication Number Publication Date
KR20100038165A true KR20100038165A (ko) 2010-04-13

Family

ID=42076124

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090094040A Ceased KR20100038165A (ko) 2008-10-03 2009-10-01 Ｓｏｉ 기판의 제작 방법

Country Status (4)

Country Link
US (2) US8143134B2 (enExample)
JP (2) JP2010109345A (enExample)
KR (1) KR20100038165A (enExample)
SG (1) SG160300A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7348227B1 (en) * 1995-03-23 2008-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
SG160300A1 (en) * 2008-10-03 2010-04-29 Semiconductor Energy Lab Method for manufacturing soi substrate
US8288249B2 (en) * 2010-01-26 2012-10-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8324084B2 (en) 2010-03-31 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device
JP4831844B1 (ja) * 2010-09-28 2011-12-07 三菱重工業株式会社 常温接合装置および常温接合方法
US8735263B2 (en) 2011-01-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8772130B2 (en) 2011-08-23 2014-07-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
JP6091905B2 (ja) 2012-01-26 2017-03-08 株式会社半導体エネルギー研究所 半導体装置
US8941113B2 (en) 2012-03-30 2015-01-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element, semiconductor device, and manufacturing method of semiconductor element
US9721832B2 (en) 2013-03-15 2017-08-01 Kulite Semiconductor Products, Inc. Methods of fabricating silicon-on-insulator (SOI) semiconductor devices using blanket fusion bonding
WO2016171262A1 (ja) * 2015-04-24 2016-10-27 日新電機株式会社 イオンビーム照射装置およびイオンビーム照射方法
JP6503859B2 (ja) * 2015-04-24 2019-04-24 日新電機株式会社 イオンビーム照射装置およびイオンビーム照射方法
JP2016207520A (ja) * 2015-04-24 2016-12-08 日新電機株式会社 イオンビーム照射装置およびイオンビーム照射方法
US9607847B1 (en) * 2015-12-18 2017-03-28 Texas Instruments Incorporated Enhanced lateral cavity etch
CN109904065B (zh) * 2019-02-21 2021-05-11 中国科学院上海微系统与信息技术研究所 异质结构的制备方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
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FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH06163446A (ja) 1992-11-25 1994-06-10 Ishikawajima Harima Heavy Ind Co Ltd イオンドーピング方法及び装置
JP3438377B2 (ja) 1995-02-22 2003-08-18 石川島播磨重工業株式会社 イオンシャワードーピング装置
JPH08255762A (ja) * 1995-03-17 1996-10-01 Nec Corp 半導体デバイスの製造方法
JP3514912B2 (ja) * 1995-08-31 2004-04-05 東芝電子エンジニアリング株式会社 薄膜トランジスタの製造方法
JPH0973873A (ja) * 1995-09-05 1997-03-18 Nissin Electric Co Ltd ホルダ駆動装置
JPH0982267A (ja) 1995-09-08 1997-03-28 Advanced Display:Kk イオンドーピング装置
JPH0982661A (ja) 1995-09-19 1997-03-28 Sony Corp 半導体装置の製造方法及びイオンドーピング装置
JPH1064471A (ja) * 1996-08-19 1998-03-06 Hitachi Ltd イオン注入装置
US6582999B2 (en) 1997-05-12 2003-06-24 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2001274368A (ja) * 2000-03-27 2001-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法およびこの方法で製造された貼り合わせウエーハ
US6583440B2 (en) * 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
US7119365B2 (en) 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
US7148124B1 (en) 2004-11-18 2006-12-12 Alexander Yuri Usenko Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
US20070281440A1 (en) * 2006-05-31 2007-12-06 Jeffrey Scott Cites Producing SOI structure using ion shower
SG160300A1 (en) * 2008-10-03 2010-04-29 Semiconductor Energy Lab Method for manufacturing soi substrate

Also Published As

Publication number Publication date
US20120164817A1 (en) 2012-06-28
US8143134B2 (en) 2012-03-27
US20100087044A1 (en) 2010-04-08
SG160300A1 (en) 2010-04-29
JP2010109345A (ja) 2010-05-13
JP2014179644A (ja) 2014-09-25
US8658508B2 (en) 2014-02-25

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