KR20090102870A - 컨텐츠-종결 dma - Google Patents
컨텐츠-종결 dmaInfo
- Publication number
- KR20090102870A KR20090102870A KR1020097017581A KR20097017581A KR20090102870A KR 20090102870 A KR20090102870 A KR 20090102870A KR 1020097017581 A KR1020097017581 A KR 1020097017581A KR 20097017581 A KR20097017581 A KR 20097017581A KR 20090102870 A KR20090102870 A KR 20090102870A
- Authority
- KR
- South Korea
- Prior art keywords
- data
- transfer
- dma
- operable
- terminate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012546 transfer Methods 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims description 36
- 230000005540 biological transmission Effects 0.000 claims description 19
- 230000004044 response Effects 0.000 claims description 17
- 230000000977 initiatory effect Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 description 10
- 230000006870 function Effects 0.000 description 8
- 238000013500 data storage Methods 0.000 description 7
- 239000000872 buffer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000001174 ascending effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Bus Control (AREA)
- Communication Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (27)
- 컨텐츠-종결 직접 메모리 액세스(CT-DMA: Content-Terminated Direct Memory Access) 회로로서,적어도 하나의 데이터 전달 인터페이스;필터 기준을 저장하도록 동작가능한 메모리;전달 데이터를 하나 이상의 필터 기준과 비교하도록 동작가능한 비교기; 및상기 비교기 출력에 응답하여 DMA 전달을 종결하도록 동작가능한 제어기를 포함하는, CT-DMA 회로.
- 제1항에 있어서,상기 데이터 전달 인터페이스는 시스템 버스 인터페이스를 포함하는, CT-DMA 회로.
- 제1항에 있어서,상기 데이터 전달 인터페이스는 다른 회로에 대한 전용 데이터 인터페이스를 포함하는, CT-DMA 회로.
- 제1항에 있어서,상기 메모리는 하나 이상의 레지스터들을 포함하는, CT-DMA 회로.
- 제4항에 있어서,상기 레지스터들은 프로세서에 의하여 실행되는 보조 프로세서(coprocessor) 레지스터 액세스 명령들을 통해 액세스되는, CT-DMA 회로.
- 제4항에 있어서,상기 레지스터들은 메모리 맵핑되는, CT-DMA 회로.
- 제1항에 있어서,상기 메모리는 하드와이어드(hardwired) 데이터 패턴들을 포함하는, CT-DMA 회로.
- 제1항에 있어서,상기 필터 기준은 패턴 데이터의 하나 이상의 유닛(unit)들을 포함하며, 상기 비교기는 전달 데이터의 하나 이상의 유닛들을 상기 패턴 데이터와 비교하도록 동작가능한, CT-DMA 회로.
- 제8항에 있어서,상기 비교기는 패턴 데이터의 둘 이상의 유닛들과 전달 데이터의 유닛을 비교하도록 동작가능한, CT-DMA 회로.
- 제8항에 있어서,상기 제어기는 전달 데이터의 하나 이상의 유닛들이 상기 패턴 데이터와 매칭될 때, DMA 전달을 종결하도록 동작가능한, CT-DMA 회로.
- 제8항에 있어서,상기 제어기는 전달 데이터의 하나 이상의 유닛들이 상기 패턴 데이터와 매칭하는데 실패할 때, DMA 전달을 종결하도록 동작가능한, CT-DMA 회로.
- 제8항에 있어서,상기 제어기는 전달 데이터의 하나 이상의 유닛들이 미리 결정된 회수만큼 상기 패턴 데이터와 매칭될 때, DMA 전달을 종결하도록 동작가능한, CT-DMA 회로.
- 제1항에 있어서,상기 제어기는 인터럽트를 어서트(assert)함으로써 DMA 전달을 종결하도록 동작가능한, CT-DMA 회로.
- 제1항에 있어서,상기 제어기는 미리 결정된 값을 미리 결정된 위치에 기록함으로써 DMA 전달을 종결하도록 동작가능한, CT-DMA 회로.
- 제1항에 있어서,상기 제어기는 상기 비교기 출력에 응답하여 다른 DMA 전달을 개시하도록 추가로 동작가능한, CT-DMA 회로.
- 제15항에 있어서,상기 비교기 출력에 응답하여 다른 DMA 전달을 개시하는 동작은 상기 비교기 출력에 응답하여 결정되는 메모리 위치로부터 DMA 제어 파라미터들을 판독하는 동작을 포함하는, CT-DMA 회로.
- 소스로부터 목적지로 알려지지 않은 양의 데이터를 송신하는 방법으로서,소스로부터의 전달 데이터를 연속하여 판독하는 단계;전달 데이터를 미리 결정된 패턴 데이터와 비교하는 단계;상기 비교에 응답하여 전달을 종결할 때를 결정하는 단계; 및상기 전달을 종결할 때까지 전달 데이터를 상기 목적지에 연속적으로 기록하는 단계를 포함하며, 상기 단계들은 프로세서에 의해 자율적으로 수행되는, 데이터를 송신하는 방법.
- 제17항에 있어서,상기 비교에 응답하여 전달을 종결할 때를 결정하는 단계는 전달 데이터의 하나 이상의 유닛들이 상기 패턴 데이터와 매칭될 때 상기 전달을 종결하도록 결정하는 단계를 포함하는, 데이터를 송신하는 방법.
- 제17항에 있어서,상기 비교에 응답하여 전달을 종결할 때를 결정하는 단계는 전달 데이터의 하나 이상의 유닛들이 상기 패턴 데이터와 매칭하는데 실패할 때 상기 전달을 종결하도록 결정하는 단계를 포함하는, 데이터를 송신하는 방법.
- 제17항에 있어서,상기 비교에 응답하여 전달을 종결할 때를 결정하는 단계는 전달 데이터의 하나 이상의 유닛들이 미리 결정된 회수만큼 상기 패턴 데이터와 매칭될 때, 상기 전달을 종결하도록 결정하는 단계를 포함하는, 데이터를 송신하는 방법.
- 제17항에 있어서,필터 기준을 수신하는 단계를 더 포함하는, 데이터를 송신하는 방법.
- 제21항에 있어서,상기 필터 기준은 상기 패턴 데이터를 포함하는, 데이터를 송신하는 방법.
- 제22항에 있어서,상기 필터 기준은 전달 데이터 및 패턴 데이터 비교들을 결합하기 위한 규칙들을 포함하는, 데이터를 송신하는 방법.
- 컴퓨팅 시스템으로서,데이터를 제공하도록 동작가능한 데이터 소스;데이터를 수신하도록 동작가능한 데이터 목적지;상기 소스로부터 상기 목적지로 전달 데이터를 수행하도록 동작가능하며, 하나 이상의 전달 데이터의 값들에 응답하여 데이터 전달을 종결하도록 추가로 동작가능한 컨텐츠-종결 직접 메모리 액세스(CT-DMA) 회로; 및상기 CT-DMA 회로를 개시하도록 동작가능한 프로세서를 포함하는, 컴퓨팅 시스템.
- 제24항에 있어서,상기 프로세서는 상기 CT-DMA 회로의 하나 이상의 메모리 위치들에 필터 기준을 기록함으로써 상기 CT-DMA 회로를 개시하는, 컴퓨팅 시스템.
- 제24항에 있어서,상기 CT-DMA 회로는 전달 데이터를 필터 기준과 비교하고, 상기 비교에 응답하여 상기 데이터 전달을 종결하는, 컴퓨팅 시스템.
- 제24항에 있어서,상기 프로세서는 메모리에 필터 기준을 기록하고, 상기 CT-DMA 회로에 상기 메모리에 대한 포인터를 제공함으로써 상기 CT-DMA 회로를 개시하는, 컴퓨팅 시스템.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/626,414 | 2007-01-24 | ||
US11/626,414 US7934025B2 (en) | 2007-01-24 | 2007-01-24 | Content terminated DMA |
PCT/US2008/051965 WO2008092044A2 (en) | 2007-01-24 | 2008-01-24 | Content-terminated dma |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20090102870A true KR20090102870A (ko) | 2009-09-30 |
KR101064101B1 KR101064101B1 (ko) | 2011-09-08 |
Family
ID=39366882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020097017581A Expired - Fee Related KR101064101B1 (ko) | 2007-01-24 | 2008-01-24 | 컨텐츠-종결 dma |
Country Status (8)
Country | Link |
---|---|
US (1) | US7934025B2 (ko) |
EP (1) | EP2126710B1 (ko) |
JP (1) | JP5185289B2 (ko) |
KR (1) | KR101064101B1 (ko) |
CN (1) | CN101589377B (ko) |
AT (1) | ATE540362T1 (ko) |
TW (1) | TW200842593A (ko) |
WO (1) | WO2008092044A2 (ko) |
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JP4985599B2 (ja) * | 2008-09-18 | 2012-07-25 | Necエンジニアリング株式会社 | Dma転送制御システム |
US8055816B2 (en) * | 2009-04-09 | 2011-11-08 | Micron Technology, Inc. | Memory controllers, memory systems, solid state drives and methods for processing a number of commands |
US20110093099A1 (en) * | 2009-10-16 | 2011-04-21 | Newport Controls | Controller system adapted for spa |
US8589603B2 (en) * | 2010-08-30 | 2013-11-19 | International Business Machines Corporation | Delaying acknowledgment of an operation until operation completion confirmed by local adapter read operation |
US8316195B2 (en) * | 2010-09-10 | 2012-11-20 | Hitachi, Ltd. | Storage system and data transfer method of storage system |
EP2620877B1 (en) * | 2010-09-21 | 2015-12-16 | Mitsubishi Electric Corporation | Dma controller and data readout device |
US11797474B2 (en) * | 2011-02-17 | 2023-10-24 | Hyperion Core, Inc. | High performance processor |
US9454367B2 (en) * | 2012-03-15 | 2016-09-27 | International Business Machines Corporation | Finding the length of a set of character data having a termination character |
US8943239B2 (en) | 2012-07-30 | 2015-01-27 | Qualcomm Incorporated | Data snooping direct memory access for pattern detection |
US10049061B2 (en) * | 2012-11-12 | 2018-08-14 | International Business Machines Corporation | Active memory device gather, scatter, and filter |
JP6122135B2 (ja) | 2012-11-21 | 2017-04-26 | コーヒレント・ロジックス・インコーポレーテッド | 分散型プロセッサを有する処理システム |
DE102013109978A1 (de) * | 2013-09-11 | 2015-03-12 | Technische Universität Dresden | Verfahren und Vorrichtung zum Vor-Auswählen, Filtern und Verteilen von Daten in Datenbank-Management-Systemen |
JP6205386B2 (ja) * | 2015-05-18 | 2017-09-27 | 長瀬産業株式会社 | 半導体装置及び情報書込/読出方法 |
US10599208B2 (en) * | 2015-09-08 | 2020-03-24 | Toshiba Memory Corporation | Memory system and controller |
WO2025072239A1 (en) * | 2023-09-26 | 2025-04-03 | Microchip Technology Incorporated | Device and methods for functional descriptor-based dma controller |
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-
2007
- 2007-01-24 US US11/626,414 patent/US7934025B2/en active Active
-
2008
- 2008-01-24 TW TW097102668A patent/TW200842593A/zh unknown
- 2008-01-24 CN CN2008800027365A patent/CN101589377B/zh not_active Expired - Fee Related
- 2008-01-24 WO PCT/US2008/051965 patent/WO2008092044A2/en active Application Filing
- 2008-01-24 KR KR1020097017581A patent/KR101064101B1/ko not_active Expired - Fee Related
- 2008-01-24 JP JP2009547431A patent/JP5185289B2/ja not_active Expired - Fee Related
- 2008-01-24 EP EP08713994A patent/EP2126710B1/en not_active Not-in-force
- 2008-01-24 AT AT08713994T patent/ATE540362T1/de active
Also Published As
Publication number | Publication date |
---|---|
US20080177909A1 (en) | 2008-07-24 |
CN101589377A (zh) | 2009-11-25 |
WO2008092044A2 (en) | 2008-07-31 |
EP2126710B1 (en) | 2012-01-04 |
ATE540362T1 (de) | 2012-01-15 |
TW200842593A (en) | 2008-11-01 |
EP2126710A2 (en) | 2009-12-02 |
WO2008092044A3 (en) | 2008-12-18 |
CN101589377B (zh) | 2012-05-23 |
US7934025B2 (en) | 2011-04-26 |
JP2010517182A (ja) | 2010-05-20 |
JP5185289B2 (ja) | 2013-04-17 |
KR101064101B1 (ko) | 2011-09-08 |
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