KR20090072260A - Method of forming an isolation layer in semiconductor device - Google Patents

Abstract

A method for forming an isolation film of a semiconductor device is provided to prevent a void by uniformly filling a moat due to a HDP(High Density Plasma) deposition property with an oxide film using a LPCVD(Low Pressure CVD) method. A trench(112) is formed on an isolation region of a semiconductor substrate(100) through an etching process using an isolation mask. A first insulation film(116) is formed on a bottom part of the trench. A second insulation film(118) is formed on the semiconductor substrate including the first insulation film. An etching process of the second insulation film is performed in order to increase an aspect ratio in the isolation region. A third insulation film(120) is formed on a top part of an edge of the second insulation film in order to fill a moat generated on the second insulation film. The second insulation film is made of a HDP oxide film.

Description

Method of forming an isolation layer in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation layer of a semiconductor device, and to a method of forming a device isolation layer of a semiconductor device by filling a moat due to high density plasma (HDP) deposition characteristics to eliminate subsequent void inducing factors. It is about.

As the semiconductor devices are highly integrated, the process of forming a device isolation layer is becoming more difficult. Accordingly, an isolation layer is formed by using a shallow trench isolation (STI) method in which a trench is formed in a semiconductor substrate and then embedded. On the other hand, there are a number of methods for the STI method, among which a tunnel insulating film, a polysilicon film and a hard mask film stacked on a semiconductor substrate are sequentially etched to form a trench, and an oxide film is formed on the entire structure to fill the trench. This is applied to, for example, a NAND flash memory device. However, in the case of highly integrated devices, since the trench depth is deeper than the inlet width of the trench, the trench may be trenched without a void using a high density plasma (HDP) oxide film that has been used due to the large aspect ratio. It is becoming more difficult to form a device isolation layer by fully gap filling. In order to solve this problem, studies are being actively conducted on materials used to gap fill trenches without voids.

Among the methods for solving the above problem, there is a method of completely gap filling the trench by using polysilazane (PSZ), which is one of spin on dielectric (SOD) materials. At this time, the coating is deposited by coating a flexible PSZ-based oxide film capable of narrow trench filling, curing it, and then flattening it by chemical mechanical polishing (CMP) process.

However, since the PSZ material contains a lot of impurities and moisture therein, it is advantageous for the gap fill when forming the device isolation layer using only the PSZ material, but it is vulnerable to reliability problems. Therefore, the wet etchback process reduces the thickness of the PSZ film to secure a subsequent gap fill margin, and then deposits an HDP oxide film having an appropriate thickness. However, due to the deposition characteristic of the HDP oxide film, a moat is generated by an asymmetric deposition phenomenon in which the HDP oxide film is thinly deposited on the trench sidewalls near the edge region except for the center region of the semiconductor substrate. After the deposition of the HDP oxide layer, a portion of the HDP oxide layer is etched by using a wet etchback process, and the HDP oxide layer is additionally deposited. At this time, voids are generated in the moat region.

In the case where the voids are formed, the sidewalls of the floating gate conductive film are exposed by the etchant during the removal of the nitride film for device isolation after the chemical mechanical polishing (CMP) process to form a subsequent device isolation layer, and thus the conductive film for the floating gate is severely exposed. Loss may occur. Subsequently, when a Peri Close (PCL) mask and an etching process are performed to maintain the effective field height (EFH) of the peripheral area, a part of the conductive film for the floating gate is caused by the conductive film attack for the floating gate. Causes tearing to occur. This decreases the area of the floating gate, which reduces the coupling ratio of the cell, thereby degrading the device's operating characteristics.

The present invention efficiently fills the moat due to the HDP (high density plasma) deposition characteristics with an oxide film using a low pressure chemical vapor deposition method, thereby removing voids in advance, thereby generating voids in a subsequent deposition process. The present invention relates to a method for forming a device isolation layer of a semiconductor device capable of suppressing the loss and preventing sidewall loss of the gate conductive film during subsequent wet etching.

The method of forming an isolation layer of a semiconductor device according to an embodiment of the present invention may include forming a trench in an isolation region of a semiconductor substrate by an etching process using an isolation mask, forming a first insulating layer under the trench, Forming a second insulating film on the semiconductor substrate including the first insulating film, performing an etching process of the second insulating film to increase an aspect ratio in the device isolation region, and filling a moat generated in the second insulating film Forming a third insulating film on an edge of the second insulating film;

In the above, the second insulating film is formed of an HDP (High Density Plasma) oxide film. The etching process is performed by a wet etchback process. After the wet etch back process, the second insulating layer is formed to be asymmetrically inclined because the thickness of the trench sidewalls closer to the edge region is lower than that of the center region of the semiconductor substrate.

The third insulating film is formed of an oxide film using a Low Pressure Chemical Vapor Deposition (LPCVD) method. The oxide film using the LPCVD method is formed of a HTO (High Temperature Oxide) film or a TEOS (Tetra Ethyl Ortho Silicate) film. The third insulating film remains on the sidewall of the conductive film formed in the active region of the semiconductor substrate in the form of a spacer.

The forming of the third insulating film may include depositing a third insulating film on the second insulating film by LPCVD to fill the mott generated in the second insulating film, and etching the third insulating film so that the third insulating film remains in the form of a spacer. Performing the step.

The first insulating film is formed of a laminated film of an HDP oxide film and a PSZ film. The first insulating film is formed of a laminated film of an HTO film and a PSZ film.

The step of forming the first insulating film may include forming an HDP oxide film on the semiconductor substrate including the trench to fill a portion of the trench, forming a PSZ film on the HDP oxide film to fill the trench, and forming the HDP oxide film and the PSZ only in the trench region. Performing a planarization etching process so that the film remains, and performing an etching process of lowering the height of the PSZ film.

The step of forming the first insulating film may include forming an HTO film on a semiconductor substrate including a trench to fill a portion of the trench, forming a PSZ film on the HTO film to fill the trench, and forming the HTO film and the PSZ film only in the trench region. Performing a planarization etching process so as to remain, and performing an etching process of lowering the height of the PSZ film.

The PSZ film is formed by coating and curing the PSZ material. Curing uses a mixture of steam annealing and N ₂ annealing.

Curing the planarized PSZ film before the etching process of lowering the height of the PSZ film. At this time, the curing uses a mixing method of steam annealing method and N ₂ annealing method.

After forming the third insulating layer, the method may further include performing an etching process of the third insulating layer to secure a space in the trench region.

After forming the third insulating film, forming a fourth insulating film on the semiconductor substrate including the third insulating film, performing a planarization etching process so that the third and fourth insulating films remain only in the region where the trench is formed, thereby forming an isolation layer; Removing the device isolation mask and performing an etching process of the device isolation layer to adjust the effective field height (EFH).

When the device isolation mask is removed, the third insulating film is left on the sidewalls of the conductive film formed in the active region of the semiconductor substrate to protect the sidewalls of the conductive film.

In addition, in the method of forming a device isolation film of a semiconductor device according to an embodiment of the present invention, a trench is formed in a device isolation region, and a semiconductor substrate having a multilayer film including a tunnel insulation film and a conductive film is provided in an active region. Forming a first insulating film in a lower portion, forming a second insulating film on a semiconductor substrate including the first insulating film, performing an etching process of the second insulating film to increase an aspect ratio in the device isolation region, and a second insulating film Forming a third insulating film on an edge of the second insulating film to fill the generated mote.

In the above, the third insulating film is formed of an oxide film using a low pressure chemical vapor deposition method. The oxide film using the low pressure chemical vapor deposition method is formed of an HTO film or a TEOS film.

When the device isolation mask is removed, the third insulating film is left on the sidewall of the conductive film in the form of a spacer to protect the sidewall of the conductive film.

The present invention has the following effects.

First, when forming an isolation layer using an HDP oxide film, a moat caused by HDP deposition characteristics is evenly embedded in an oxide film using an LPCVD method to reduce voids and topologies to reduce voids. In this case, void generation during the subsequent deposition process can be suppressed to prevent sidewall loss of the gate conductive film during subsequent wet etching.

Second, by filling the moat with an oxide film using the LPCVD method and performing an etching process, the LPCVD oxide film is left in the form of a spacer, so that a sufficient space and a slope can be secured during subsequent gap filling to prevent defects from occurring. have.

Third, the cell coupling ratio may be prevented from being lowered by preventing sidewall loss of the gate conductive film, thereby preventing deterioration of operating characteristics of the device.

Fourth, even if the device continues to be fine-patterned in the future, it is not necessary to use new equipment, and it is possible to reduce device investment costs by forming a device separator having excellent characteristics using existing equipment.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

1A to 1N are cross-sectional views illustrating a method of forming an isolation layer of a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, the tunnel insulating layer 102, the conductive layer 104, and the device isolation mask 106 are sequentially formed on the semiconductor substrate 100. The tunnel insulating layer 102 may be formed of a silicon oxide layer (SiO ₂ ), and in this case, may be formed by an oxidation process. In the DRAM manufacturing process, the tunnel insulating layer 102 is formed as a gate insulating layer. The conductive film 104 is used as a floating gate of a flash memory device, and may be formed of a polysilicon film, a metal layer, or a laminated film thereof. The conductive film 104 is used as a gate electrode in a DRAM manufacturing process. Preferably, the conductive film 104 is an undoped polysilicon film to lower the concentration of impurities (eg, phosphorus (P)) at the interface between the tunnel insulating film 102 and the floating gate (not shown) to be formed later. (undoped polysilicon) and the doped polysilicon layer (doped polysilicon) may be formed in a laminated structure, it may be formed by performing in-situ or ex-situ process.

The device isolation mask 106 is used as an etch mask in subsequent trench formation, and is used to prevent loss of the conductive film 104. The device isolation mask 106 may be a buffer oxide film (not shown), a device isolation nitride film 108, and a hard material. The mask film 110 may be formed in a stacked structure. In this case, the buffer oxide film may be omitted, and the device isolation nitride film 108 is formed of a nitride film-based material for use as a polishing stop film in a subsequent chemical mechanical polishing (CMP) process for forming a device isolation film. . In addition, the hard mask layer 110 may be formed of an oxide, nitride, SiON, or amorphous carbon.

Next, the trench 112 is formed by etching the device isolation mask 106, the conductive film 104, the tunnel insulating film 102, and the semiconductor substrate 100 in the device isolation region. More specifically described as follows. A photoresist (not shown) is applied on the device isolation mask 106 and an exposure and development process is performed to form a photoresist pattern (not shown) that exposes the device isolation mask 106 in the device isolation region. Subsequently, the device isolation region of the device isolation mask 106 is etched by an etching process using a photoresist pattern. Thereafter, the photoresist pattern is removed. Subsequently, the conductive film 104 and the tunnel insulating film 102 are etched by an etching process using the device isolation mask 106. As a result, the semiconductor substrate 100 in the device isolation region is exposed. In the process of etching the device isolation mask 106, the conductive film 104, and the tunnel insulating film 102, the hard mask film 110 of the device isolation mask 106 is also etched by a predetermined thickness. Subsequently, the semiconductor substrate 100 of the exposed device isolation region is etched to a predetermined depth. As a result, the trench 112 is formed in the device isolation region. As such, the trench 112 may be formed by performing an ASA-STI (Advanced Self Align-Shallow Trench Isolation) process on the semiconductor substrate 100.

Referring to FIG. 1B, a wall oxidation process may be further performed to compensate for damage caused by an etching process for forming the trench 112. In this case, the sidewall oxidation process may be performed by a radical oxidation process to help the oxidation of the device isolation mask 106 and to minimize the smiling phenomenon occurring at both ends of the tunnel insulating layer 102.

As a result, the surface of the exposed tunnel insulating film 102, the conductive film 104, and the device isolation mask 106, as well as the sidewalls and the bottom surface of the trench 108, are oxidized to a predetermined thickness through a radical oxidation process. Not shown) is formed of the sidewall oxide film 114.

Referring to FIG. 1C, a first insulating layer 116 having a liner shape is formed on the sidewall oxide layer 114 to fill a portion of the trench 112. The first insulating film 116 is a tunnel insulating film due to infiltration of H ₂ or SiH ₂ outgassed during the curing process of a polysilazane (PSZ) film to be formed later, and dose ion moving. In order to prevent the deterioration of (102), it should be formed using materials that have been proven reliable. In order to prevent loss of sidewalls of the conductive film 104 during the wet etch process, which is performed for the purpose of securing a subsequent gap-fill margin and securing an etching selectivity, It is formed in the form of a liner using a material having a high etching selectivity.

To this end, the first insulating film 116 is an HDP oxide film or low pressure chemical vapor deposition using a high density plasma (HDP) method having an etching selectivity of about 6 to 10 times higher than that of the PSZ film. It is preferable to form a high temperature oxide (HTO) film using a deposition (LPCVD) method. In this case, the first insulating layer 116 may be formed to a thickness of 150 to 1500 Å so as to suppress the contact between the PSZ film containing a large amount of impurities to be formed later and the tunnel insulating layer 102 as much as possible. In FIG. 1C, the deposition of the HDP oxide film as the first insulating film 116 will be described.

However, when the first insulating layer 116 formed of the HDP oxide film is formed, the thickness of the sidewalls of the trench 112 close to the edge in the remaining region except for the center region of the semiconductor substrate 100 is due to the HDP deposition characteristic. As a result, the first insulating film 116 is inclined to be deposited. That is, since the source gas is supplied from the center top of the semiconductor substrate 100 by using a shower head during HDP deposition, the direction of SiO ₂ falling toward the edge is slightly inclined toward the edge. Asymmetric unbalanced deposition occurs with the direction of As a result, the first insulating film 116 is formed at the bottom of the trench 112 and above the active region than at the sidewalls of the trench 112 and the sidewalls of the tunnel insulating film 102, the conductive film 104, and the device isolation mask 106. It is formed thick.

However, when the thickness of the HDP oxide film is thin as in the first insulating film 116, this phenomenon is inadequate and the trench 112 is completely filled by the PSZ (polysilazane) film which is subsequently deposited. This phenomenon at the time of forming the first insulating film 116 will be ignored.

Referring to FIG. 1D, the second insulating layer 118 is formed by depositing an insulating material on the first insulating layer 114 including the trench 112 to fill the trench 112. The second insulating layer 118 is formed of a spin on dielectric (SOD) insulating layer having the highest fluidity and the best buried property of the trench 112. In this case, PSZ (polysilazane) -based chemical (chemical) may be used to form the SOD insulating film. Therefore, the SOD insulating film can be formed of a PSZ film.

When the second insulating layer 118 is formed of a PSZ film, the PSZ material is deposited by spin coating, followed by a curing process. When the coating process of the PSZ material is performed, since the viscosity of the material itself is low and flows, the trench 112 may be filled without voids.

The curing process is performed at a level of suppressing further smileing of the tunnel insulation film 102 by using a mixing method of a low temperature steam anneal method and a high temperature N ₂ annealing method. At this time, after completion of the curing process, N is desorbed from the PSZ material consisting of Si, H and N, and H is substituted to form a solidified PSZ film made of a SiO ₂ film.

PSZ film has better landfill characteristics than HDP oxide film, but its etching rate is faster than that of wet etchant, and it is rapidly lost when exposed to wet etchant used in subsequent processes. There is this. Therefore, it is necessary to reduce the thickness of the PSZ film so that the PSZ film is not exposed in a subsequent step. This will be described later.

Referring to FIG. 1E, the sidewall oxide film 114, the first insulating film 116, and the second insulating film 118 formed in portions other than the region where the trench 112 is formed by performing the planarization process on the second insulating film 118. Remove it. The planarization process is preferably carried out using a chemical mechanical polishing (CMP) process, and the etching process is preferably performed until the device isolation nitride film 108 of the device isolation mask 106 is exposed. .

Meanwhile, after the planarization process for the second insulating film 118 is performed, a curing process is performed to help the densification of the second insulating film 118 to lower the etch rate of the second insulating film 118 to a controllable level. It can be carried out more. In this case, the curing process may be performed using a mixing method of a low temperature steam annealing method and a high temperature N ₂ annealing method, and may be performed using other methods.

Referring to FIG. 1F, an etching process for lowering the thickness of the second insulating layer 118 is performed. The etching process may be performed by a wet etching process, and may be preferably performed by a wet etchback process. In the wet etch back process, a buffered oxide etchant (BOE) or HF may be used as an etchant. In this case, the wet etchback process is performed to adjust the process time appropriately to secure a subsequent gap fill margin and to secure an etching selectivity so that the second insulating layer 118 is lower than the surface of the semiconductor substrate 100 in the active region. do.

Accordingly, the second insulating film 118 having a higher etching ratio than the first insulating film 116 is quickly etched by the etching process, so that the thickness of the second insulating film 118 is lowered to secure a gap fill margin of the subsequent deposition process. In this case, since the first insulating film 116 having an etching ratio lower than that of the second insulating film 118 is formed on the sidewall of the tunnel insulating film 102, the tunnel insulating film 102 is not exposed when the second insulating film 118 is etched. 116). However, during the etching of the second insulating layer 118, the first insulating layer 116 and the sidewall oxide layer 114 are etched together to expose a portion of the sidewall of the conductive layer 104.

Referring to FIG. 1G, a third insulating film 120 having a liner shape is formed on the device isolation nitride film 108 including the second insulating film 118. Preferably, the third insulating film 120 is formed to a thickness of 150 to 1000 Å using an HDP oxide film.

However, as described above, in the case of forming the third insulating layer 120 made of the HDP oxide film, the trench close to the edge in the remaining region except for the center region of the semiconductor substrate 100 due to the HDP deposition characteristics. The thickness of the sidewalls is lowered, such that the third insulating layer 120 is inclinedly deposited. That is, since the source gas is supplied from the center top of the semiconductor substrate 100 by using a shower head during HDP deposition, the direction of SiO ₂ falling toward the edge is slightly inclined toward the edge. Asymmetric unbalanced deposition occurs with the direction of

As a result, the third insulating film 120 is formed thicker in the trench 112 and in the upper portion of the active region than in the sidewalls of the tunnel insulating film 102, the conductive film 104, and the device isolation nitride film 108. It is formed thinner on the sidewall of the conductive film 104 closer to the edge region than on the sidewall of the conductive film 104 near the center region of the (100). At this time, a moat (A), which is a concave portion in the vertical direction, is generated at one side wall of the conductive film 104 near the edge region of the semiconductor substrate 100.

Referring to FIG. 1H, the portion of the third insulating layer 120 is etched to minimize the insulating layer on the sidewalls of the conductive layer 104 and to bottom-up the bottom of the trench 112 to increase the aspect ratio of the device isolation region. Carry out an etching process. The etching process may be performed by a wet etching process, preferably, by a wet etchback process. In this case, as the etchant during the wet etchback process, diluted hydrofluoric acid (Dilute HF) of 500: 1 to 50: 1 may be used.

As a result, the third insulating film 120 of the sidewall of the conductive film 104 is removed by the etching process to expose a portion of the sidewall of the conductive film 104, and the upper portion of the second insulating film 118 and the active region of the trench 112 are formed. A portion of the third insulating film 120 remains on the nitride film 108 for element isolation in the region. However, the portion in which the mort (A of FIG. 1G) is generated during the etching process of the third insulating layer 120 is also etched by the etchant and changed into a mort (A ′) having a more concave profile than the initial generation.

Referring to FIG. 1I, the fourth insulating layer 122 is formed on the edge of the third insulating layer 120 remaining in the region where the trench 112 is formed to fill the moat A '. The fourth insulating film 122 is an LPCVD oxide film using a Chemical Vapor Deposition (LPCVD) method, preferably a Low Pressure Chemical Vapor Deposition (LPCVD) method to efficiently fill the mort A '. It can be formed as. In this case, the LPCVD oxide film may be formed to a thickness of 50 to 200 kW using an HTO (High Temperature Oxide) film or a TEOS (Tetra Ethyl Ortho Silicate) film.

LPCVD oxide film usually has a buried property. In the case where the mote (A 'in FIG. 1H) is generated, the thickness increases as a whole, but when the two thin film surfaces formed on the sidewall of the conductive film 104 meet each other, the thickness increases. Sources that were supplied to each meet (+) to meet the effect of + α compared to the other place has the effect of faster deposition rate. In addition, the buried portion may be planarized after subsequent deposition.

In addition, LPCVD deposition is a method of making SiO ₂ through a gas phase reaction and attaching it to a substrate. At low pressure, deposition is induced in a low Gibbs' free energy direction. In other words, the part where the moat is generated is filled and the part where the angular is rounded is made through the migration of the molecules themselves.

Accordingly, by using the fourth insulating film 122 made of the LPCVD oxide film, the mortity A 'caused by the deposition characteristics of the HDP oxide film may be evenly embedded to alleviate the lower step and the topology.

Referring to FIG. 1J, an etching process for leaving the fourth insulating layer 122 in the form of a spacer is performed. Here, the etching process may be performed by a dry etching process, preferably may be performed by a spacer etching process.

As a result, all of the horizontal portions of the fourth insulating layer 122 are removed by the spacer etching process, and the vertical portions deposited thicker than the horizontal portions remain to form the fourth insulating layer on the sidewalls of the conductive layer 104 and the nitride film 108 for device isolation. Residue 122 in the form of a spacer has a positive slope. In this case, the fourth insulating film 122 is left to the thickness of 30 to 150 막 on the sidewall of the conductive film 104 in the form of a spacer.

At this time, the portion where the moat A 'is generated by the third insulating film 120 made of the HDP oxide film is preserved in a buried state. Therefore, it is possible to eliminate voids in the subsequent deposition process in advance, and to ensure sufficient space and slope in the subsequent gap fill to prevent the occurrence of defects.

Although not shown, after the fourth insulating film 122 is left in the form of a spacer, a wet dip out process using BOE or diluted HF is further performed to sufficiently secure the space in the trench 112 region. One gap fill margin can be further secured.

Referring to FIG. 1K, the fifth insulating layer 124 is formed on the entire structure including the fourth insulating layer 122 remaining in the form of a spacer. The fifth insulating layer 124 may be formed of an HDP oxide layer.

Referring to FIG. 1L, the third, fourth and fourth insulating layers formed in portions other than the region where the trench 112 is formed by performing the planarization process on the third, fourth and fourth insulating layers 120, 122, and 124. Remove (120, 122, 124). The planarization process is preferably performed using a CMP process, and the etching process is preferably performed until the device isolation nitride film 108 is exposed.

As a result, the device isolation film 126 including the sidewall oxide film 114 and the first to fifth insulating films 116, 118, 120, 122, and 124 is formed in the region where the trench 112 is formed.

As described above, the mortity generated in the third insulating film 120 by the HDP deposition property through the fourth insulating film 122 remaining in the form of a spacer when the device isolation layer 126 is formed according to an embodiment of the present invention. (A ') is sufficiently filled, and void generation is suppressed.

Referring to FIG. 1M, a process of removing the nitride film 108 for device isolation is performed. The removal process may be performed by a wet etching process, preferably, by a wet dip out process using an HF solution and a phosphoric acid (H ₃ PO ₄ ) solution.

As a result, the device isolation nitride film 108 may be selectively removed to expose the upper surface of the conductive film 104, and the sidewalls of the device isolation film 126 may also be exposed, thereby leaving the device isolation film 126 protruding. However, a portion of the third and fourth insulating layers 122 and 124 are also etched together during the etching process for removing the device isolation nitride layer 108, thereby lowering the protrusion of the device isolation layer 126.

However, in the present invention, voids are suppressed when the device isolation layer 126 is formed, so that the sidewalls of the conductive film 104 are not exposed by the loss of the device isolation layer 126 during the removal of the device isolation nitride layer 108. Sidewall attack of the sidewall 104 is prevented to prevent sidewall loss of the conductive layer 104.

As such, when the loss of the sidewall of the conductive film 104 is prevented, the area of the conductive film 104 is prevented from being reduced, thereby preventing the deterioration of the cell coupling ratio. have.

Referring to FIG. 1N, an etching process for controlling the effective field height (EFH) of the device isolation layer 126 in the cell region is performed. In the etching process, the upper portion of the device isolation layer 126 is etched by a predetermined thickness using a solution including HF. As a result, the upper sidewall of the conductive film 104 is exposed. In this case, the etching process may be performed such that the device isolation layer 126 remains higher than the surface of the semiconductor substrate 100 in the active region in order to improve cycling characteristics of the tunnel insulating layer 102.

Meanwhile, in one embodiment of the present invention, the etching process for controlling EFH is performed after removing the device isolation nitride film 108, but the removal process for removing the nitride film 108 for device separation is performed after performing the etching process for controlling the EFH. It may be.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A to 1N are cross-sectional views illustrating a method of forming an isolation layer of a flash memory device according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel insulating film

104: conductive film 106: device isolation mask

108: nitride film for device isolation 110: hard mask film

112 trench 114 sidewall oxide film

116: first insulating film 118: second insulating film

120: third insulating film 122: fourth insulating film

124: fifth insulating film 126: device isolation film

Claims (23)

Forming a trench in an isolation region of the semiconductor substrate by an etching process using an isolation mask; Forming a first insulating film under the trench; Forming a second insulating film on the semiconductor substrate including the first insulating film; Performing an etching process of the second insulating layer to increase an aspect ratio in the device isolation region; And And forming a third insulating film on an edge of the second insulating film so that a moat generated in the second insulating film is filled. The method of claim 1, And the second insulating film is formed of an HDP oxide film. The method of claim 1, The etching process is a device isolation film forming method of a semiconductor device performed by a wet etch back process. The method of claim 3, wherein after the wet etch back process, And the second insulating layer is formed to be asymmetrically inclined due to a lower thickness of the trench sidewalls closer to the edge region than the center region of the semiconductor substrate. The method of claim 1, And the third insulating film is formed of an oxide film using a low pressure chemical vapor deposition method. The method of claim 5, wherein The oxide film using the low pressure chemical vapor deposition method is a device isolation film forming method of a semiconductor device formed of an HTO film or TEOS film. The method of claim 1, And the third insulating film is formed on the sidewall of the conductive film formed in the active region of the semiconductor substrate in the form of a spacer. The method of claim 1, wherein the forming of the third insulating film, Depositing a third insulating film on the second insulating film by a low pressure chemical vapor deposition method so that the mott generated in the second insulating film is filled; And And etching the third insulating film so that the third insulating film remains in the form of a spacer. The method of claim 1, And the first insulating film is formed of a laminated film of an HDP oxide film and a PSZ film. The method of claim 1, And the first insulating film is a laminated film of an HTO film and a PSZ film. The method of claim 9, wherein the forming of the first insulating film, Forming the HDP oxide film on the semiconductor substrate including the trench to fill a portion of the trench; Forming a PSZ film on the HDP oxide film to fill the trench; Performing a planarization etching process so that the HDP oxide layer and the PSZ layer remain only in the trench region; And And performing an etching process of lowering the height of the PSZ film. The method of claim 10, wherein the forming of the first insulating film, Forming an HTO film on the semiconductor substrate including the trench to fill a portion of the trench; Forming a PSZ film on the HTO film to fill the trench; Performing a planarization etching process so that the HTO film and the PSZ film remain only in the trench region; And And performing an etching process of lowering the height of the PSZ film. The method according to claim 11 or 12, The PSZ film is a method of forming a device isolation layer of a semiconductor device formed by coating and curing the PSZ material. The method of claim 13, The curing method is a device isolation film forming method of a semiconductor device using a steam anneal method and a mixed method of N ₂ annealing method. The method according to claim 11 or 12, And curing the planarized PSZ film before the etching process of lowering the height of the PSZ film. The method of claim 15, The curing method is a device isolation film forming method of a semiconductor device using a steam anneal method and a mixed method of N ₂ annealing method. The method of claim 1, wherein after the third insulating film is formed, And performing an etching process of the third insulating film to secure a space in the trench region. The method of claim 1, wherein after the third insulating film is formed, Forming a fourth insulating film on the semiconductor substrate including the third insulating film; Forming a device isolation layer by performing a planarization etching process such that the third and fourth insulating layers remain only in the region where the trench is formed; Removing the device isolation mask; And And performing an etching process of the device isolation layer to control EFH. The method of claim 18, And removing the device isolation mask, wherein the third insulating film remains on the sidewall of the conductive film formed in the active region of the semiconductor substrate to protect the sidewall of the conductive film. Providing a semiconductor substrate having a trench formed in the device isolation region and a multilayered film including a tunnel insulating film and a conductive film in the active region; Forming a first insulating film under the trench; Forming a second insulating film on the semiconductor substrate including the first insulating film; Performing an etching process to increase an aspect ratio in the device isolation region; And And forming a third insulating film on an edge of the second insulating film to fill the mott generated in the second insulating film. The method of claim 20, And the third insulating film is formed of an oxide film using a low pressure chemical vapor deposition method. The method of claim 21, The oxide film using the low pressure chemical vapor deposition method is a device isolation film forming method of a semiconductor device formed of an HTO film or TEOS film. The method of claim 20, And removing the device isolation mask, wherein the third insulating film remains on the sidewall of the conductive film in a spacer form to protect the sidewall of the conductive film.

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