KR20090041249A - Apparatus for driving liquid crystal display of 2 dot inversion type - Google Patents

Abstract

An apparatus for driving a liquid crystal display of 2 dot inversion type is provided to prevent the generation of the horizontal line phenomenon caused by the brightness difference between the horizontal lines. An apparatus for driving a liquid crystal display of 2 dot inversion type comprises a timing controller(61), a gate driving unit(62), a data driving unit(63), and a liquid crystal panel(64). The timing controller outputs a gate control signal(GDC) for controlling the drive of the data driving unit and the gate driving unit; and the data control signal(DDC). The timing controller respectively differently controls the on-period of each gate signal by using the gate masking signal. The gate driving unit outputs the gate signal supplied from the timing controller to each gate line(GL1~GLn) of the liquid crystal panel. The data driving unit supplies the pixel signal to each data line(DL1~DLm) of the liquid crystal panel.

Description

 A driving device of the 2-dot inversion liquid crystal display device {APPARATUS FOR DRIVING LIQUID CRYSTAL DISPLAY OF 2 DOT INVERSION TYPE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technology of a liquid crystal display device, and more particularly, to a driving device of a two-dot inversion liquid crystal display device suitable for preventing a horizontal line phenomenon generated in the two-dot inversion driving method.

Recently, with the development of information technology (IT), the importance of the flat panel display device as a visual information transmission medium has been further emphasized, and low power consumption, thinning, light weight, and high quality are required to secure improved competitiveness in the future.

A liquid crystal display (LCD), which is a typical display device of a flat panel display device, is an apparatus for displaying an image using optical anisotropy of liquid crystal, and has advantages such as thin, small size, low power consumption, and high quality.

Such a liquid crystal display device is a display device in which image information is individually supplied to pixels arranged in a matrix, and a desired image is displayed by adjusting light transmittance of the pixels. Accordingly, the liquid crystal display includes a liquid crystal panel in which pixels, which are the smallest unit for implementing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. Since the LCD does not emit light by itself, a backlight unit is provided to supply light to the LCD. The driver includes a timing controller and a data driver and a gate driver.

FIG. 1 is a block diagram of a liquid crystal display according to the related art, and as shown therein, a gate control signal GDC and a data control signal DDC for controlling driving of the gate driver 12 and the data driver 13. A timing controller 11 for outputting the digital pixel data RGB and reordering the digital pixel data RGB; A gate driver 12 for supplying a gate signal to each gate line GL1 to GLn of the liquid crystal panel 14; A data driver 13 for supplying a pixel signal to each of the data lines DL1 to DLm of the liquid crystal panel 14; It consists of a liquid crystal panel 14 driven by the gate signal and the pixel signal to display an image. The operation thereof will be described as follows.

The timing controller 11 may include a gate control signal GDC for controlling the gate driver 12 and a data control signal for controlling the data driver 13 using a vertical / horizontal synchronization signal and a clock signal supplied from the system. DDC). In addition, the timing controller 11 samples the digital pixel data RGB input from the system, rearranges the digital pixel data RGB, and supplies the same to the data driver 13.

The gate driver 12 sequentially supplies gate signals to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 11, thereby supplying pixel signals. Horizontal lines 14 are selected.

The data driver 13 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 11. The pixel signal thus converted is supplied to the data lines DL1 to DLm on the liquid crystal panel 14.

The liquid crystal panel 14 has a data line (DL1~DLm) and a gate line, to the intersection of the (GL1~GLn) having a plurality of liquid crystal cells (C _LC) disposed in a matrix form a plurality of liquid crystal cells (C _LC Are driven by the pixel signal and the gate signal to display a desired image.

For reference, in the above description, the gate driver 12 and the data driver 13 are described as being separately installed from the liquid crystal panel 14, but recently, they are COF (Chip On Film) and COG (Chip On Glass). There is a tendency to be mounted on the liquid crystal panel 14 by mounting techniques, such as these.

The liquid crystal display uses an inversion method to prevent deterioration of the liquid crystal cells. In particular, the liquid crystal display device provides an excellent image quality compared to other inversion methods, but is vertical two-dot inversion to compensate for the dot inversion method, which consumes more power. Mainly use the method. In other words, flickering occurs when the frame frequency is lowered from 60 Hz to 50 to 30 Hz in order to reduce power consumption when using the dot inversion method. In order to compensate for this, vertical 2 as shown in FIGS. The dot inversion method is used.

2A and 2B illustrate polarities of pixel signals supplied to liquid crystal cells in a vertical two-dot inversion scheme divided into odd frames (previous frames) and even frames (current frames). In the odd and even frames shown in FIGS. 2A and 2B, the vertical two-dot inversion scheme changes the polarity of the pixel signal in dots in the horizontal direction, as in the conventional dot inversion scheme, while in the vertical direction. It is characterized by a change of 2 dots.

However, due to the characteristics of the GIP (GIP: Gate In Panel) model, the output characteristics of the gate signal are not good, and thus the charging time of the pixel is insufficient when the conventional method of outputting the gate signal only in the actual charging period is adopted.

Therefore, the gate of the thin film transistor (TFT), which is a switching element, is opened in advance using a gate signal in a pre-charging period prior to the actual charging period. overlap) Driving method.

3 is a timing diagram of a gate signal to which the gate overlap driving method is applied. That is, FIG. 3A is a waveform diagram of a pixel signal driven in a vertical two-dot inversion scheme, and FIGS. 3B to 3E are gate signals of the gate driver 12 according to the gate overlap driving. 3 is a waveform diagram of GS1 to GS4, and FIG. 3F is a waveform diagram of the gate masking signal GMS.

However, it can be seen that the intervals of the gate masking signal GMS between the first and third gate signals GS1 and GS3 and the second and fourth gate signals GS2 and GS4 are all set to be the same. . As a result, as shown in FIGS. 3B to 3E, it can be seen that the ON sections of all the gate signals GS1 to GS are set at the same interval.

However, in the substantially vertical 2-dot inversion method, due to the load characteristic of the data driver 13, a difference in charging amount appears between the even horizontal line and the odd horizontal line, which is represented by the difference in luminance. For example, FIG. 4 illustrates the charging charge amount of two pixels that are continuous in the vertical direction in FIG. 2A or 2B, and the charging charge Qo of the pixel positioned in the odd horizontal line is on the even horizontal line. It can be seen that less than the charge amount Qe of the located pixel.

The reason for this is that in the case of pixels on the odd horizontal line, the polarity is changed from the positive (+) to the negative (-) signal or vice versa, which requires a relatively long rise time or fall time. This is because the pixels located on the even horizontal line are changed in a signal of the same polarity, so that less time is required.

In this case, based on the TN mode, a pixel located in the odd horizontal line and having a small amount of charging charge Qo is positioned in the even horizontal line, and thus, is brighter than a pixel having a large amount of charged charge Qe. As a result, a luminance difference is generated between the odd horizontal line and the even horizontal line. As a result, a 2-line dim phenomenon occurs on the screen as shown in FIG. 5.

As described above, in the conventional liquid crystal display device to which the vertical two-dot inversion method is applied, the on sections of the gate signals of the horizontal lines are set to be the same. As a result, the charge charging amount of the pixel having the polarity inversion is relatively lower than that of the pixel having the polarity inversion. Accordingly, there is a problem in that a luminance difference is generated between the odd horizontal line and the even horizontal line, which causes a 2-line dim phenomenon.

Accordingly, an object of the present invention is a horizontal line phenomenon caused by a luminance difference between two adjacent horizontal lines by appropriately adjusting an on-section of a gate signal between horizontal lines using a gate masking signal in a liquid crystal display device to which a two-dot inversion driving method is applied. To prevent this from happening.

In order to achieve the above object, the present invention outputs a gate control signal and a data control signal for driving control of a gate driver and a data driver, and a horizontal line having no polarity change of a pixel signal and a horizontal change having a polarity. A timing controller for adjusting and outputting an on period of the gate signal with respect to the line; A gate driver for outputting a gate signal input from the timing controller to each gate line of the liquid crystal panel; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel.

The on period of the gate signal includes a precharging period and a charging period for the pixel signal.

In order to change the interval of the gate signal, the interval of the gate masking signal is adjusted or the output timing of the gate masking signal is adjusted.

According to an exemplary embodiment of the present invention, a horizontal line and a polarity of a pixel signal are changed by appropriately adjusting and outputting an on-section of a gate signal between horizontal lines using a gate masking signal in a liquid crystal display device to which a two-dot inversion driving method is applied. Luminance differences between horizontal lines that do not occur are not generated, whereby a horizontal line phenomenon due to luminance differences between horizontal lines can be reliably prevented from occurring.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is a block diagram showing an embodiment of a driving apparatus of a two-dot inversion liquid crystal display according to the present invention. As shown in FIG. 6, the driving of the gate driver 62 and the data driver 63 is controlled. The gate masking signal is used to output the gate control signal GDC and the data control signal DDC, and to turn on the respective gate signals for the horizontal line having no polarity change and the horizontal line having the polarity change of the pixel signal. A timing controller 61 for adjusting and outputting differently; A gate driver 62 outputting the gate signal supplied from the timing controller 61 to the gate lines GL1 to GLn of the liquid crystal panel 64; A data driver 63 for supplying a pixel signal to each of the data lines DL1 to DLm of the liquid crystal panel 64; The liquid crystal cells arranged in a matrix form by the gate signal and the pixel signal are respectively driven to display an image.

The timing controller 61 includes a data processor 61A for sampling and rearranging digital pixel data RGB input from the outside; Outputs a gate control signal (GDC) and a data control signal (DDC) for controlling the driving of the gate driver 62 and the data driver 63, and also has a horizontal line and a polarity change without a polarity change of the pixel signal. A timing signal generator 61B for outputting respective gate masking signals GMS_even and GMS_odd for the horizontal line; A gate masking signal selecting unit 61C which selects and outputs a corresponding signal among the gate masking signals GMS_even and GMS_odd according to a horizontal line having no polarity change of the pixel signal and a horizontal line having a change of polarity; The on-section of the original gate signal input from the timing signal generator 61B is masked with a gate masking signal input from the gate masking signal selector 61C to change the horizontal line and the polarity of the pixel signal. The gate signal processor 61D is configured to be set differently according to the horizontal line and output to the gate driver 62.

Referring to Figures 7 to 9 attached to the operation of the present invention configured as described above in detail as follows.

The timing signal generator 61B of the timing controller 61 uses a gate control signal for controlling the gate driver 62 using the vertical / horizontal synchronization signal Hsync / Vsync and the clock signal CLK supplied from the system. GDC) and a data control signal DDC for controlling the data driver 63 are output. The data processor 61A of the timing controller 61 samples the digital pixel data RGB input from the system and rearranges the digital pixel data RGB to supply the data driver 63 to the data driver 63.

The gate driver 62 sequentially supplies the gate signals to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 61, thereby supplying pixel signals. 64 horizontal lines are selected.

In more detail, the gate driver 62 shifts the gate start pulse according to the gate shift clock to generate a shift pulse. The gate driver 62 supplies a gate signal consisting of gate on and off sections (signals) to the corresponding gate line GL in a horizontal period in response to the shift clock. In this case, the gate driver 62 supplies the gate-on signal only in the enable period in response to the gate output enable signal, and supplies the gate-off signal (gate low signal) in other periods.

The data driver 63 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 61. The pixel signal thus converted is supplied to the data lines DL1 to DLm on the liquid crystal panel 64.

In more detail, the data driver 63 generates a sampling signal by shifting the source start pulse according to the source shift clock. Subsequently, the data driver 63 sequentially inputs and latches the pixel data RGB in predetermined units in response to the sampling signal. The data driver 63 converts the latched pixel data RGB for one line into an analog pixel signal and supplies the same to the data lines DL1 to DLm. In this case, the data driver 63 converts the positive and negative pixel signals in response to the polarity control signal. For example, the data driver 63 inverts the pixel signal in a vertical two-dot inversion manner in response to a polarity control signal whose polarity is inverted every two horizontal periods. The data driver 63 supplies the pixel signals to the data lines DL1 to DLm only during the enable period in response to the source output enable signal.

The liquid crystal panel 64 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC And a thin film transistor (TFT) connected to each of them.

The thin film transistor TFT is turned on when the gate signal is supplied from the gate line GL, and supplies the pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when the gate off signal is supplied through the gate line GL to maintain the pixel signal charged in the liquid crystal cell C _LC .

The liquid crystal cell C _LC includes a pixel electrode connected to a common electrode and a thin film transistor TFT with a liquid crystal interposed therebetween. The liquid crystal cell C _LC further includes a storage capacitor C _ST so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In the liquid crystal cell C _LC , an arrangement state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, and light transmittance is adjusted accordingly to implement gradation.

For reference, in the above description, the gate driver 62 and the data driver 63 are described as being separately installed from the liquid crystal panel 64. However, in recent years, the gate driver 62 and the data driver 63 are installed on a chip on film (COF) and chip on glass (COG). There is a tendency to be mounted on the liquid crystal panel 64 by mounting techniques, such as these.

The liquid crystal display of the present invention is driven by a vertical two-dot driving method, and uses a gate signal having a precharging period prior to the actual charging period to open a gate of the thin film transistor TFT, which is a switching element, in advance. gate overlap) driving method is applied.

However, when the on periods of all the gate signals are set at the same interval, a difference in charging amount appears between the even horizontal line and the odd horizontal line due to the load characteristic of the data driver 63. The reason is that for pixels located on the odd (or even) horizontal line, the polarity is changed from positive (+) to negative (-) signal and vice versa, requiring a relatively long rise or fall time. While the charging time is insufficient, the pixel located in the even (or odd) horizontal line is changed in the signal of the same polarity, so that less time is required and thus more charging time can be obtained. Because there is.

In this case, based on the TN mode, a pixel located in the odd horizontal line and having a small amount of charge charges is located in the even horizontal line, so that it is relatively brighter than a pixel having a large charge amount, and thus the luminance between the odd horizontal line and the even horizontal line is increased. Differences were generated, thereby causing a 2-Line Dim phenomenon.

Accordingly, in the present invention, the above imbalance of the charging charge amount between the pixels positioned in the odd horizontal line and the even horizontal line is solved by using the gate masking signal, which will be described in detail below.

In the first exemplary embodiment of the present invention, the gate masking signals having different pulse widths are used to adjust the on periods of the gate signals for the horizontal line without the polarity change of the pixel signal and the horizontal line with the polarity change.

To this end, the timing signal generator 61B outputs original gate signals for the odd horizontal lines and the even horizontal lines. The timing signal generator 61B outputs the width of the gate masking signal of the gate signal of the odd horizontal line shorter than the width of the gate masking signal of the gate signal of the even horizontal line.

Here, the odd horizontal line means a horizontal line (n-1 horizontal line, n + 1 horizontal line, n + 3 horizontal line…) in which the polarity of the pixel signal is changed from positive polarity to negative polarity or vice versa, and the even horizontal line Means a horizontal line (n horizontal line, n + 2 horizontal line, n + 4 horizontal line) in which the polarity of the pixel signal is maintained from positive polarity to positive polarity or from negative polarity to negative polarity.

The gate masking signal selector 61C selects and outputs a gate masking signal for the on period of the gate signal of the odd and even horizontal lines at a corresponding time point.

Accordingly, the gate signal processor 61D masks the original gate signal of the odd and even horizontal lines inputted from the timing signal generator 61B with the gate masking signal inputted from the gate masking signal selector 61C. The on section of the gate signal with respect to the odd horizontal line is relatively longer than the on section of the gate signal with the even horizontal line, and the gate signal having the adjusted on section is output to the gate driver 62.

For example, the timing signal generator 61B generates and outputs a gate masking signal for the on period of the gate signal of the odd horizontal line in a short form as shown in FIG. 7 (f), and outputs the gate signal of the even horizontal line. A gate masking signal for the on period of is generated and output in a long form as shown in FIG.

Accordingly, the on periods of the gate signals GS2 and GS4 of the odd horizontal lines output from the gate signal processing unit 61D are relatively long as shown in FIGS. 7B and 7D, which are excellent. The on period of the gate signal of the horizontal line is relatively short as shown in (a) and (c) of FIG.

The gate signals GS1 to GS4 masked as described above by the gate signal processor 61D are output to the gate driver 62.

The gate signals GS1 to GS4 of FIGS. 7A to 7D correspond to the gate signals GS1 to GS4 of FIGS. 3B to 3E.

That is, the gate signal GS1 of the even horizontal line shown in FIG. 7A is a gate signal corresponding to the pixel signal of the nth positive polarity in FIG. 3A.

The gate signal GS2 of the odd horizontal line shown in FIG. 7B is a gate signal corresponding to the n + 1th negative pixel signal in FIG.

The gate signal GS3 of the even horizontal line shown in FIG. 7C is a gate signal corresponding to the pixel signal of the n + 2th negative polarity in FIG. 3A.

The gate signal GS of the odd horizontal line shown in FIG. 7D is a gate signal corresponding to the pixel signal of the n + 3th positive polarity in FIG.

As a result, by masking the gate signal as described above, a luminance difference does not occur between the odd horizontal lines and the even horizontal lines (between two adjacent horizontal lines). This does not occur.

In the second embodiment of the present invention, the timing of the gate masking signal is adjusted to adjust the on periods of the respective gate signals with respect to the horizontal line having no polarity change and the horizontal line having polarity change. The controller 61 includes a data processor 61A for sampling and rearranging digital pixel data RGB input from the outside; Outputs a gate control signal (GDC) and a data control signal (DDC) for controlling the driving of the gate driver 62 and the data driver 63, and also has a horizontal line and a polarity change without a polarity change of the pixel signal. A timing signal generator 61B for adjusting and outputting output timings of the gate masking signals GMS_even and GMS_odd with respect to the horizontal line; A gate masking signal selecting unit 61C which selects and outputs a corresponding signal among the gate masking signals GMS_even and GMS_odd according to a horizontal line having no polarity change of the pixel signal and a horizontal line having a change of polarity; The precharging period or the charging period of the original gate signal input from the timing signal generator 61B is adjusted according to the gate masking signals GMS_even and GMS_odd input from the gate masking signal selector 61C. The gate signal processor 61D outputs differently, which will be described with reference to FIG. 9.

The timing signal generator 61B outputs original gate signals for the odd horizontal lines and the even horizontal lines. FIG. 9A is a waveform diagram of a pixel signal driven in a vertical two-dot inversion scheme, and FIGS. 9B through 9E show gate signals GS1 to B that are output from the timing signal generator 61B. GS4) is a waveform diagram.

The timing signal generator 61B adjusts and outputs a timing of the gate masking signal GMS in order to adjust a precharging period or a charging period for the pixel signal. 9 (h) and (i) are waveform diagrams of even and odd gate masking signals GMS_even and (GMS_odd) in the prior art, and FIGS. 9F and 9G are timing diagrams according to the present invention. The waveforms of the adjusted even and odd gate masking signals GMS_even and GMS_odd are shown.

As shown in FIGS. 9F and 9H, the even gate masking signal GMS_even according to the present invention is output in a delayed form compared to the even gate masking signal GMS_even according to the prior art. 9 (g) and 9 (i), the odd gate masking signal GMS_odd according to the present invention is output in a forward pulled form compared to the excellent gate masking signal GMS_odd according to the prior art.

The gate masking signal selection unit 61C selects even and odd gate masking signals GMS_even and GMS_odd whose timing is adjusted as described above, and outputs them to the gate signal processing unit 61D for each corresponding time point.

Accordingly, the gate signal processor 61D uses the even and odd gate masking signals GMS_even and GMS_odd whose timings input from the gate masking signal selector 61C are adjusted. The precharging section and the charging section of the gate signal of the odd and even horizontal lines inputted from 61B are adjusted and output.

The gate signal GS1 of the even horizontal line shown in FIG. 9B represents a gate signal corresponding to the pixel signal of the nth positive polarity, and the gate signal processing unit 61D has an even, whose timing is adjusted. Using the odd gate masking signals GMS_even and GMS_odd, the charging period of the gate signal is reduced and output.

The gate signal GS2 of the odd horizontal line shown in (c) of FIG. 9 represents a gate signal corresponding to the pixel signal of the n + 1th negative polarity, and the timing of the gate signal processor 61D is adjusted. By using the even-numbered even-numbered gate masking signals GMS_even and GMS_odd, the precharging period of the on-signal of the gate signal is reduced and output.

The gate signal GS3 of the even horizontal line shown in FIG. 9D represents a gate signal corresponding to an n + 2th negative pixel signal, and the timing of the gate signal processor 61D is adjusted. By using the even-numbered odd-numbered gate masking signals GMS_even and GMS_odd, the charging period of the gate signal is reduced and output.

The gate signal GS4 of the odd horizontal line shown in FIG. 9E represents a gate signal corresponding to an n + 3th positive polarity pixel signal, and the gate signal processor 61D adjusts the timing. The even and odd gate masking signals GMS_even and GMS_odd are used to reduce and output the precharging interval among the on periods of the gate signal.

In other words, the gate signal processor 61D changes polarity as shown in FIGS. 9B and 9D by using the even and odd gate masking signals GMS_even and GMS_odd whose timing is adjusted as described above. For the gate signals GS1 and GS3 of the even horizontal line without the output, the charging section is output by reducing the charging period among the on periods of the gate signal, and the radix horizontal line having the polarity change as shown in FIGS. 9C and 9E. For the gate signals GS2 and GS4, the precharging period is reduced in the on period of the gate signal and output.

Therefore, a luminance difference does not occur between the odd horizontal line and the even horizontal line, so that a 2-line dim phenomenon does not occur as shown in FIG. 8.

1 is a block diagram of a liquid crystal display device according to the prior art.

2A and 2B are pixel polarity arrangement diagrams of a frame in a vertical 2-dot inversion scheme.

Fig. 3A is a waveform diagram of a pixel signal of the vertical 2-dot inversion method.

3B and 3E are waveform diagrams of gate signals.

3F is a waveform diagram of a gate masking signal.

4 is a waveform diagram showing the charge amount of an even-numbered pixel.

5 is a schematic diagram of a screen in which a horizontal line phenomenon occurs due to a luminance difference between adjacent horizontal lines;

6 is a block diagram of a vertical two-dot inversion liquid crystal display device according to the present invention;

7A to 7D are waveform diagrams of gate signals according to the present invention.

7 (e) and 7 (f) are waveform diagrams of odd and excellent gate masking signals applied to the present invention. 8 is a schematic diagram of a screen in which a luminance difference between adjacent horizontal lines is eliminated according to the present invention so that a horizontal line phenomenon does not appear.

Fig. 9A is a waveform diagram of a pixel signal of the vertical 2-dot inversion method.

9B and 9E are waveform diagrams of gate signals.

9 (f) and 9 (g) are waveform diagrams of even and odd gate masking signals whose timing is adjusted according to the present invention.

9 (h) and 9 (i) are waveform diagrams of the original even and odd gate masking signals.

*** Description of the symbols for the main parts of the drawings ***

61: timing controller 61A: data processing unit

61B: timing signal generator 61C: gate masking signal selector

61D: gate signal processor 62: gate driver

63: data driver 64: liquid crystal panel

Claims (9)

A timing controller which outputs a driving control signal of the gate driver and the data driver, and adjusts and outputs an on-section of the gate signal for a horizontal line having no polarity change and a horizontal line having a polarity change of the pixel signal; A gate driver for outputting a gate signal input from the timing controller to each gate line of the liquid crystal panel; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel according to a data control signal input from the timing controller. The apparatus of claim 1, wherein the timing controller is configured to adjust an on period of the gate signal by using a gate masking signal having different periods. The method of claim 1, wherein the timing controller is A data processor for sampling digital pixel data RGB input from the outside and rearranging the digital pixel data RGB; A timing signal for outputting driving control signals of the gate driver and the data driver, and outputting respective gate masking signals GMS_even and GMS_odd for horizontal lines having no polarity change and pixel lines having no polarity change of the pixel signal. A generator; A gate masking signal selecting unit which selects and outputs a corresponding signal among the gate masking signals GMS_even and GMS_odd according to a horizontal line having no polarity change of the pixel signal and a horizontal line having a change of polarity; Mask the original gate signal input from the timing signal generator with the gate masking signal input from the gate masking signal selector so that the ON periods of the gate signal for the horizontal line without polarity change and the horizontal line with polarity change are different. And a gate signal processor for outputting the gate driver to the gate driver. The apparatus of any one of claims 1 to 3, wherein the on period of the gate signal includes a precharging period and a charging period. The apparatus of claim 1, wherein the liquid crystal panel is driven in a TN mode. The apparatus of claim 1, wherein the timing controller is configured to adjust an on period of the gate signal by adjusting a timing of the gate masking signal. The method of claim 1, wherein the timing controller is A data processor for sampling digital pixel data RGB input from the outside and rearranging the digital pixel data RGB; In addition to outputting the drive control signal of the gate driver and the data driver, the output timing of each gate masking signal (GMS_even) or (GMS_odd) is adjusted for a horizontal line having no change in polarity of the pixel signal and a horizontal line having a change in polarity. A timing signal generator for outputting; A gate masking signal selecting unit which selects and outputs a corresponding signal among the gate masking signals GMS_even and GMS_odd according to a horizontal line having no polarity change of the pixel signal and a horizontal line having a change of polarity; A gate signal processor for controlling the precharging period or the charging period of the original gate signal input from the timing signal generator according to the gate masking signals GMS_even and GMS_odd and outputting differently. A two-dot inversion liquid crystal display device drive device, characterized in that consisting of. 8. The apparatus of claim 7, wherein the gate masking signal (GMS_even) is output later than the original gate masking signal. 8. The apparatus of claim 7, wherein the gate masking signal (GMS_odd) is output faster than the original gate masking signal.

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