KR20090012573A - 반도체 소자 및 그 제조 방법 - Google Patents

반도체 소자 및 그 제조 방법 Download PDF

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Publication number
KR20090012573A
KR20090012573A KR1020070076505A KR20070076505A KR20090012573A KR 20090012573 A KR20090012573 A KR 20090012573A KR 1020070076505 A KR1020070076505 A KR 1020070076505A KR 20070076505 A KR20070076505 A KR 20070076505A KR 20090012573 A KR20090012573 A KR 20090012573A
Authority
KR
South Korea
Prior art keywords
region
etch stop
gate electrode
gate structure
stop layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020070076505A
Other languages
English (en)
Korean (ko)
Inventor
이주원
신동석
김태균
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020070076505A priority Critical patent/KR20090012573A/ko
Priority to US12/165,999 priority patent/US20090032881A1/en
Priority to JP2008192141A priority patent/JP2009033173A/ja
Publication of KR20090012573A publication Critical patent/KR20090012573A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020070076505A 2007-07-30 2007-07-30 반도체 소자 및 그 제조 방법 Withdrawn KR20090012573A (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020070076505A KR20090012573A (ko) 2007-07-30 2007-07-30 반도체 소자 및 그 제조 방법
US12/165,999 US20090032881A1 (en) 2007-07-30 2008-07-01 Semiconductor devices and methods of fabricating the same in which a mobility change of the major carrier is induced through stress applied to the channel
JP2008192141A JP2009033173A (ja) 2007-07-30 2008-07-25 半導体素子およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070076505A KR20090012573A (ko) 2007-07-30 2007-07-30 반도체 소자 및 그 제조 방법

Publications (1)

Publication Number Publication Date
KR20090012573A true KR20090012573A (ko) 2009-02-04

Family

ID=40337314

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070076505A Withdrawn KR20090012573A (ko) 2007-07-30 2007-07-30 반도체 소자 및 그 제조 방법

Country Status (3)

Country Link
US (1) US20090032881A1 (https=)
JP (1) JP2009033173A (https=)
KR (1) KR20090012573A (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180123420A (ko) * 2017-05-08 2018-11-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 로우 k 스페이서 형성 방법
KR20190037068A (ko) * 2017-09-28 2019-04-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 차등층 형성 프로세스 및 그에 의해 형성되는 구조물
KR20200014254A (ko) * 2018-07-31 2020-02-10 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스 및 제조 방법
US11532507B2 (en) 2018-10-31 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US12593495B2 (en) 2018-07-31 2026-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7767534B2 (en) * 2008-09-29 2010-08-03 Advanced Micro Devices, Inc. Methods for fabricating MOS devices having highly stressed channels
US9202913B2 (en) * 2010-09-30 2015-12-01 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor structure
US9142462B2 (en) * 2010-10-21 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a contact etch stop layer and method of forming the same
DE102018101511B4 (de) * 2017-09-28 2021-03-18 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zur Halbleiterverarbeitung zum Bilden einer differenziellen Ätzstoppschicht

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972754A (en) * 1998-06-10 1999-10-26 Mosel Vitelic, Inc. Method for fabricating MOSFET having increased effective gate length
US6521502B1 (en) * 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6825529B2 (en) * 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US7279746B2 (en) * 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US20050275034A1 (en) * 2004-04-08 2005-12-15 International Business Machines Corporation A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance
US7615426B2 (en) * 2005-02-22 2009-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. PMOS transistor with discontinuous CESL and method of fabrication
US7445978B2 (en) * 2005-05-04 2008-11-04 Chartered Semiconductor Manufacturing, Ltd Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
US20070023845A1 (en) * 2005-07-26 2007-02-01 Fujitsu Limited Semiconductor device and method for fabricating the same
DE102006040765B4 (de) * 2006-08-31 2011-02-03 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Feldeffekttransistors mit einer verspannten Kontaktätzstoppschicht mit geringerer Konformität und Feldeffekttransistor

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180123420A (ko) * 2017-05-08 2018-11-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 로우 k 스페이서 형성 방법
US10361282B2 (en) 2017-05-08 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a low-K spacer
US12563806B2 (en) 2017-05-08 2026-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a low-k spacer
KR20190037068A (ko) * 2017-09-28 2019-04-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 차등층 형성 프로세스 및 그에 의해 형성되는 구조물
US10763104B2 (en) 2017-09-28 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming differential etch stop layer using directional plasma to activate surface on device structure
US10804271B2 (en) 2017-09-28 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and device each having differential etch stop layer over gate spacer
KR20200014254A (ko) * 2018-07-31 2020-02-10 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스 및 제조 방법
US11600530B2 (en) 2018-07-31 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US12593495B2 (en) 2018-07-31 2026-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11532507B2 (en) 2018-10-31 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Also Published As

Publication number Publication date
JP2009033173A (ja) 2009-02-12
US20090032881A1 (en) 2009-02-05

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20070730

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid