KR20080062576A - Manufacturing method of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent the generation of a parasitic transistor by blocking the loss of an isolation layer. An isolation layer(202) defining an active region is formed on a semiconductor substrate(200). A dielectric(216) is formed on the semiconductor substrate. The dielectric is thicker at the isolation layer part than at the active region. A mask pattern exposing the hard mask layer and the gate forming region is formed on the dielectric. The exposed hard mask layer and the dielectric are etched to form a hard mask layer pattern and a dielectric pattern. The semiconductor substrate is etched by using the hard mask layer pattern and the dielectric pattern as etching masks to form grooves(R,R',P). The mask pattern is a line-type recess mask pattern. When the exposed hard mask layer and the dielectric are etched to form the hard mask layer pattern and the dielectric pattern, a partial thickness on the active region substrate and a partial thickness on the isolation layer are removed.

Description

Manufacturing method of semiconductor device

1A to 1D are cross-sectional views illustrating processes for forming a recess gate of a conventional semiconductor device.

2A to 2D are cross-sectional views illustrating processes for forming a recess gate in a semiconductor device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: semiconductor substrate 202: device isolation film

216: sidewall oxide film

R, R ', P: home

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to minimize parasitic transistors that may be induced between active regions and passing gates of adjacent device isolation layers by minimizing oxide loss of the device isolation layers, thereby improving yield of semiconductor devices. The manufacturing method of the semiconductor element which can be performed.

As the integration of semiconductor memory devices is advanced, the conventional planar transistor structure suffers from the problem of reducing the threshold voltage margin and the refresh time of the cell region, thereby refreshing while securing the threshold voltage corresponding to the high integration of semiconductor memory devices. Various studies are being actively conducted to secure the characteristics.

Thus, a recess gate MOSFET structure has been proposed. The recess gate MOSFET structure recesses a channel region to form a groove, and forms a gate on the groove to increase an effective channel length, and a short channel effect. ), The device characteristics can be improved.

Here, before the recess gate MOSFET structure is proposed, a shallower junction is formed as the channel length is reduced to secure a drain-induced barrie lowering (DIBL) margin of a short channel.

Of course, although the basic process is to form a layer through the ion implantation in the lower region of the source and drain by blocking the drift current due to the strong electric field between the source and drain of the MOSFET, nanometer (nm) class It is inevitable to use a transistor having a three-dimensional shape, such as a recess gate MOSFET structure, since it is necessary to reduce the source and drain depletion region to form the channel length.

On the other hand, in recent years, as the channel length increases, the doping concentration of the substrate can be reduced, and a bulb type recess gate, which can be improved by drain-induced barrier lowering (DIBL), has been commercialized.

However, although the recess gate MOSFET is advantageous in terms of the short channel margin side and the refresh time securing side, the distance between the recess gate of the active region and the passing gate of the adjacent device isolation layer is close to that of the groove forming the passing gate. When the depth becomes deep, that is, when the loss of the oxide film forming the device isolation film is large, parasitic leakage becomes large in this part.

1A to 1D are cross-sectional views illustrating processes for forming a recess gate of a conventional semiconductor device.

Referring to FIG. 1A, an insulating film 104 is formed on a semiconductor substrate 100 on which an isolation layer 104 formed of an oxide film defining an active region is formed. Then, an amorphous carbon film 106, a SiON film 108, an OBARC (Organic Bottom ARC: 110) film, and an argon fluoride photoresist (ArF Photoresist) film are formed on the insulating film 104. 112 is sequentially formed, and the argon fluoride photoresist 112 is patterned to expose the recess gate forming region.

At this time, the insulating film 104 is formed by Low Pressure-Tetra Ethyl Ortho Silicate (LP-TEOS) or High Thermal Oxide (HTO) process, and the insulating film 104 formed by the process is 70-95% of step coverage ( The thickness of the insulating film 104 formed on the active region and the device isolation film is almost the same because it is formed of a step coverage.

Referring to FIG. 1B, an amorphous carbon film 106 which is an OBARC film (not shown), a SiON film (not shown), and a hard mask film in an exposed region using the patterned argon fluoride photoresist 106 as a mask pattern. Etch At this time, the silicon and oxide films in the regions where the recess gates and the passing gates are to be formed in the active region and the device isolation layer 102 of the semiconductor substrate 100 are etched on the amorphous carbon film 106 as the hard mask film. Etch little by little to expose it. Thereafter, the argon fluoride photoresist (not shown), the OBARC film (not shown), and the SiON film (not shown) are removed.

Referring to FIG. 1C, an etching process of the amorphous carbon film 106 remaining on the semiconductor substrate 100 using an etching mask is performed to pass through the region in which the recess gate is formed in the active region and the device isolation layer 102. Grooves R and P are formed in regions where gates are to be formed.

At this time, no matter how high the etching selectivity of the oxide film forming the device isolation film 102, the device isolation film 102 is formed during the etching of 1,000 ~ 1,500 실리콘 silicon to form a groove (R) in the active region and the oxide film The groove P is formed by etching about 100 to 300 Å, and the etching degree of the oxide layer constituting the device isolation layer 102 is etched to a deeper depth than the portion where the storage node contact of the active region is to be formed.

Referring to FIG. 1D, the sidewall oxide layer 114 is formed on the semiconductor substrate 100 including the surfaces of the grooves R and P for forming the recess gates of the semiconductor substrate subjected to the etching process. Then, the entire sidewall etch process is performed on the sidewall oxide layer 114 to leave the sidewall oxide layer 114 only on the sidewalls of the patterns formed on the semiconductor substrate 100, and then to the bottom of the groove R formed in the active region. An isotropic etching process is performed to form a bulb type groove R '. In this case, when the front side etching process and the anisotropic etching process are performed, the loss of the oxide film forming the device isolation layer is further increased.

Thereafter, although not shown, a semiconductor device manufacturing process including a gate forming process is performed on the semiconductor substrate by a known method.

However, as described above, the oxide layer forming the device isolation layer by the front side etching process and the anisotropic etching process when forming the groove for forming the recess gate in the active region is more than the portion where the storage node contact of the active region is to be formed. Passing gates are formed to be lost to deep depths, which causes parasitic transistors between the storage node contacts in the active region and adjacent passing gates, causing malfunctions of the cell region transistors.

The present invention provides a method of manufacturing a semiconductor device which can improve the yield of a semiconductor device by minimizing the oxide loss of the device isolation layer to prevent parasitic transistors that may be induced between the active region and the passivation gate of the adjacent device isolation layer.

In one embodiment, a method of manufacturing a semiconductor device includes forming an insulating film on a semiconductor substrate on which a device isolation film defining an active region is formed so as to have a thickness greater than that in an active region in a portion of the device isolation film; Forming a mask pattern exposing a hard mask layer and a gate formation region on the insulating layer; Etching the exposed hard mask layer and the insulating layer to form a hard mask layer pattern and an insulating layer pattern; And etching the substrate to form the groove by using the hard mask pattern and the insulating layer pattern as an etching mask.

The mask pattern may be a line type recess mask pattern.

When the exposed hard mask film and the insulating film are etched to form the hard mask film pattern and the insulating film pattern, the partial thickness of the active region substrate and the partial thickness of the insulating film on the device isolation layer are removed.

The insulating film is formed of an oxide film.

Forming a groove by etching the substrate using the hard mask pattern and the insulating layer pattern as an etch mask, and forming a sidewall oxide layer on the semiconductor substrate including the surfaces of the grooves; Performing a front-side etching process on the semiconductor substrate to leave a sidewall oxide film on the sidewalls of the grooves; And forming a bulb-type groove by using the hard mask pattern and the remaining sidewall oxide layer as an etch mask.

The device isolation film is formed of an oxide film.

The hard mask film is formed of an amorphous carbon film.

The mask pattern may be formed of argon fluoride photoresist.

A SiON film and an organic bottom arc (OBARC) film are formed between the hard mask film and the mask pattern.

The insulating film formed on the active region is formed to have a thickness of 10 to 50% of the insulating film formed on the device isolation film.

The insulating film is formed by a PECVD process.

The PECVD process includes a substrate temperature of 300 to 450 ° C., a process pressure of 10 to 50 Torr, SiH ₄ + N ₂ O, SiH ₄ + O ₂ , Si ₂ H ₆ + N ₂ O, Si ₂ H ₆ + O ₂ Or Si (C ₂ H ₅ O) + O ₂ It is characterized by using any one of the compounds as a source (Source) gas.

The insulating film formed by the PECVD process has a step coverage of 30 to 50%.

After forming an insulating film on the semiconductor substrate, and before forming a hard mask film on the insulating film, the semiconductor substrate is dip into a 300: 1 BOE (Buffered Oxide Etch) solution or HF solution for 1 to 3 seconds. It characterized in that it further comprises the step).

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the manufacturing process of a recess gate MOSFET type semiconductor device having a three-dimensional transistor structure, the present invention is formed by a PECVD method having a step coverage of 50% or less when forming a recess gate groove. A poor oxide film is used as the insulating film to prevent loss of the device isolation film in the passing gate portion.

That is, when LP-TEOS and HTO used as insulating films form grooves for forming recess gates, there is no difference in height formed on the active region and the device isolation film, thereby forming the device isolation film in various etching processes. In order to solve the problem of large loss of oxide film, an oxide film formed by PECVD method having poor step coverage of 10 to 50% is adopted as an insulating film so that the thickness of the oxide film on the device isolation film is made thicker than the active region so as to be recessed. The loss of the oxide film forming the device isolation film is prevented in various etching processes for forming the groove of the gate.

Therefore, the loss of the oxide film forming the conventional device isolation film is improved by about 200 to 400 GPa, and the distance between the storage node contact formed in the semiconductor device manufacturing process and the adjacent passing gate formed in the device isolation film is prevented to prevent the occurrence of parasitic leakage. As a result, electrical short circuit between the storage node contact and the passing gate of the device isolation layer may be prevented and the yield of the semiconductor device may be improved.

2A through 2D are cross-sectional views illustrating processes of forming a recess gate of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, an insulating film 216 is formed on the semiconductor substrate 200 on which the device isolation film 204 formed of an oxide film defining an active region is formed. Next, an amorphous carbon film 206, a SiON film 208, an organic bottom ARC 110, an OBARC film, and an argon fluoride photoresist (ArF Photoresist) are formed on the insulating film 214. 212 is sequentially formed, and the argon fluoride photoresist 212 is patterned to expose the recess gate forming region.

In this case, the insulating film is an oxide film formed by a PECVD method having a poor step coverage of 30 to 50%, the insulating film 216 is formed by using a PECVD method to form an upper portion of the device isolation layer as a flat target (Target) of the oxide film formation The height of the insulating layer 216 formed on the semiconductor substrate 200 is about half or less than that of the device isolation layer in the active region because the active region where the recess gate is to be formed is lower in planar height than the device isolation layer. Has

In addition, the process conditions for forming the insulating film by the PECVD method is SiH ₄ + N ₂ O, SiH ₄ + O ₂ , Si ₂ H ₆ + N ₂ O, Si ₂ H ₆ + O at a substrate temperature of 300 ~ 450 ℃ ₂ Or Si (C ₂ H ₅ O) + O ₂ Compounds such as these are used as the source material. In particular, a SiH ₄ compound having a high sticking coefficient is advantageous as a source material to form an insulating film having poor step coverage. In the general PECVD process, the process pressure is 0.1 to 5 Torr, but the process is performed at a high pressure of 10 to 50 Torr to reduce the thickness of the insulating film 216 formed on the active region.

Referring to FIG. 2B, an amorphous carbon film 206 which is an OBARC film (not shown), a SiON film (not shown), and a hard mask film in an exposed region using the patterned argon fluoride photoresist 212 as a mask pattern. Etch

In this case, since the thickness of the insulating film 216 formed on the semiconductor substrate 200 is less than half of the thickness of the device isolation film region in the active region, the thickness of the amorphous carbon film 206 which is a hard mask film may be reduced. In the etching process, the insulating layer 216 is etched in the active region to expose the silicon of the active region to the outside. However, in the device isolation film 202 region, the oxide film forming the device isolation film 202 is etched while the insulating film 216 in the active region is etched to expose the silicon. The oxide film is not exposed to the outside. Thereafter, the argon fluoride photoresist (not shown), the OBARC film (not shown), and the SiON film (not shown) are removed.

Referring to FIG. 2C, the etching process is performed on the amorphous carbon film 206 remaining on the semiconductor substrate 100 using an etching mask to form a groove R in an area where a recess gate is to be formed in an active region. . At this time, the groove P is also formed in the device isolation film 202.

At this time, in the process of forming the groove R for forming the recess gate in the active region, an etching process of the insulating layer 216 is performed in the device isolation layer 202 to form the groove in the active region. Even after this, the loss of the oxide film forming the device isolation film 202 hardly occurs.

Referring to FIG. 2D, the sidewall oxide layer 214 is formed on the semiconductor substrate 100 including the surfaces of the grooves R and P for forming the recess gates of the semiconductor substrate 200 subjected to the etching process. . Then, the entire sidewall etching process is performed on the sidewall oxide layer 214 to leave the sidewall oxide layer 214 only on the sidewalls of the patterns formed on the semiconductor substrate 200, and to be non-overlaid on the bottom of the groove R formed in the active region. An isotropic etching process is performed to form a bulb type groove R '. In this case, even if a loss of the oxide layer forming the device isolation layer occurs through the anisotropic etching process, the depth does not occur to the depth at which the storage node contact is formed.

Thereafter, although not shown, a semiconductor device manufacturing process including a gate forming process is performed on the semiconductor substrate by a known method.

On the other hand, the oxide film formed by the PECVD method in the stepped bone portion is characterized by a fast wet etching rate. Accordingly, in order to reduce the oxide loss of the device isolation layer 202 where the pass gate is to be formed by the etching process, an insulating film formed by PECVD is formed, and the semiconductor substrate 200 is immersed in a 300: 1 buffered oxide etching (BOE) solution. After dipping for 1 to 10 seconds and performing a cleaning and drying process, an amorphous carbon film or the like, which is a hard mask film, is formed on the insulating film 216. As described above, when the dip process is performed, the insulating film 216 formed in the active region portion is removed more quickly than the region of the device isolation layer 204 to further increase the oxide thickness difference between the device isolation layer portion and the active region portion. Afterwards, the time for forming the grooves R in the active region may be shortened even in the etching process, thereby reducing the loss of the oxide film forming the device isolation layer.

By using the insulating film formed by the PECVD method in manufacturing the semiconductor device as described above, it is possible to minimize the loss of the oxide film forming the device isolation film due to the etching during the formation of the grooves for forming the recess gate, and thus have a quality of 60 nm or less. A semiconductor device can be manufactured.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention uses the insulating film of the semiconductor device formed by the PECVD method having a poor step coverage of 10 to 50%, thereby preventing the loss of the device isolation film during the manufacturing process of the semiconductor device to prevent the active region and the adjacent device isolation film It is possible to prevent the generation of parasitic transistors, which may be caused between passing gates formed in the gate.

As a result, malfunction of the device can be prevented and the yield of the semiconductor device can be improved.

Claims (14)

Forming an insulating film on the semiconductor substrate on which the device isolation film defining the active region is formed so as to have a thickness thicker than that in the active region; Forming a mask pattern exposing a hard mask layer and a gate formation region on the insulating layer; Etching the exposed hard mask layer and the insulating layer to form a hard mask layer pattern and an insulating layer pattern; Etching the substrate to form a groove by using the hard mask pattern and the insulating layer pattern as an etching mask; A method of manufacturing a semiconductor device, comprising. The method of claim 1, The mask pattern is a method of manufacturing a semiconductor device, characterized in that the line-type recess mask pattern. The method of claim 1, And forming a hard mask layer pattern and an insulating layer pattern by etching the exposed hard mask layer and the insulating layer, wherein a part thickness of the active region substrate and a part thickness of the insulating layer on the device isolation layer are removed. The method of claim 1, And said insulating film is formed of an oxide film. The method of claim 1, Forming a groove by etching the substrate using the hard mask pattern and the insulating layer pattern as an etch mask, and forming a sidewall oxide layer on the semiconductor substrate including the surfaces of the grooves; Performing a front-side etching process on the semiconductor substrate to leave a sidewall oxide film on the sidewalls of the grooves; And Forming a bulb-type groove by using the hard mask pattern and the remaining sidewall oxide layer as an etching mask; To The method of manufacturing a semiconductor device further comprising. The method of claim 1, The device isolation film is a semiconductor device manufacturing method, characterized in that formed of an oxide film. The method of claim 1, The hard mask film is a semiconductor device manufacturing method, characterized in that formed with an amorphous carbon (Amorphous carbon) film. The method of claim 1, The mask pattern is a method of manufacturing a semiconductor device, characterized in that formed with ArF photoresist (ArF Photoresist). The method of claim 1, A method of manufacturing a semiconductor device, comprising forming a SiON film and an organic bottom arc (OBARC) film between the hard mask film and the mask pattern. The method of claim 1, The insulating film formed on the active region is formed to have a thickness of 10 to 50% of the insulating film formed on the device isolation film. The method of claim 1, The insulating film is a method of manufacturing a semiconductor device, characterized in that formed by PECVD process. The method of claim 11, The PECVD process includes a substrate temperature of 300 to 450 ° C., a process pressure of 10 to 50 Torr, SiH ₄ + N ₂ O, SiH ₄ + O ₂ , Si ₂ H ₆ + N ₂ O, Si ₂ H ₆ + O ₂ Or Si (C ₂ H ₅ O) + O ₂ A method for manufacturing a semiconductor device, using any one of the compounds as a source gas. The method of claim 1, The insulating film formed by the PECVD process has a step coverage of 30 to 50%. The method of claim 1, After forming an insulating film on the semiconductor substrate, and before forming a hard mask film on the insulating film, the semiconductor substrate is dip into a 300: 1 BOE (Buffered Oxide Etch) solution or HF solution for 1 to 3 seconds. Method for manufacturing a semiconductor device characterized in that it further comprises a).

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