KR100728994B1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to improve effectively operation characteristics of device by increasing the width of a gate channel using an active region with a recess. A semiconductor substrate(41) includes an isolation region and an active region, wherein the active region is partially recessed. An isolation layer(43) is formed within the isolation region of the substrate. A gate(48) is formed on the recessed portion of the active region. The recessed portion is formed like an U type structure. The depth of the recessed portion of the active region is in a range of 100 to 5000 A. The recessed portion is started from a predetermined position spaced apart from the isolation layer as much as 20 to 500 A.

Description

Semiconductor device and method for manufacturing same {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

1 is a cross-sectional view for explaining a conventional problem.

2 is a plan view of a general semiconductor device.

3 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, corresponding to lines A-A 'and B-B' in FIG.

4A to 4H are cross-sectional views illustrating processes for manufacturing a semiconductor device according to an embodiment of the present invention, corresponding to lines A-A 'and B-B' in FIG.

Explanation of symbols on the main parts of the drawings

41: semiconductor substrate 42: hard mask

T: trench 43: device isolation film

44 spacer 45 gate insulating film

46: gate conductive film 47: gate hard mask film

48: gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device capable of improving the operating characteristics and manufacturing yield of a semiconductor device by increasing the width of a gate channel without an etching process of an isolation layer. It is about a method.

Recently, as the design rule of the highly integrated semiconductor device is drastically reduced to less than 100 nm, the channel length and width of the gate are correspondingly reduced, and the doping concentration to the junction region is increased, thereby increasing the electric field. As the increase, the junction leakage current increases. As a result, it is difficult to obtain a threshold voltage value required by a highly integrated device using a conventional planar channel structure transistor, and reaches a limit in improving refresh characteristics. Accordingly, research on the idea of realization of a gate having a three-dimensional channel structure capable of expanding a channel region and actual process development studies are being actively conducted.

One such effort has recently been proposed in the field of logic devices (Fin Gate) having a channel having a three-dimensional structure. The protruding gate has a structure in which a part of the active region is etched by etching the device isolation layer and a gate line is formed to surround the protruding active region. In this case, the effective channel width is increased to drive current through the channel. ) Characteristic and threshold voltage margin are improved.

On the other hand, in order to improve the buried characteristics when the device isolation region becomes fine due to the high integration of the semiconductor device, the lower portion of the device isolation layer is formed of a fluid insulating film, for example, a spin-on glass (SOG) film and the top of the device isolation layer Is formed of a dense insulating film, for example, an HDP (High Density Plasma) film.

However, in the above-described conventional technique, due to the difference in etching speed between the fluid insulating layer 11 and the dense insulating layer 12, as shown in FIG. 1, the lower portion of the device isolation layer 13 is more etched to cause the bowing phenomenon. Will occur. For this reason, there is a problem in that the operation characteristics of the semiconductor device are deteriorated, such that the gate conductive film remains in a portion where the bowing phenomenon occurs in a subsequent gate forming process, causing an electrical short.

Accordingly, an object of the present invention is to provide a semiconductor device capable of increasing the width of a gate channel without etching the device isolation layer, and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can improve the operating characteristics and manufacturing yield of the semiconductor device by increasing the width of the gate channel without etching the device isolation layer.

A semiconductor device of the present invention for achieving the above object, a semiconductor substrate having an isolation region and a recessed active region; An isolation layer formed in the isolation region of the semiconductor substrate; And a gate formed in the recessed substrate active region, wherein the entirety of the active region is recessed except for the portion in contact with the device isolation layer.

Here, the recessed active region is characterized by having a "U" shape.

The active region is recessed by a depth of 100 to 5000 microns.

The active region is recessed in its entirety except for the width of 20 to 500 으로부터 from the interface of the device isolation layer.

In addition, the method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of: forming a hard mask on the semiconductor substrate having an active region and an isolation region; Etching the substrate device isolation region exposed by the hard mask to form a trench; Forming an isolation layer in the trench; Removing the hard mask to protrude the device isolation layer over the substrate; Forming spacers on sidewalls of the device isolation film portions protruding from the substrate; Recessing the substrate active region using the device isolation layer including the spacer as an etch mask; Removing a portion of the device isolation layer protruding from the spacer and the substrate; And forming a gate on the recessed active region; Characterized in that it comprises a.

Here, the active region is characterized in that the recessed to have a "U" shape.

The active region is recessed by a depth of 100 to 5000 microns.

The active region is characterized in that the entire remaining portion of the active isolation region except for the width of 20 ~ 500 으로부터 from the interface.

Forming a spacer on sidewalls of the device isolation film portion protruding above the substrate may include forming a spacer film on the entire surface of the substrate from which the hard mask is removed; And etching back the spacer layer.

The spacer film is formed by any one selected from the group consisting of an ALD method, an O ₃ -TEOS method, and an LP-CVD method.

The spacer is characterized in that it is formed to a thickness of 20 ~ 500Å.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. According to the present invention, an isolation layer defining an active region of a semiconductor substrate is formed, the active region is entirely recessed to have a “U” shape, and then the recess is formed. A gate is formed on the active region.

In this way, the present invention can increase the effective width of the gate channel without etching the device isolation film, thereby effectively improving the operating characteristics of the semiconductor device. In addition, the present invention does not need to etch the device isolation film in order to increase the effective width of the gate channel, it is easy to form the device isolation film can be improved manufacturing yield.

In detail, FIG. 2 is a plan view of a general semiconductor device, and FIG. 3 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention, which corresponds to lines A-A 'and B-B' of FIG. Same as In FIG. 2, reference numeral 11 denotes an active region, 12 an isolation region, and 13 a gate line.

Referring to FIG. 3, a semiconductor device of the present invention includes a semiconductor substrate 41 having an isolation region and an active region recessed to have a “U” shape, and an isolation layer formed on the substrate isolation region of the substrate 41. 43 and a gate 48 formed on the recessed active region of the substrate 41.

The entire active area is recessed from the interface of the device isolation layer 43 except for a width of about 20 to 500 mW, and the recessed active area has a depth of about 100 to 5000 mW.

Here, the effective width of the channel of the gate 48 is increased by recessing the active region in a “U” shape, thereby improving operating characteristics of the semiconductor device. In addition, since the device isolation layer 43 does not need to be etched in order to increase the width of the channel of the gate 48, the device isolation layer 43 may be easily formed, thereby improving manufacturing yield.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 4A to 4H.

Referring to FIG. 4A, a hard mask 42 exposing the isolation region is formed on a semiconductor substrate 41 having an active region and an isolation region. In this case, the hard mask 42 is formed of a nitride film or a polysilicon film.

Referring to FIG. 4B, a mask pattern (not shown) is formed on the hard mask 42 to expose a portion of the hard mask 42 corresponding to the device isolation region of the substrate 41. Next, the portion of the hard mask 42 exposed by the mask pattern is etched, the mask pattern is removed, and the device isolation region of the substrate 41 is etched using the etched hard mask 42 as an etch mask. To form the trench T.

Referring to FIG. 4C, a sidewall oxide film (not shown) is formed on the trench T surface, and then a linear nitride film (not shown) and a linear oxide film (not shown) are formed on the entire surface of the substrate 41 on which the sidewall oxide film is formed. Form in turn. Subsequently, an isolation layer 43 is formed on the linear oxide layer to completely fill the trench T including the hard mask 42.

In this case, the device isolation layer 43 may be a high density plasma (HDP) method, a spin-on glass (SOG) method, an atomic layer deposition (ALD) method, a tetra ethyl ortho silicate (O ₃₎ -TEOS, or hydrogen peroxide- It is formed through a silane method.

Here, the present invention can improve the manufacturing yield of the semiconductor device because it is possible to form a combination of various methods in order to improve the buried characteristics, without having to form the device isolation film 43 as a single film.

Referring to FIG. 4D, the hard mask is removed such that the device isolation layer 43 protrudes over the semiconductor substrate 41.

Referring to FIG. 4E, after depositing a spacer film (not shown) on the entire surface of the substrate 41 from which the hard mask is removed, a portion of the device isolation layer 43 protruded over the substrate 41 by etching back the spacer film. Spacers 44 are formed on the sidewalls of the spacers.

Here, the spacer layer is formed to a thickness of about 20 ~ 500Å according to any one of ALD method, O ₃ -TEOS method and Low Pressure-Chemical Vapor Deposition (LP-CVD) method, the etch back is dry etching Carried out in the process.

Referring to FIG. 4F, the active region of the substrate 41 is recessed by a depth of about 100 to 5000 microns. In this case, the recess uses the device isolation film 43 including the spacer 44 as an etching mask, so that the thickness of the spacer 44 is about 20 to 500 으로부터 from the interface of the device isolation film 43. The entire active area except for the width is recessed.

Here, since the channel of the gate to be formed on the recessed substrate 41 active region through the recess has a “U” shape, the effective width of the channel is increased to effectively improve the operating characteristics of the semiconductor device. Can be. In addition, since the device isolation layer 43 does not need to be recessed in order to increase the effective width of the gate channel, the weak portion of the device isolation layer 43 is not exposed, and therefore, due to the exposure of the device isolation layer 43. Problems can be prevented.

Referring to FIG. 4G, portions of the device isolation layer 43 protruding from the spacer and the substrate 41 are removed.

Referring to FIG. 4H, after the gate insulating layer 45 formed of an oxide film is formed on the recessed active region, the gate conductive layer 46 and the gate hard mask layer 47 are formed on the gate insulating layer 45. Form in turn. In this case, the gate conductive film 46 is usually formed of a laminated film of a polysilicon film and a metal film, and the gate hard mask film 47 is usually formed of a nitride film.

Next, the gate hard mask film 47, the gate conductive film 46, and the gate insulating film 45 are sequentially etched to form a gate 48.

Thereafter, although not shown, a series of subsequent known processes are sequentially performed to complete the semiconductor device.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention can effectively improve the operation characteristics of the semiconductor device by increasing the effective width of the gate channel formed on the active region by making the active region of the semiconductor substrate.

In addition, the present invention can improve the manufacturing yield of the semiconductor device by increasing the width of the gate channel without etching the device isolation film of the substrate.

Claims (11)

A semiconductor substrate having an isolation region and a recessed active region; An isolation layer formed in the isolation region of the semiconductor substrate; And A gate formed in the recessed substrate active region; The active region is a semiconductor device, characterized in that the entire remaining portion except the portion in contact with the device isolation film. The method of claim 1, And wherein said recessed active region has a "U" shape. The method of claim 1, And the active region is recessed by a depth of 100 to 5000 microns. The method of claim 1, The active region is a semiconductor device, characterized in that the entire remaining portion except the width of 20 ~ 500Å from the interface of the device isolation film. Forming a hard mask on the semiconductor substrate having an active region and an isolation region to expose the isolation region; Etching the substrate device isolation region exposed by the hard mask to form a trench; Forming an isolation layer in the trench; Removing the hard mask to protrude the device isolation layer over the substrate; Forming a spacer on a sidewall of a portion of the device isolation layer protruding from the substrate; Recessing the substrate active region using the device isolation layer including the spacer as an etch mask; Removing a portion of the device isolation layer protruding from the spacer and the substrate; And Forming a gate on the recessed active region; Method of manufacturing a semiconductor device comprising a. The method of claim 5, And the active region is recessed to have a "U" shape. The method of claim 5, And said active region is recessed by a depth of 100 to 5000 microns. The method of claim 5, The active region is a manufacturing method of a semiconductor device, characterized in that the entire remaining portion except the width of 20 ~ 500Å from the interface of the device isolation film. The method of claim 5, Forming a spacer on the side wall of the device isolation film portion protruding above the substrate, Forming a spacer layer on an entire surface of the substrate from which the hard mask is removed; And Etching back the spacer layer; Method of manufacturing a semiconductor device comprising a. The method of claim 9, The spacer film is formed according to any one selected from the group consisting of ALD method, O ₃ -TEOS method and LP-CVD method. The method of claim 5, The spacer is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 20 to 500Å.

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