KR101024754B1 - Semiconductor device and method for forming the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same, and to improve a process length for forming a recess gate by forming a double bulb type recess gate region so as to secure a channel length suitable for an ultra-high density semiconductor device. It is possible to increase the channel length of the gate efficiently.

Description

Semiconductor device and method for forming the same {SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME}

1A to 1F are cross-sectional views showing a method of forming a semiconductor device according to the prior art.

2A to 2I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a technique for increasing a channel length of a recess gate formed by a subsequent process by forming a recess gate region in a double structure in an ultra-high density semiconductor device. .

As the semiconductor devices are highly integrated, the line width of the gate is narrowed, and the reduction of the channel length causes the phenomenon that the electrical characteristics of the semiconductor device are degraded.

Recently, recess gates have been used to overcome this problem.

The recess gate is a technique capable of increasing the gate channel length by etching the semiconductor substrate in the gate predetermined region by a predetermined depth to increase the contact area between the active region and the gate.

However, the general gate structure has a problem in that leakage current is generated in the recess gate region due to misalignment between the recess gate region and the gate. Thus, a recess gate forming method for forming the recess gate region in the shape of a bulb has been developed.

The bulb type recess gate forming process is formed in the following manner.

First, an active region of a semiconductor substrate is defined, and an impurity ion implantation process is performed in an active region to improve electrical characteristics of the semiconductor device.

Next, the gate predetermined region of the active region is partially etched to form a first recess gate region, and a thermal oxide film is formed on sidewalls of the first recess gate region.

Next, using the thermal oxide film as an etching barrier, the lower semiconductor substrate of the first recess gate region isotropically etched to a predetermined depth to form a second recess gate region. In this way, the neck-shaped first recess gate and the second recess gate serving as the body portion are combined to form a bulb-type recess gate region which becomes one recess gate region.

1A to 1F are cross-sectional views illustrating a method of forming a recess gate of a semiconductor device according to the related art.

Referring to FIG. 1A, an isolation layer 110 defining an active region 120 is formed on a semiconductor substrate 100. In this case, the device isolation layer 110 may be formed using a shallow trench isolation (STI) process. Next, a channel ion implantation process is performed in the active region 120.

Next, the oxide layer 130 and the hard mask layer 140 are sequentially formed on the semiconductor substrate 100, and the anti-reflection film 145 is formed on the hard mask layer 140. Next, a photoresist pattern 150 is formed on the antireflection film 145 to define the recess gate predetermined region.

Referring to FIG. 1B, the anti-reflection film 145, the hard mask layer 140, the oxide layer 130, and the semiconductor substrate 100 may be sequentially etched using the photoresist pattern 150 as a mask to form a first recess gate region ( 160). At this time, the first recess gate region 160 is preferably formed to a depth of 400 ~ 5000 kHz. Next, the photoresist pattern 150, the antireflection film 145, and the hard mask layer 140 are removed.

Referring to FIG. 1C, a barrier film is formed on the entire surface of the semiconductor substrate 100 including the first recess gate region 160. At this time, the barrier film is deposited by ALD method at a temperature of 300 ~ 400 ℃ using any one selected from the Al2O3 film, HfO2 film and their composite structure. Next, the barrier layer under the oxide layer 130 and the first recess gate region 160 is removed using the entire surface etching process to form the sidewall barrier layer 170. At this time, the side wall barrier film is preferably formed to a thickness of 30 ~ 300Å. Here, by forming the sidewall barrier layer 170 at a low temperature (300 ~ 400 ℃), it is possible to solve the problem that the channel implant ions are diffused into the active region 120 to reduce the electrical characteristics of the semiconductor device, ALD method By using it, the step coverage of the side wall barrier film 170 can be improved.

Referring to FIG. 1D, a spherical second recess gate region isotropically etched by etching the bottom of the exposed semiconductor substrate 100 under the first recess gate region 160, that is, the first recess gate region 160. Form 180. At this time, the second recess gate region 180 is preferably etched to a depth of 400 ~ 5000 kPa.

Referring to FIG. 1E, a bulb-type rib including the first recess gate region 160 and the second recess gate region 180 may be removed by removing the oxide layer 130 on the semiconductor substrate 100. The recess gate region 190 is formed. Here, the first recess gate region 160 becomes a neck portion of the bulb-type recess gate, and the second recess gate region 180 becomes a body portion of the bulb-type recess gate. The bulb-type recess gate region 190 is formed in a shape in which a cross-sectional shape thereof continues in a line shape along the gate direction.

Referring to FIG. 1F, a gate oxide layer 195 is formed on a surface of the active region 120 including the bulb type recess gate region 190.

Next, a gate polysilicon layer filling the bulb type recess gate region 190 is formed, and a gate is formed by forming a metal layer and a gate hard mask layer pattern on the gate polysilicon layer.

As described above, the semiconductor device according to the related art and the method of forming the same have a problem of lowering the electrical characteristics of the semiconductor device by reducing the channel length as the semiconductor device is highly integrated.

The present invention provides a semiconductor device and a method of forming the double bulb type recess to form a bulb type recess gate having an increased channel length, thereby improving process margins and efficiently increasing the channel length of the gate. To provide that purpose.

The semiconductor device according to the present invention,

An isolation layer defining an active region on the semiconductor substrate;

A first recess gate region formed in the semiconductor substrate of the active region;

A second recess gate region formed at a bottom of the first recess gate region;

Forming a third recess gate region on a sidewall of the first recess gate region to include a double bulb type recess gate region including first, second and third recess gate regions;

Including a gate structure on said double bulb type recess gate region,

The gate structure is formed in a stacked structure of a gate insulating film, a gate conductive layer and a hard mask layer.

In addition, the method of forming a semiconductor device according to the present invention,

Forming a device isolation film defining an active region on the semiconductor substrate;

Etching the semiconductor substrate of the active region to form a first recess gate region;

Forming a bulb type recess gate region by etching a bottom of the first recess gate region to form a second recess gate region;

Forming a third recess gate region on a sidewall of the first recess gate region;

The first recess gate region forming process may include forming a stacked structure of an oxide layer, a hard mask layer, and an antireflection film on a semiconductor substrate, and patterning the stacked structure by a photolithography process using a recess gate mask; And etching the semiconductor substrate using the stacked structure as a mask.

The forming of the second recess gate region may include forming a sidewall barrier film on the sidewall of the first recess gate, forming an bulb by isotropically etching the bottom of the first recess gate, and removing the sidewall barrier film. Including a process,

The third recess gate region forming process may include forming an etch barrier layer filling the first and second recess gate regions, forming a hard mask layer over the entire surface, and using a recess gate mask. Patterning the hard mask layer by a photolithography process, etching the etch barrier layer using the hard mask layer as a mask, but leaving the bottom of the first recess gate region, the hard mask layer and Forming a third recess gate region by etching the semiconductor substrate on the sidewalls of the first recess gate region using an etch selectivity difference from the etch barrier layer;

The etch barrier layer includes a photosensitive film or an oxide film,

The hard mask layer includes a nitride film,

The etching process of the etch barrier layer is to leave 100-300 Å from the bottom of the first recess gate region,

The third recess gate region forming process may be performed by an isotropic etching process.

Forming a gate insulating film on a surface of the semiconductor substrate including the first, second and third recess gate regions, and forming a gate structure on the first, second and third recess gate regions. It is done.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, an isolation layer 310 defining an active region 320 is formed on a semiconductor substrate 300. In this case, the device isolation layer 310 is preferably formed using a shallow trench isolation (STI) process. Next, a channel ion implantation process is performed in the active region 320.

Next, the oxide layer 330 and the first hard mask layer 340 are sequentially formed on the semiconductor substrate 300, and the antireflection film 345 is formed on the first hard mask layer 340. Next, a first photoresist pattern 350 is formed on the anti-reflection film 345 to define the recess gate predetermined region.

Referring to FIG. 2B, the anti-reflection film 345, the first hard mask layer 340, the oxide layer 330, and the semiconductor substrate 300 may be sequentially etched using the first photoresist pattern 350 as a mask. The recess gate region 360 is formed. In this case, the first recess gate region 360 may be formed to have a depth of 400 to 5000 kHz. Next, the first photoresist film pattern 350, the antireflection film 345, and the first hard mask layer 340 are removed.

Referring to FIG. 2C, a barrier film is formed on the entire surface of the semiconductor substrate 300 including the first recess gate region 360. At this time, the barrier film is deposited by ALD method at a temperature of 300 ~ 400 ℃ using any one selected from the Al2O3 film, HfO2 film and their composite structure. Next, the barrier layer under the oxide layer 330 and the first recess gate region 360 is removed using the entire surface etching process to form the sidewall barrier layer 370. At this time, the side wall barrier film is preferably formed to a thickness of 30 ~ 300Å. Here, by forming the sidewall barrier film 370 at a low temperature (300 ~ 400 ℃), it is possible to solve the problem that the channel implant ions are diffused into the active region 320 to reduce the electrical characteristics of the semiconductor device, ALD method By using it, the step coverage of the sidewall barrier film 370 can be improved.

Referring to FIG. 2D, the bottom of the exposed semiconductor substrate 300 under the first recess gate region 360, that is, the bottom of the first recess gate region 360 isotropically etched to form a spherical second recess gate region ( 380). At this time, the second recess gate region 380 is preferably etched to a depth of 400 ~ 5000 kPa.

Referring to FIG. 2E, a bulb type including the first recess gate region 360 and the second recess gate region 380 may be removed by removing the oxide layer 330 on the semiconductor substrate 300. The recess gate region 390 is formed. At this time, the sidewall barrier film 370 is removed during the oxide film layer 330 removal process.

Here, the first recess gate region 360 becomes a neck portion of the bulb-type recess gate, and the second recess gate region 380 becomes a body portion of the bulb-type recess gate. The bulb-type recess gate region 390 is formed in a shape in which a cross-sectional shape of the bulb-shaped recess gate region 390 is formed in a line shape along the gate direction.

Referring to FIG. 2F, an etch barrier layer 400 filling the bulb type recess gate region 390 is formed. In this case, the etching barrier layer 400 is formed of a photosensitive film or an oxide film.

The planarized second hard mask layer 410 is formed on the entire surface. In this case, the second hard mask layer 410 is formed of a nitride film.

The second photoresist layer pattern 420 is formed on the second hard mask layer 410.

Referring to FIG. 2G, the etch barrier layer 400 is etched using the second photoresist pattern 420 as a mask. In this case, the etching process of the etching barrier layer 400 may be performed by removing 100-300 의 of the first recess gate region 360 to the upper portion of the second recess gate region 380, that is, the neck of the bulb-type recess gate 39. It is carried out anisotropically to leave the etch barrier layer 400 by the thickness.

Referring to FIG. 2H, the third recess gate region 430 isotropically etches the active region 320 of the semiconductor substrate using a difference in etching selectivity from the second hard mask layer 410 and the etch barrier layer 400. To form.

Referring to FIG. 2I, the second hard mask layer 41 and the etch barrier layer 400 are removed to form the double bulb type recess gate regions 360, 380, and 430.

A gate insulating layer 440 is formed on the surfaces of the double bulb type recess gate regions 360, 380, and 430.

In a subsequent process, a double bulb type recess gate having a channel length is formed by forming a gate structure on a semiconductor substrate including the double bulb type recess gate regions 360, 380, and 430 and implanting impurities.

As described above, the semiconductor device and the method for forming the same according to the present invention,

The channel length of the ultra-high density semiconductor device transistor is increased to prevent short channel effects and refresh characteristics of the semiconductor device, thereby improving the electrical characteristics of the semiconductor device.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (12)

delete delete delete Forming a device isolation film defining an active region on the semiconductor substrate; Etching the semiconductor substrate of the active region to form a first recess gate region; Forming a bulb type recess gate region by etching a bottom of the first recess gate region to form a second recess gate region; Forming a third recess gate region on a sidewall of the first recess gate region. The method of claim 4, wherein The first recess gate region forming process Forming a stacked structure of an oxide film layer, a hard mask layer and an antireflection film on the semiconductor substrate; Patterning the stacked structure by a photolithography process using a recess gate mask; And etching the semiconductor substrate using the stacked structure as a mask. The method of claim 4, wherein The second recess gate region forming process Forming a sidewall barrier film on the sidewalls of the first recess gates; Isotropically etching the bottom of the first recess gate to form a bulb; And removing the sidewall barrier film. The method of claim 4, wherein The third recess gate region forming process Forming an etch barrier layer filling the first and second recess gate regions; Forming a hard mask layer over the entire surface, Patterning the hard mask layer by a photolithography process using a recess gate mask; Etching the etch barrier layer using the hard mask layer as a mask, but leaving the bottom of the first recess gate region; And forming the third recess gate region by etching the semiconductor substrate on the sidewalls of the first recess gate region using an etch selectivity difference between the hard mask layer and the etch barrier layer. Formation method of the device. The method of claim 7, wherein The etching barrier layer is a method of forming a semiconductor device, characterized in that it comprises a photosensitive film or an oxide film. The method of claim 7, wherein And the hard mask layer comprises a nitride film. The method of claim 7, wherein And etching the etching barrier layer by 100-300 kV from the bottom of the first recess gate region. The method of claim 7, wherein And forming the third recess gate region by an isotropic etching process. The method of claim 4, wherein Forming a gate insulating film on a surface of the semiconductor substrate including the first, second and third recess gate regions; Forming a gate structure on the first, second and third recessed gate regions.

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