KR20070112234A - 플라즈마 산화 및 산화된 재료의 제거 - Google Patents

플라즈마 산화 및 산화된 재료의 제거 Download PDF

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Publication number
KR20070112234A
KR20070112234A KR1020077022513A KR20077022513A KR20070112234A KR 20070112234 A KR20070112234 A KR 20070112234A KR 1020077022513 A KR1020077022513 A KR 1020077022513A KR 20077022513 A KR20077022513 A KR 20077022513A KR 20070112234 A KR20070112234 A KR 20070112234A
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KR
South Korea
Prior art keywords
conductive layer
etching
layer
converting
copper
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Ceased
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KR1020077022513A
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English (en)
Korean (ko)
Inventor
윤상 김
앤드류 3세 베일리
형석 알렉산더 윤
아서 엠 하워드
Original Assignee
램 리써치 코포레이션
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Publication of KR20070112234A publication Critical patent/KR20070112234A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/269—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6314—Formation by oxidation, e.g. oxidation of the substrate of a metallic layer

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Solid-Phase Diffusion Into Metallic Material Surfaces (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
KR1020077022513A 2005-03-09 2006-02-27 플라즈마 산화 및 산화된 재료의 제거 Ceased KR20070112234A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/076,725 US7540935B2 (en) 2003-03-14 2005-03-09 Plasma oxidation and removal of oxidized material
US11/076,725 2005-03-09

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020137003686A Division KR101376830B1 (ko) 2005-03-09 2006-02-27 플라즈마 산화 및 산화된 재료의 제거

Publications (1)

Publication Number Publication Date
KR20070112234A true KR20070112234A (ko) 2007-11-22

Family

ID=36992195

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020077022513A Ceased KR20070112234A (ko) 2005-03-09 2006-02-27 플라즈마 산화 및 산화된 재료의 제거
KR1020137003686A Expired - Fee Related KR101376830B1 (ko) 2005-03-09 2006-02-27 플라즈마 산화 및 산화된 재료의 제거

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020137003686A Expired - Fee Related KR101376830B1 (ko) 2005-03-09 2006-02-27 플라즈마 산화 및 산화된 재료의 제거

Country Status (6)

Country Link
US (1) US7540935B2 (enExample)
JP (1) JP2008536296A (enExample)
KR (2) KR20070112234A (enExample)
CN (1) CN101164121B (enExample)
TW (1) TWI310587B (enExample)
WO (1) WO2006098888A2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100729933B1 (ko) * 2005-12-19 2007-06-18 동부일렉트로닉스 주식회사 구리 시드층의 증착 온도 측정 방법 및 이를 이용한 구리층형성 방법
WO2008048259A2 (en) * 2006-10-16 2008-04-24 Materials And Technologies Corporation Wet processing using a fluid meniscus, apparatus and method
JP5184644B2 (ja) * 2007-11-21 2013-04-17 ラム リサーチ コーポレーション 湿式エッジ洗浄を強化するためのベベルプラズマ処理
US8414790B2 (en) * 2008-11-13 2013-04-09 Lam Research Corporation Bevel plasma treatment to enhance wet edge clean
US20120088370A1 (en) * 2010-10-06 2012-04-12 Lam Research Corporation Substrate Processing System with Multiple Processing Devices Deployed in Shared Ambient Environment and Associated Methods
CN105225976A (zh) * 2014-06-25 2016-01-06 中芯国际集成电路制造(上海)有限公司 焊盘的制作方法及半导体器件
CN107980170B (zh) * 2015-06-17 2022-02-18 英特尔公司 用于器件制造的通过对氧化物层的原子层去除的过渡金属干法蚀刻
CN112382608A (zh) * 2020-11-04 2021-02-19 上海华力集成电路制造有限公司 铜互连线的制造方法
US11557487B2 (en) * 2021-06-04 2023-01-17 Tokyo Electron Limited Etching metal during processing of a semiconductor structure
WO2025004295A1 (ja) * 2023-06-29 2025-01-02 株式会社Kokusai Electric 処理方法、処理装置、半導体装置の製造方法及びプログラム

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468284A (en) * 1983-07-06 1984-08-28 Psi Star, Inc. Process for etching an aluminum-copper alloy
US4919750A (en) * 1987-09-14 1990-04-24 International Business Machines Corporation Etching metal films with complexing chloride plasma
US5098516A (en) * 1990-12-31 1992-03-24 Air Products And Chemicals, Inc. Processes for the chemical vapor deposition of copper and etching of copper
US5561082A (en) * 1992-07-31 1996-10-01 Kabushiki Kaisha Toshiba Method for forming an electrode and/or wiring layer by reducing copper oxide or silver oxide
JP2885616B2 (ja) * 1992-07-31 1999-04-26 株式会社東芝 半導体装置およびその製造方法
US5431774A (en) * 1993-11-30 1995-07-11 Texas Instruments Incorporated Copper etching
US6090701A (en) * 1994-06-21 2000-07-18 Kabushiki Kaisha Toshiba Method for production of semiconductor device
US5736002A (en) * 1994-08-22 1998-04-07 Sharp Microelectronics Technology, Inc. Methods and equipment for anisotropic, patterned conversion of copper into selectively removable compounds and for removal of same
JP3417751B2 (ja) * 1995-02-13 2003-06-16 株式会社東芝 半導体装置の製造方法
US6171661B1 (en) * 1998-02-25 2001-01-09 Applied Materials, Inc. Deposition of copper with increased adhesion
JP4307592B2 (ja) * 1998-07-07 2009-08-05 Ｏｋｉセミコンダクタ株式会社 半導体素子における配線形成方法
JP3892621B2 (ja) * 1999-04-19 2007-03-14 株式会社神戸製鋼所 配線膜の形成方法
US6355979B2 (en) * 1999-05-25 2002-03-12 Stmicroelectronics, Inc. Hard mask for copper plasma etch
US6344105B1 (en) * 1999-06-30 2002-02-05 Lam Research Corporation Techniques for improving etch rate uniformity
US20030155079A1 (en) * 1999-11-15 2003-08-21 Andrew D. Bailey Plasma processing system with dynamic gas distribution control
US20020072228A1 (en) * 1999-12-15 2002-06-13 Texas A&M University System Semiconductor conductive pattern formation method
US6403491B1 (en) * 2000-11-01 2002-06-11 Applied Materials, Inc. Etch method using a dielectric etch chamber with expanded process window
US6613667B1 (en) * 2001-05-02 2003-09-02 The Texas A&M University System Forming an interconnect of a semiconductor device
TW550648B (en) * 2001-07-02 2003-09-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
US6518183B1 (en) * 2001-09-06 2003-02-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hillock inhibiting method for forming a passivated copper containing conductor layer
JP4024508B2 (ja) * 2001-10-09 2007-12-19 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6806948B2 (en) * 2002-03-29 2004-10-19 Lam Research Corporation System and method of broad band optical end point detection for film change indication
US6794245B2 (en) * 2002-07-18 2004-09-21 Micron Technology, Inc. Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules
JP2004193488A (ja) * 2002-12-13 2004-07-08 Tosoh Corp バリア金属用研磨液及び研磨方法
KR100483290B1 (ko) 2002-12-14 2005-04-15 동부아남반도체 주식회사 반도체 소자의 제조 방법
KR100482180B1 (ko) * 2002-12-16 2005-04-14 동부아남반도체 주식회사 반도체 소자 제조방법
US6821899B2 (en) * 2003-03-14 2004-11-23 Lam Research Corporation System, method and apparatus for improved local dual-damascene planarization
US6939796B2 (en) * 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
US7217649B2 (en) * 2003-03-14 2007-05-15 Lam Research Corporation System and method for stress free conductor removal
US7232766B2 (en) * 2003-03-14 2007-06-19 Lam Research Corporation System and method for surface reduction, passivation, corrosion prevention and activation of copper surface
US7129167B1 (en) * 2003-03-14 2006-10-31 Lam Research Corporation Methods and systems for a stress-free cleaning a surface of a substrate
US20050287698A1 (en) * 2004-06-28 2005-12-29 Zhiyong Li Use of chalcogen plasma to form chalcogenide switching materials for nanoscale electronic devices

Also Published As

Publication number Publication date
US20060128152A1 (en) 2006-06-15
KR20130036066A (ko) 2013-04-09
TWI310587B (en) 2009-06-01
CN101164121B (zh) 2011-01-26
WO2006098888A3 (en) 2007-12-21
TW200644113A (en) 2006-12-16
US7540935B2 (en) 2009-06-02
KR101376830B1 (ko) 2014-03-20
WO2006098888A2 (en) 2006-09-21
JP2008536296A (ja) 2008-09-04
CN101164121A (zh) 2008-04-16

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