US20020072228A1 - Semiconductor conductive pattern formation method - Google Patents
Semiconductor conductive pattern formation method Download PDFInfo
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- US20020072228A1 US20020072228A1 US09/736,043 US73604300A US2002072228A1 US 20020072228 A1 US20020072228 A1 US 20020072228A1 US 73604300 A US73604300 A US 73604300A US 2002072228 A1 US2002072228 A1 US 2002072228A1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
Definitions
- Ultra-large scale integrated circuits ULSI
- microelectronics microelectronics, optoelectronics, and other electronic devices and products generally require fine interconnection or conductive patterns to accommodate functionality and density constraints.
- fine interconnection patterns are increasingly difficult to control.
- one material used to form interconnection patterns is copper. Copper may be used for interconnection patterns rather than aluminum materials because copper generally has a higher conductivity, substantially no hillocks formation, and substantially no electron migration. Actually, copper interconnection may be required for the sub 180 nanometer ULSI.
- one problem associated with copper trace or line formation is that there is a lack of an effective dry etching process to prepare well-controlled copper fine lines.
- copper lines are generally prepared with a chemical mechanical polishing (CMP) process, such as Damascene or dual-Damascene.
- CMP chemical mechanical polishing
- Plasma etching of copper has also been used to form interconnection patterns.
- the most common etching chemistry is derived from an aluminum etch, i.e., using halogen-containing gases as the feed streams.
- the reaction products of the plasma etch i.e., copper halides
- the reaction products often accumulate on the surface of the product or device instead of being removed.
- a high-energy source such as a high-density plasma, a laser, an infrared (IR) or ultraviolet (UV) beam, or a high substrate temperature, needs to be added to a reactive ion etching (RIE) chamber.
- RIE reactive ion etching
- Such methods either may have poor etch uniformity for large area substrates or require a complicated reactor design and process control scheme.
- the high temperature approach does not have the above described problems, but still requires high ion bombardment energy to achieve a high etch rate. Additionally, the selectivity of copper or other interconnection materials to another film will generally be lowered by the high ion bombardment energy.
- the etch rate is negative, i.e., the etched surface is higher than the unetched surface due to the accumulation of the reaction product.
- the present invention provides a method for conductive pattern formation that addresses disadvantages and problems associated with previous conductive pattern formation methods.
- a method for forming a conductive pattern for semiconductor device includes patterning a mask layer outwardly from a conductive layer of the semiconductor device.
- the patterning defines portions of the conductive layer where vias or open areas through the conductive layer are desired.
- the method also includes exposing the semiconductor device to a plasma.
- the plasma converts the unmasked portions of the conductive layer into a compound.
- the method further includes exposing the semiconductor device to a treatment process to selectively remove the compound.
- a method for forming a conductive pattern for an electronic device includes forming a conductive layer outwardly from a substrate of the electronic device and patterning a mask layer outwardly from the conductive layer.
- the patterning defines portions of the conductive layer where vias or open areas through the conductive layer are desired.
- the method also includes exposing the electronic device to a plasma.
- the plasma converts the unmasked portions of the conductive layer into a compound.
- the method further includes exposing the semiconductor device to a treatment process to selectively remove the compound.
- the method also includes removing the mask layer from the masked portions of the conductive layer.
- the present invention provides several technical advantages.
- the present invention provides conductive pattern formation using a generally high etch rate.
- Another advantage of the present invention is that the prevention may be applied to a large-area substrate.
- a further advantage of the present invention is that the method is compatible with other semiconductor processes and device requirements.
- FIG. 1 illustrates a schematic cross-sectional diagram of a semiconductor device having a mask layer formed over a conductive layer that is deposited on a substrate in accordance with an embodiment of the present invention
- FIG. 2 illustrates a schematic cross-sectional diagram of the semiconductor device of FIG. 1 after plasma exposure in accordance with an embodiment of the present invention
- FIG. 3 illustrates a schematic cross-sectional diagram of the semiconductor device of FIGS. 1 and 2 after plasma-converted compound layer material removal in accordance with an embodiment of the present invention
- FIG. 4 illustrates a schematic cross-sectional diagram of the semiconductor device of FIGS. 1 - 3 after the mask layer and the compound removal in accordance with an embodiment of the present invention
- FIG. 5 is a flow diagram illustrating conductive pattern formation in accordance with an embodiment of the present invention.
- FIGS. 1 - 4 illustrate the formation of an electronic device 10 in accordance with an embodiment of the present invention.
- Device 10 may include a semiconductor device, microelectronic device, optoelectronic device, magnetic device, or any other device requiring a conductive interconnection pattern.
- a conductive layer 12 and a barrier layer 14 are formed upwardly from a substrate 16 .
- Substrate 16 may include glass, silicon, plastic, metal, or any other suitable substrate material.
- Barrier layer 14 may include titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, chromium, or any other suitable material to enhance the adhesion of the conductive layer 12 and/or to substantially prevent diffusion of the material comprising the conductive layer 12 into the substrate 16 .
- layer 14 may comprise either conductive or nonconductive materials corresponding to a particular application.
- conductive layer 12 may also be formed upwardly from substrate 16 without barrier layer 14 .
- Conductive layer 12 may include copper, nickel, and iron, alloys or compounds of copper, nickel and iron, or other suitable conductive materials for providing conductive interconnections or magnetic patterns on the device 10 .
- one or more mask layers 18 are formed upwardly from conductive layer 12 to define open areas or vias 20 through the conductive layer 12 at desired locations.
- one or more of the mask layers 18 are formed over the conductive layer 12 to define a desired conductive or magnetic pattern for the device 10 , thereby masking a portion of the conductive layer 12 that will remain on the device 10 . Unmasked portions of the conductive layer 12 corresponding to the vias 20 are removed, as will be discussed in greater detail below, thereby forming open areas or vias 20 through the conductive layer 12 .
- mask layers 18 include a hard masking layer 22 formed upwardly from the conductive layer 12 , and a photoresist layer 24 formed upwardly from the masking layer 22 .
- the function of layer 22 is to provide a protection, a passivation, or a diffusion barrier to the conductive layer 12 .
- Masking layer 22 may include silicon oxide, silicon nitride, metals, metal oxides, or other suitable materials to provide additional etching layers of device 10 to accommodate a variety of pattern formations and/or etching techniques.
- photoresist layer 24 may be formed upwardly from the conductive layer 12 without the masking layer 22 .
- the plasma reactor may have a conventional simple parallel-plate design or have a high density plasma (such as inductive-coupled plasma ICP, electron cyclotron resonance ECR, hellicon plasma, or other suitable designs).
- the plasma exposure may be performed using conventional plasma etching or deposition techniques, such as, but not limited to, 1 mTorr to 10 Torr pressure.
- An electrode, located generally where device 10 is loaded into the reactor, may be heated with an electric heater, a hot oil coil, an infrared source, or other suitable methods.
- a wide range of substrate 10 temperatures may be used during the plasma exposure, such as, but not limited to, from lower than room temperature to approximately 500 degrees Celsius.
- the plasma includes one of a variety of gases comprising an element selected from the halogen group of elements, such as, but not limited to, chlorine, bromine, fluorine, iodine, or their mixtures, as the reactive component in the feed stream of the plasma exposure process.
- the plasma may include a chlorine-containing gas such as HCl, Cl 2 , organic or inorganic chloride, HBr, Br 2 , HI, I 2 or their mixtures.
- gases such as, but not limited to, oxygen, inert gases, and nitrogen may be mixed with the reactive component to enhance the plasma-conductive layer 12 reaction.
- FIG. 2 a cross-sectional view of device 10 is illustrated after the plasma exposure. As illustrated in FIG. 2, unmasked portions of the conductive layer 12 are converted into a compound layer 30 as a result of the chemical reaction between the plasma and the exposed portions of the conductive layer 12 .
- the conductive layer 12 comprises copper and the plasma comprises an HCl plasma
- a copper chloride layer may be formed as compound layer 30 .
- the compound layer 30 may be thicker than the original conductive layer 12 .
- the compound layer 30 may grow isotropically when it is higher than the mask layers 18 .
- the plasma exposure process may also be controlled to for form an interface between the masked portion of the conductive layer 12 and the compound layer 30 that is substantially perpendicular to the surface of the substrate 16 .
- the plasma exposure process may also be controlled to form a sloped or angled interface at a variety of angular orientations between the masked portion of the layer 12 and the compound layer 30 .
- Such plasma exposure characteristics as the gas type, pressure, power, time, and the substrate temperature may be varied to form a desired interface between the masked portion of the conductive layer 12 and the compound layer 30 .
- the device 10 is illustrated after removal of the compound layer 30 .
- the device 10 may be exposed to a physical or chemical environment or process to remove the compound layer 30 .
- a hydrogen chloride (HCl) solution may be used to remove the compound layer 30 with substantially little affect to the remaining conductive layer 12 and/or mask layers 18 .
- the copper chloride may be removed by heating the device 10 to a high temperature, such as between 500-600 degrees Celsius, under vacuum or in an inert atmosphere because the copper chloride material has generally a much lower higher vapor pressure than copper material.
- a high temperature such as between 500-600 degrees Celsius
- Another alternative method includes exposing the device 10 to an energized electron or ion beam that will evaporate the compound layer 30 .
- a laser, IR, or UV beam could also be used to remove the compound layer 30 .
- other suitable methods or techniques may also be used to remove the compound layer 30 .
- the device 10 is illustrated after removal of portions of layer 14 corresponding to the vias 20 and the mask layers 18 , thereby providing the desired conductive or magnetic pattern.
- Layer 14 may be selectively removed from the via 20 locations using conventional methods, including, but not limited to, etching processes. However, it should be understood that layer 14 may remain on the device 10 , for example, if layer 14 comprises an insulating material.
- the mask layers 18 may be removed using conventional methods such as, but not limited to, a plasma process, a solvent dipping, or a combination of plasma processes and solvent dipping.
- the photoresist layer 24 may be removed using an acetone solution in an ultrasonic bath at approximately sixty degrees Celsius. However, other suitable methods may also be used to remove the mask layers 18 .
- the mask layers 18 may be removed either before or after the removal of the compound layer 30 , and layer 14 may be removed either after or before removal of the mask layers 18 .
- FIG. 5 is a flow diagram illustrating a method for conductive pattern formation on a device 10 in accordance with an embodiment of the present invention.
- the method begins at step 100 , where the barrier layer 14 is formed upwardly from the substrate 16 .
- the barrier layer 14 may be omitted to accommodate a particular device 10 configuration or materials selection.
- conductive layer 12 is formed upwardly from barrier layer 14 , or upwardly from the substrate 16 if the barrier layer 14 was omitted.
- the conductive layer 12 may include copper, nickel, iron, or other suitable conductive or magnetic materials.
- one or more mask layers 18 are formed upwardly over portions of the conductive layer 12 to define a desired conductive pattern.
- a mask layer 18 is configured to a desired conductive pattern for the device 10 , thereby creating vias 20 corresponding to unmasked portions of the conductive layer 12 that will be removed to form the desired conductive pattern.
- the device is exposed to a plasma in a plasma reactor.
- the plasma comprises a gas selected from the halogen group of elements such as, but not limited to, chlorine, bromine, fluorine, and iodine.
- exposure of the device 10 to the plasma converts the unmasked portions of the conductive layer 12 to a compound layer 30 .
- step 110 a determination is made whether to remove the mask layers 18 before or after removal of the compound layer 30 . If removal of the mask layers 18 is desired before removing the compound layer 30 , the method proceeds to step 112 , where mask layers 18 are removed using conventional methods. If removal of the mask layers 18 is desired after removal of the compound layer 30 , the method proceeds from step 110 to step 114 .
- the compound layer 30 is removed from the device 10 , thereby forming the open areas or vias 20 in the conductive layer 12 corresponding to the previously unmasked portions of the conductive layer 12 .
- layer 14 may be removed from the substrate 16 corresponding to the via 20 locations. As described above, layer 14 may be removed either after or before removal of the mask layers 18 .
- decisional step 116 a determination is made whether the mask layers 18 were previously removed. If the mask layers 18 were not removed before removal of the compound layer 30 , the method proceeds from step 116 to step 118 , where the mask layers 18 are removed. If the mask layers 18 were removed prior to removal of the compound layer 30 , the method terminates.
- the present invention provides a conductive pattern formation method that provides greater control and creation of fine conductive interconnection lines or traces for semiconductors and other electronic devices than prior conductive pattern formation processes. Additionally, the conductive pattern formation method of the present invention may be used with conventional semiconductor fabrication equipment and facilities, thereby substantially reducing or eliminating costly facility upgrades, retrofits, or the design and manufacturing of unconventional new tools to form fine line conductive or magnetic patterns.
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Abstract
A method for forming a conductive or magnetic pattern for a semiconductor or other electronic device includes patterning a mask layer outwardly from a conductive layer of the semiconductor device. The patterning defines portions of the conductive layer where vias through the conductive layer are desired. The method also includes exposing the semiconductor device to a plasma. The plasma converts the unmasked portions of the conductive layer into a compound. The method further includes exposing the semiconductor device to a treatment process to selectively remove the compound. The mask layer may be removed either before or after removal of the compound, thereby providing the unmasked conductive layer in the desired pattern.
Description
- Ultra-large scale integrated circuits (ULSI), microelectronics, optoelectronics, and other electronic devices and products generally require fine interconnection or conductive patterns to accommodate functionality and density constraints. However, fine interconnection patterns are increasingly difficult to control. For example, one material used to form interconnection patterns is copper. Copper may be used for interconnection patterns rather than aluminum materials because copper generally has a higher conductivity, substantially no hillocks formation, and substantially no electron migration. Actually, copper interconnection may be required for the sub 180 nanometer ULSI. However, one problem associated with copper trace or line formation is that there is a lack of an effective dry etching process to prepare well-controlled copper fine lines. For example, copper lines are generally prepared with a chemical mechanical polishing (CMP) process, such as Damascene or dual-Damascene. However, when the minimum device geometry is reduced or shrunk to less than 100 nanometers, such a process is especially difficult for use in etching and filling high aspect ratio structures.
- Plasma etching of copper has also been used to form interconnection patterns. For example, the most common etching chemistry is derived from an aluminum etch, i.e., using halogen-containing gases as the feed streams. Since the reaction products of the plasma etch, i.e., copper halides, have very low volatilities at room temperature, the reaction products often accumulate on the surface of the product or device instead of being removed. In order to facilitate the removal of these halides, a high-energy source, such as a high-density plasma, a laser, an infrared (IR) or ultraviolet (UV) beam, or a high substrate temperature, needs to be added to a reactive ion etching (RIE) chamber. Such methods either may have poor etch uniformity for large area substrates or require a complicated reactor design and process control scheme. The high temperature approach does not have the above described problems, but still requires high ion bombardment energy to achieve a high etch rate. Additionally, the selectivity of copper or other interconnection materials to another film will generally be lowered by the high ion bombardment energy. In many of the copper etching processes, for example, the etch rate is negative, i.e., the etched surface is higher than the unetched surface due to the accumulation of the reaction product.
- Accordingly, a need has arisen for an improved interconnection or conductive pattern forming method for microelectronic, optoelectronic and other electronic devices. The present invention provides a method for conductive pattern formation that addresses disadvantages and problems associated with previous conductive pattern formation methods.
- In accordance with one embodiment of the present invention, a method for forming a conductive pattern for semiconductor device includes patterning a mask layer outwardly from a conductive layer of the semiconductor device. The patterning defines portions of the conductive layer where vias or open areas through the conductive layer are desired. The method also includes exposing the semiconductor device to a plasma. The plasma converts the unmasked portions of the conductive layer into a compound. The method further includes exposing the semiconductor device to a treatment process to selectively remove the compound.
- According to another embodiment of the present invention, a method for forming a conductive pattern for an electronic device includes forming a conductive layer outwardly from a substrate of the electronic device and patterning a mask layer outwardly from the conductive layer. The patterning defines portions of the conductive layer where vias or open areas through the conductive layer are desired. The method also includes exposing the electronic device to a plasma. The plasma converts the unmasked portions of the conductive layer into a compound. The method further includes exposing the semiconductor device to a treatment process to selectively remove the compound. The method also includes removing the mask layer from the masked portions of the conductive layer.
- The present invention provides several technical advantages. For example, the present invention provides conductive pattern formation using a generally high etch rate. Another advantage of the present invention is that the prevention may be applied to a large-area substrate. A further advantage of the present invention is that the method is compatible with other semiconductor processes and device requirements.
- Other aspects and technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims.
- For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:
- FIG. 1 illustrates a schematic cross-sectional diagram of a semiconductor device having a mask layer formed over a conductive layer that is deposited on a substrate in accordance with an embodiment of the present invention;
- FIG. 2 illustrates a schematic cross-sectional diagram of the semiconductor device of FIG. 1 after plasma exposure in accordance with an embodiment of the present invention;
- FIG. 3 illustrates a schematic cross-sectional diagram of the semiconductor device of FIGS. 1 and 2 after plasma-converted compound layer material removal in accordance with an embodiment of the present invention;
- FIG. 4 illustrates a schematic cross-sectional diagram of the semiconductor device of FIGS.1-3 after the mask layer and the compound removal in accordance with an embodiment of the present invention; and
- FIG. 5 is a flow diagram illustrating conductive pattern formation in accordance with an embodiment of the present invention.
- FIGS.1-4 illustrate the formation of an
electronic device 10 in accordance with an embodiment of the present invention.Device 10 may include a semiconductor device, microelectronic device, optoelectronic device, magnetic device, or any other device requiring a conductive interconnection pattern. - Referring to FIG. 1, a
conductive layer 12 and abarrier layer 14 are formed upwardly from asubstrate 16.Substrate 16 may include glass, silicon, plastic, metal, or any other suitable substrate material.Barrier layer 14 may include titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, chromium, or any other suitable material to enhance the adhesion of theconductive layer 12 and/or to substantially prevent diffusion of the material comprising theconductive layer 12 into thesubstrate 16. Thus,layer 14 may comprise either conductive or nonconductive materials corresponding to a particular application. However, it should be understood thatconductive layer 12 may also be formed upwardly fromsubstrate 16 withoutbarrier layer 14. -
Conductive layer 12 may include copper, nickel, and iron, alloys or compounds of copper, nickel and iron, or other suitable conductive materials for providing conductive interconnections or magnetic patterns on thedevice 10. As illustrated in FIG. 1, one ormore mask layers 18 are formed upwardly fromconductive layer 12 to define open areas orvias 20 through theconductive layer 12 at desired locations. For example, one or more of themask layers 18 are formed over theconductive layer 12 to define a desired conductive or magnetic pattern for thedevice 10, thereby masking a portion of theconductive layer 12 that will remain on thedevice 10. Unmasked portions of theconductive layer 12 corresponding to thevias 20 are removed, as will be discussed in greater detail below, thereby forming open areas orvias 20 through theconductive layer 12. - In the embodiment illustrated in FIG. 1,
mask layers 18 include ahard masking layer 22 formed upwardly from theconductive layer 12, and aphotoresist layer 24 formed upwardly from themasking layer 22. The function oflayer 22 is to provide a protection, a passivation, or a diffusion barrier to theconductive layer 12.Masking layer 22 may include silicon oxide, silicon nitride, metals, metal oxides, or other suitable materials to provide additional etching layers ofdevice 10 to accommodate a variety of pattern formations and/or etching techniques. However, it should be understood thatphotoresist layer 24 may be formed upwardly from theconductive layer 12 without themasking layer 22. - Referring to FIG. 2,
device 10 is then exposed to a plasma in a plasma reactor (not explicitly shown). The plasma reactor may have a conventional simple parallel-plate design or have a high density plasma (such as inductive-coupled plasma ICP, electron cyclotron resonance ECR, hellicon plasma, or other suitable designs). The plasma exposure may be performed using conventional plasma etching or deposition techniques, such as, but not limited to, 1 mTorr to 10 Torr pressure. An electrode, located generally wheredevice 10 is loaded into the reactor, may be heated with an electric heater, a hot oil coil, an infrared source, or other suitable methods. A wide range ofsubstrate 10 temperatures may be used during the plasma exposure, such as, but not limited to, from lower than room temperature to approximately 500 degrees Celsius. - The plasma includes one of a variety of gases comprising an element selected from the halogen group of elements, such as, but not limited to, chlorine, bromine, fluorine, iodine, or their mixtures, as the reactive component in the feed stream of the plasma exposure process. For example, the plasma may include a chlorine-containing gas such as HCl, Cl2, organic or inorganic chloride, HBr, Br2, HI, I2 or their mixtures. Other gases, such as, but not limited to, oxygen, inert gases, and nitrogen may be mixed with the reactive component to enhance the plasma-
conductive layer 12 reaction. - Referring to FIG. 2, a cross-sectional view of
device 10 is illustrated after the plasma exposure. As illustrated in FIG. 2, unmasked portions of theconductive layer 12 are converted into acompound layer 30 as a result of the chemical reaction between the plasma and the exposed portions of theconductive layer 12. For example, if theconductive layer 12 comprises copper and the plasma comprises an HCl plasma, a copper chloride layer may be formed ascompound layer 30. - Depending on the reaction mechanism and process characteristics, the
compound layer 30 may be thicker than the originalconductive layer 12. For example, thecompound layer 30 may grow isotropically when it is higher than the mask layers 18. Additionally, the plasma exposure process may also be controlled to for form an interface between the masked portion of theconductive layer 12 and thecompound layer 30 that is substantially perpendicular to the surface of thesubstrate 16. The plasma exposure process may also be controlled to form a sloped or angled interface at a variety of angular orientations between the masked portion of thelayer 12 and thecompound layer 30. Such plasma exposure characteristics as the gas type, pressure, power, time, and the substrate temperature may be varied to form a desired interface between the masked portion of theconductive layer 12 and thecompound layer 30. - Referring to FIG. 3, the
device 10 is illustrated after removal of thecompound layer 30. Thedevice 10 may be exposed to a physical or chemical environment or process to remove thecompound layer 30. For example, if thecompound layer 30 comprises copper chloride resulting from the reaction of a coppermaterial conductive layer 12 with a HCl plasma as described above, a hydrogen chloride (HCl) solution may be used to remove thecompound layer 30 with substantially little affect to the remainingconductive layer 12 and/or mask layers 18. In another method, using copper chloride as thecompound layer 30 for example, the copper chloride may be removed by heating thedevice 10 to a high temperature, such as between 500-600 degrees Celsius, under vacuum or in an inert atmosphere because the copper chloride material has generally a much lower higher vapor pressure than copper material. Another alternative method includes exposing thedevice 10 to an energized electron or ion beam that will evaporate thecompound layer 30. A laser, IR, or UV beam could also be used to remove thecompound layer 30. However, other suitable methods or techniques may also be used to remove thecompound layer 30. - Referring to FIG. 4, the
device 10 is illustrated after removal of portions oflayer 14 corresponding to thevias 20 and the mask layers 18, thereby providing the desired conductive or magnetic pattern.Layer 14 may be selectively removed from the via 20 locations using conventional methods, including, but not limited to, etching processes. However, it should be understood thatlayer 14 may remain on thedevice 10, for example, iflayer 14 comprises an insulating material. The mask layers 18 may be removed using conventional methods such as, but not limited to, a plasma process, a solvent dipping, or a combination of plasma processes and solvent dipping. For example, thephotoresist layer 24 may be removed using an acetone solution in an ultrasonic bath at approximately sixty degrees Celsius. However, other suitable methods may also be used to remove the mask layers 18. Additionally, the mask layers 18 may be removed either before or after the removal of thecompound layer 30, andlayer 14 may be removed either after or before removal of the mask layers 18. - FIG. 5 is a flow diagram illustrating a method for conductive pattern formation on a
device 10 in accordance with an embodiment of the present invention. The method begins atstep 100, where thebarrier layer 14 is formed upwardly from thesubstrate 16. However, it should be understood that thebarrier layer 14 may be omitted to accommodate aparticular device 10 configuration or materials selection. Atstep 102,conductive layer 12 is formed upwardly frombarrier layer 14, or upwardly from thesubstrate 16 if thebarrier layer 14 was omitted. As described above, theconductive layer 12 may include copper, nickel, iron, or other suitable conductive or magnetic materials. - At
step 104, one or more mask layers 18 are formed upwardly over portions of theconductive layer 12 to define a desired conductive pattern. For example, amask layer 18 is configured to a desired conductive pattern for thedevice 10, thereby creatingvias 20 corresponding to unmasked portions of theconductive layer 12 that will be removed to form the desired conductive pattern. Atstep 106, the device is exposed to a plasma in a plasma reactor. As described above, the plasma comprises a gas selected from the halogen group of elements such as, but not limited to, chlorine, bromine, fluorine, and iodine. Atstep 108, exposure of thedevice 10 to the plasma converts the unmasked portions of theconductive layer 12 to acompound layer 30. - At
decisional step 110, a determination is made whether to remove the mask layers 18 before or after removal of thecompound layer 30. If removal of the mask layers 18 is desired before removing thecompound layer 30, the method proceeds to step 112, where mask layers 18 are removed using conventional methods. If removal of the mask layers 18 is desired after removal of thecompound layer 30, the method proceeds fromstep 110 to step 114. - At
step 114, thecompound layer 30 is removed from thedevice 10, thereby forming the open areas orvias 20 in theconductive layer 12 corresponding to the previously unmasked portions of theconductive layer 12. Atstep 115,layer 14 may be removed from thesubstrate 16 corresponding to the via 20 locations. As described above,layer 14 may be removed either after or before removal of the mask layers 18. Atdecisional step 116, a determination is made whether the mask layers 18 were previously removed. If the mask layers 18 were not removed before removal of thecompound layer 30, the method proceeds fromstep 116 to step 118, where the mask layers 18 are removed. If the mask layers 18 were removed prior to removal of thecompound layer 30, the method terminates. - Thus, the present invention provides a conductive pattern formation method that provides greater control and creation of fine conductive interconnection lines or traces for semiconductors and other electronic devices than prior conductive pattern formation processes. Additionally, the conductive pattern formation method of the present invention may be used with conventional semiconductor fabrication equipment and facilities, thereby substantially reducing or eliminating costly facility upgrades, retrofits, or the design and manufacturing of unconventional new tools to form fine line conductive or magnetic patterns.
- Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (30)
1. A method for forming a conductive pattern for a semiconductor device, comprising:
patterning a mask layer outwardly from a conductive layer of the semiconductor device, the patterning defining portions of the conductive layer where vias through the conductive layer are desired;
exposing the semiconductor device to a plasma, the plasma converting the unmasked portions of the conductive layer into a compound; and
exposing the semiconductor device to a treatment process, the treatment process selectively removing the compound.
2. The method of claim 1 , wherein the conductive layer comprises a copper material.
3. The method of claim 1 , further comprising removing the mask layer from the semiconductor device.
4. The method of claim 3 , wherein removing the mask layer comprises removing the mask layer after removing the compound.
5. The method of claim 3 , wherein removing the mask layer comprises removing the mask layer before removing the compound.
6. The method of claim 1 , wherein exposing the semiconductor device to a treatment process comprises:
exposing the semiconductor device to a substantially inert atmosphere; and
heating the semiconductor device to between 300 and 800 degrees Celsius to remove the compound.
7. The method of claim 1 , further comprising providing a barrier layer between the conductive material and a substrate of the semiconductor device.
8. The method of claim 1 , wherein the conductive material comprises a copper material, and wherein exposing the semiconductor device to a plasma comprises exposing the semiconductor device to a chlorine-containing gas.
9. The method of claim 8 , wherein the compound comprises a copper chloride material, and wherein exposing the semiconductor device to a treatment process comprises exposing the semiconductor device to a hydrogen chloride solution to remove the copper chloride material.
10. The method of claim 1 , wherein the mask layer comprises a photoresist material.
11. A method for forming a conductive pattern for an electronic device, comprising:
forming a conductive layer outwardly from a substrate of the electronic device;
patterning a mask layer outwardly from the conductive layer, the patterning defining portions of the conductive layer where vias through the conductive layer are desired;
exposing the electronic device to a plasma, the plasma converting the unmasked portions of the conductive layer into a compound;
exposing the electronic device to a treatment process to selectively remove the compound; and
removing the mask layer from the masked portions of the conductive layer.
12. The method of claim 11 , wherein removing the mask layer comprises removing the mask layer before removing the compound.
13. The method of claim 11 , wherein forming a conductive layer comprises forming a copper layer outwardly from the substrate.
14. The method of claim 11 , wherein exposing the electronic device to a plasma comprises exposing the electronic device to a plasma, the plasma comprising a gas having an element selected from the halogen group of elements.
15. The method of claim 11 , further comprising providing a barrier layer between the conductive layer and the substrate of the electronic device.
16. The method of claim 11 , wherein exposing the electronic device to a plasma comprises controlling the exposure of the electronic device to the plasma to form a substantially perpendicular interface between the masked conductive material and the compound.
17. The method of claim 11 , wherein patterning a mask layer comprises patterning a photoresist layer outwardly from the conductive layer.
18. A method for forming a conductive pattern for an electronic device, comprising:
masking a portion of a conductive layer of the electronic device, the masked portion of the conductive layer defining the conductive pattern;
exposing the electronic device to a plasma, the plasma converting an unmasked portion of the conductive layer into a compound; and
exposing the electronic device to a treatment process, the treatment process selectively removing the compound.
19. The method of claim 18 , wherein masking a portion of a conductive layer comprises depositing a photoresist layer outwardly from a portion of the conductive layer.
20. The method of claim 19 , further comprising removing the photoresist layer after removing the compound.
21. The method of claim 19 , further comprising removing the photoresist layer before removing the compound.
22. The method of claim 18 , wherein exposing the electronic device to a plasma comprises exposing the electronic device to a plasma, the plasma comprising a gas having an element selected from the halogen group of elements.
23. The method of claim 22 , wherein the plasma comprises a chlorine-containing gas.
24. The method of claim 22 , wherein the plasma comprises a bromine-containing gas.
25. The method of claim 22 , wherein the plasma comprises a fluorine-containing gas.
26. The method of claim 22 , wherein the plasma comprises an iodine-containing gas.
27. The method of claim 18 , wherein exposing the electronic device to a plasma comprises controlling the exposure of the electronic device to the plasma to form a substantially perpendicular interface between the masked conductive material and the compound.
28. The method of claim 18 , wherein the conductive layer comprises a copper material.
29. The method of claim 28 , wherein exposing the electronic device comprises exposing the electronic device to a plasma, the plasma comprising a chlorine-containing gas, the plasma converting the unmasked portion of the conductive layer to copper chloride.
30. The method of claim 29 , wherein exposing the electronic device to a treatment process comprises exposing the electronic device to a hydrogen chloride solution to remove the copper chloride.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US09/736,043 US20020072228A1 (en) | 1999-12-15 | 2000-12-12 | Semiconductor conductive pattern formation method |
US10/753,214 US7037832B1 (en) | 1999-12-15 | 2004-01-05 | Method of forming a conductive pattern by removing a compound with heat in a substantially inert atmosphere |
Applications Claiming Priority (2)
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US17125999P | 1999-12-15 | 1999-12-15 | |
US09/736,043 US20020072228A1 (en) | 1999-12-15 | 2000-12-12 | Semiconductor conductive pattern formation method |
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US10/753,214 Continuation-In-Part US7037832B1 (en) | 1999-12-15 | 2004-01-05 | Method of forming a conductive pattern by removing a compound with heat in a substantially inert atmosphere |
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US20020072228A1 true US20020072228A1 (en) | 2002-06-13 |
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US10/753,214 Expired - Fee Related US7037832B1 (en) | 1999-12-15 | 2004-01-05 | Method of forming a conductive pattern by removing a compound with heat in a substantially inert atmosphere |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20040038547A1 (en) * | 2002-08-20 | 2004-02-26 | Seung-Young Son | Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas |
US6730237B2 (en) * | 2001-06-22 | 2004-05-04 | International Business Machines Corporation | Focused ion beam process for removal of copper |
US20060273069A1 (en) * | 2005-06-06 | 2006-12-07 | Fujifilm Electronic Imaging Ltd. | Forming a conductive pattern on a substrate |
US20090011604A1 (en) * | 2007-07-05 | 2009-01-08 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Photon induced removal of copper |
US20120001335A1 (en) * | 2010-07-02 | 2012-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Device and Manufacturing Method Thereof |
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US7540935B2 (en) * | 2003-03-14 | 2009-06-02 | Lam Research Corporation | Plasma oxidation and removal of oxidized material |
CN102800419B (en) * | 2011-05-27 | 2014-07-09 | 清华大学 | Method for preparing graphene conductive film structure |
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US5281447A (en) * | 1991-10-25 | 1994-01-25 | International Business Machines Corporation | Patterned deposition of metals via photochemical decomposition of metal-oxalate complexes |
US5350484A (en) * | 1992-09-08 | 1994-09-27 | Intel Corporation | Method for the anisotropic etching of metal films in the fabrication of interconnects |
US5736002A (en) * | 1994-08-22 | 1998-04-07 | Sharp Microelectronics Technology, Inc. | Methods and equipment for anisotropic, patterned conversion of copper into selectively removable compounds and for removal of same |
US5939334A (en) * | 1997-05-22 | 1999-08-17 | Sharp Laboratories Of America, Inc. | System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides |
US6010603A (en) * | 1997-07-09 | 2000-01-04 | Applied Materials, Inc. | Patterned copper etch for micron and submicron features, using enhanced physical bombardment |
US6057230A (en) * | 1998-09-17 | 2000-05-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dry etching procedure and recipe for patterning of thin film copper layers |
-
2000
- 2000-12-12 US US09/736,043 patent/US20020072228A1/en not_active Abandoned
-
2004
- 2004-01-05 US US10/753,214 patent/US7037832B1/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US6730237B2 (en) * | 2001-06-22 | 2004-05-04 | International Business Machines Corporation | Focused ion beam process for removal of copper |
US20040038547A1 (en) * | 2002-08-20 | 2004-02-26 | Seung-Young Son | Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas |
US7226867B2 (en) * | 2002-08-20 | 2007-06-05 | Samsung Electronics Co., Ltd. | Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas |
US20060273069A1 (en) * | 2005-06-06 | 2006-12-07 | Fujifilm Electronic Imaging Ltd. | Forming a conductive pattern on a substrate |
US7271099B2 (en) * | 2005-06-06 | 2007-09-18 | Ffei Limited | Forming a conductive pattern on a substrate |
US20090011604A1 (en) * | 2007-07-05 | 2009-01-08 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Photon induced removal of copper |
US20120001335A1 (en) * | 2010-07-02 | 2012-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Device and Manufacturing Method Thereof |
US8518762B2 (en) * | 2010-07-02 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
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