KR20070071165A - Method of crystallization and method of fabricating thin film transistor using thereof - Google Patents

Abstract

A crystallization method is provided to minimize the contamination of a silicon thin film by crystallizing a silicon thin film while using minimum catalyst metal. An amorphous silicon thin film is formed on a substrate. A metal layer is formed on the amorphous silicon thin film. A heat treatment is performed on the substrate at a first temperature for a time interval of t1 to form a seed on the amorphous silicon thin film. A heat treatment is performed in an atmosphere of oxidation on the substrate at a second temperature for a time interval of t2 to crystallize the amorphous silicon thin film. The metal layer can be transition metal including nickel.

Description

Crystallization method and manufacturing method of thin film transistor using the same {METHOD OF CRYSTALLIZATION AND METHOD OF FABRICATING THIN FILM TRANSISTOR USING THEREOF}

1A to 1D are cross-sectional views sequentially illustrating a crystallization method according to an embodiment of the present invention.

2A and 2B are cross-sectional views specifically showing the crystallization process shown in FIG. 1C.

3 is a graph showing the crystallization process of the present invention in two stages of crystallization according to time and temperature.

4 is a plan view schematically illustrating a structure of a liquid crystal display panel according to an exemplary embodiment of the present invention.

5A to 5I are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor using the crystallization method of the present invention.

** Explanation of symbols for main parts of drawings **

110, 210, 310: array substrate 111,311: buffer layer

120,220: amorphous silicon thin film 120 ', 320': polycrystalline silicon thin film

150: catalytic metal

The present invention relates to a crystallization method and a method for manufacturing a thin film transistor using the same, and more particularly, to a crystallization method for minimizing contamination by metal elements in a metal induced crystallization method and a method for manufacturing a thin film transistor using the same. will be.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, is a method of driving the liquid crystal of the pixel portion by using an amorphous silicon thin film transistor (TFT) as a switching element. .

Amorphous silicon thin film transistor technology was established in 1979 by LeComber et al., UK, and was commercialized in 1986 as a 3 inch liquid crystal portable television. Recently, a large area thin film transistor liquid crystal display device of 50 inches or more has been developed.

However, the amorphous silicon thin film transistor is a peripheral circuit such as a CMOS (Complementary Metal Oxide Semiconductor) that requires high-speed operation of 1 MHz or more with a field effect mobility (<1 cm ² / Vsec) of electrons as carriers. There is a limit to use.

Accordingly, studies are being actively conducted to simultaneously integrate the pixel portion and the driving circuit portion on a glass substrate using a polycrystalline silicon thin film transistor having a greater field effect mobility than the amorphous silicon thin film transistor.

Polycrystalline silicon thin film transistor technology has been applied to small modules such as camcorders since the development of liquid crystal color television in 1982. Since it can realize low photosensitivity and high field effect mobility compared to amorphous silicon thin film transistors, ) And the driving circuit can be manufactured directly on the same substrate.

This integration eliminates the need for an additional process of connecting a driver integrated circuit (driver IC) and a pixel array, which has been conventionally required, thereby greatly improving productivity and reliability. As described above, the excellent characteristics of the polycrystalline silicon thin film As a result, it is possible to fabricate smaller and superior thin film transistors.

Despite the advantages of polycrystalline silicon thin film transistors, high-temperature processes using expensive quartz substrates are required for manufacturing, so the application field is limited to small-area high-resolution liquid crystal displays, and low-temperature processes using low-cost glass substrates are amorphous. Compared to silicon thin film transistors, it is limiting the application of large area liquid crystal display devices.

The polycrystalline silicon thin film transistor as described above requires a polycrystalline silicon thin film as an active layer. As a method of manufacturing the polycrystalline silicon thin film, a method of forming a polycrystalline silicon thin film directly by as-deposition on a substrate and forming a substrate on the substrate There is a method in which an amorphous silicon thin film is deposited and then thermally crystallized. In particular, in order to use a low cost glass substrate, a low temperature process is required, and a method for improving the field effect mobility of a thin film transistor is required for use in an element of a driving circuit unit.

In this case, the solid phase crystallization (SPC) method, which is generally used to fabricate a polycrystalline silicon thin film, can obtain a uniform polycrystalline silicon thin film even with a relatively simple process, but the heat treatment temperature is higher than 600 ° C. and the heat treatment time is also high. It has a disadvantage that it is difficult to use a glass substrate because it is long for several tens of hours.

In addition, the polycrystalline silicon thin film obtained by the solid-phase crystallization method has a relatively large grain (grain) of the order of several micrometers level, but there is a disadvantage that many defects are formed in the grain. The defect is known to adversely affect the performance of the thin film transistor after the grain boundary region.

Recently, various crystallization methods have been studied to fabricate polycrystalline silicon thin film transistors at low temperature, and a method that is currently emerging is a crystallization method using an excimer laser (EL).

In the case of the excimer laser crystallization, there is almost no crystal defect seen in the polycrystalline silicon thin film crystallized by the solid-state crystallization method, so that an excellent electrical characteristic can be obtained. However, the process window is narrow and the reproducibility and The problem is that uniformity is poor.

In addition, there is a metal induced crystallization (MIC) method. In the case of the metal induced crystallization, the crystallization temperature of silicon is greatly reduced by using a catalytic metal, but leakage current is caused by contamination of the silicon thin film by the metal element. Has a disadvantage of large. As described above, the catalytic metal greatly assists in crystallization such as lowering the crystallization temperature. However, the catalytic metal remains in the active layer even after crystallization, thus adversely affecting device characteristics such as increasing the leakage current of the thin film transistor. At this time, when the concentration of the catalyst metal is too low, there is a problem that the crystallization characteristics are lowered or the crystallization proceeds unevenly.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a crystallization method having a uniform crystallization characteristic without deterioration of device characteristics by improving the crystallization method and a method of manufacturing a thin film transistor using the same.

Another object of the present invention is to provide a crystallization method which minimizes contamination by metal elements and improves electrical characteristics of a thin film transistor, and a method of manufacturing a thin film transistor using the same.

Further objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, the crystallization method of the present invention comprises the steps of forming an amorphous silicon thin film on a substrate; Forming a metal layer on the amorphous silicon thin film; Heat treating the substrate at a first temperature for t1 time to form a seed on the surface of the amorphous silicon thin film; And heat treating the substrate at a second temperature in an oxidizing atmosphere for t2 hours to crystallize the amorphous silicon thin film.

In addition, the method of manufacturing a thin film transistor of the present invention comprises the steps of providing a substrate; Forming an amorphous silicon thin film on the substrate; Forming a metal layer on the amorphous silicon thin film; Heat treating the substrate at a first temperature for t1 time to form a seed on the surface of the amorphous silicon thin film; Heat treating the substrate at a second temperature in an oxidizing atmosphere for t2 hours to crystallize the amorphous silicon thin film; Patterning the crystallized silicon thin film to form an active layer; Forming a gate insulating film on the substrate; Forming a gate electrode on the substrate; Implanting impurity ions into a predetermined region of the active layer using the gate electrode as a mask to form a source region and a drain region; Forming an interlayer insulating film having contact holes formed on the substrate; And forming a source electrode electrically connected to the source region through the contact hole and a drain electrode electrically connected to the drain region.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the crystallization method and a method for manufacturing a thin film transistor using the same according to the present invention.

1A to 1D are cross-sectional views sequentially illustrating a crystallization method according to an embodiment of the present invention.

In this case, the present embodiment is described as an example of a silicon thin film to be crystallized, but the present invention is not limited thereto.

First, as shown in FIG. 1A, a buffer layer 111 having a predetermined thickness is formed on the entire surface of the substrate 110 made of a transparent insulating material such as glass.

The buffer layer 111 serves to block impurities such as sodium (natrium) from the substrate 110 from penetrating into the upper layer during the crystallization process.

In addition, an amorphous silicon thin film 120 and a predetermined cap layer 130 are formed on the substrate 110 on which the buffer layer 111 is formed.

The cap layer 130 may be formed as an insulating film of a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiNx), and minimizes penetration of the catalyst metal due to metal induction crystallization into the lower amorphous silicon thin film 120. do. At this time, when the cap layer 130 is formed of a silicon oxide film is formed to a thickness of about 50 ~ 100Å.

Representative methods of depositing the amorphous silicon thin film 120 include a low pressure chemical vapor deposition (LPCVD) method and a plasma enhanced chemical vapor deposition (PECVD) method. In the case of depositing the amorphous silicon thin film 120 by the plasma chemical vapor deposition method, although it is slightly different depending on the temperature of the substrate during deposition, about 20% of hydrogen atoms are included in the amorphous silicon thin film 120.

Next, as shown in FIG. 1B, a small amount of catalytic metal 150 is deposited on the cap layer 120.

In this case, as the catalyst metal 150, a transition metal such as nickel (Ni), aluminum (aluminum; Al), ferrum (Fe), cobalt (Co) or chromium (chromium) may be used. Can be.

Thereafter, as shown in FIGS. 1C and 1D, the crystallization of the present embodiment includes two crystallization processes, a first crystallization process and a second crystallization process, on the substrate 110 on which the catalytic metal 150 is deposited. By proceeding to form a uniform crystalline silicon thin film 120 'on the substrate 110, which will be described in detail with reference to the drawings.

2A and 2B are cross-sectional views illustrating the crystallization process of FIG. 1C in detail, and the enlarged portion A of FIG. 1C is shown. FIG. 3 illustrates two steps of crystallization of the crystallization process of the present invention according to time and temperature. It is a graph shown by the process.

At this time, time t1 of FIG. 3 represents the progress time of the first crystallization process, and time t2 represents the progress time of the second crystallization process. At the time t2 or more, crystallization of the predetermined amorphous silicon thin film is completed.

In addition, the temperature Tc of FIG. 3 represents an initial temperature at which a predetermined amorphous silicon thin film starts to crystallize.

As shown in FIG. 2A, when the first crystallization is performed on the substrate 110 on which the catalytic metal 150 is deposited in a small amount of heat treatment equipment, a portion of the catalyst metal 150 may be disposed on the lower cap layer ( Diffuse through 130 to crystallize a portion of the surface of the amorphous silicon thin film 120.

The heat treatment equipment includes a blast furnace (furnace) or RTA (Rapid Thermal Annealing) equipment or alternating magnetic field (Alternating Magnetic Field) equipment.

In this case, the first crystallization is continued for a time t1 at a predetermined crystallization temperature (Tc) to form a crystalline silicon thin film 120 ′ having a minimum silicon seed formed on a portion of the surface of the amorphous silicon thin film 120.

In addition, the first crystallization is performed in a reducing or inert atmosphere in which a general crystallization process is performed. For example, the first crystallization process is performed while maintaining the chamber in a reducing or inert atmosphere with H ₂ or a gas such as Ar or He.

The first crystallization process is continued for a predetermined time t1 for forming a minimum silicon seed for the entire amorphous silicon thin film 120 to crystallize, wherein if the first crystallization is continued for a time t1 or more, unnecessary catalyst The metal 150 flows into the amorphous silicon thin film 120 to cause metal contamination.

Thereafter, as shown in FIG. 2B, the entire amorphous silicon thin film is crystallized into the crystalline silicon thin film 120 ′ through a second crystallization process using the silicon seed formed on the surface of the amorphous silicon thin film.

The second crystallization proceeds for a predetermined t2 time period when the entire amorphous silicon thin film is crystallized. At this time, the second crystallization is performed while the inside of the chamber is made into an oxidizing atmosphere by using a gas such as O ₂ .

In the oxidation atmosphere, the upper catalyst metal 150 is oxidized during the second crystallization process so that it is no longer introduced into the lower silicon thin films 120 and 120 ', and the crystalline silicon thin film formed through the first crystallization ( 120 ') is used as a seed and crystallization proceeds.

In this case, the second crystallization may proceed at the same temperature (①) as the crystallization temperature (Tc), as shown in Figure 3, at a lower temperature (②) or higher temperature (③) than the crystallization temperature (Tc) You can also proceed.

In addition, the first crystallization and the second crystallization may be continuously performed in the same heat treatment equipment, and if necessary, the first crystallization and the second crystallization may be performed in different heat treatment equipment.

As described above, the crystallization method of the present embodiment can crystallize the silicon thin film using the minimum catalyst metal through the two-step crystallization process, thereby minimizing the contamination of the silicon thin film by the catalyst metal. In addition, since the crystallization method merely divides the crystallization step into a step of forming a seed and proceeding crystallization through the seed, a large-area silicon thin film can be uniformly crystallized in a relatively simple method.

In addition, when the metal induction crystallization using the catalyst metal is an additional process of removing the metal elements remaining in the active layer, in the present embodiment, since the amount of the catalyst metal initially introduced into the silicon thin film can be minimized. The same residual gettering process is eliminated.

In this case, the silicon thin film crystallized in accordance with an embodiment of the present invention can be used in the fabrication of semiconductor devices such as thin film transistors, solar cells, image sensors, and the like, and a thin film transistor made of the crystallized silicon thin film and a liquid crystal display panel having the same. For example, as follows.

4 is a plan view schematically illustrating a structure of a liquid crystal display panel according to an exemplary embodiment of the present invention, and illustrates a driving circuit-integrated liquid crystal display panel in which a driving circuit unit is integrated on an array substrate.

As shown in the drawing, the driving circuit-integrated liquid crystal display panel 300 is largely composed of an array substrate 310 and a color filter substrate 320 and a liquid crystal layer formed between the array substrate 310 and the color filter substrate 320. Not shown).

The array substrate 310 includes a pixel portion 315, which is an image display area in which unit pixels are arranged in a matrix form, a gate driving circuit portion 314 and a data driving circuit portion 313 disposed outside the pixel portion 315. have.

In this case, although not shown in the drawing, the pixel portion 315 of the array substrate 310 is arranged horizontally and horizontally on the array substrate 310 to define a plurality of gate lines and data lines, the gate line and A thin film transistor, which is a switching element formed in an intersection region of a data line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching element that applies and cuts off a signal voltage to a pixel electrode and is a type of field effect transistor (FET) that controls the flow of current by an electric field.

In the gate driving circuit unit 314 and the data driving circuit unit 313, the data driving circuit unit 313 is positioned at one long side of the array substrate 310 protruding from the color filter substrate 320. The gate driving circuit unit 314 is positioned at one end side of the array substrate 310.

In this case, the gate driving circuit unit 314 and the data driving circuit unit 313 use a thin film transistor having a complementary metal oxide semiconductor (CMOS) structure which is an inverter to properly output the input signal.

For reference, the CMOS is an integrated circuit having a MOS structure which is used for a thin film transistor of a driving circuit unit requiring high speed signal processing, and requires a transistor of a P channel and an N channel, and the characteristics of speed and density are intermediate between NMOS and PMOS. It shows form.

The gate driving circuit unit 314 and the data driving circuit unit 313 are devices for supplying scan signals and data signals to pixel electrodes through gate lines and data lines, respectively, and are connected to an external signal input terminal (not shown). It controls the external signal input through the external signal input terminal to output to the pixel electrode.

In this case, a color filter (not shown) for implementing color and a common electrode (not shown), which is a counter electrode of a pixel electrode formed on the array substrate 310, are formed in the image display area 115 of the color filter substrate 320. It is.

The array substrate 310 and the color filter substrate 320 configured as described above are provided with a cell gap so as to be uniformly spaced apart by a spacer (not shown), and a seal pattern (not shown) formed outside the image display area. Are bonded to form a unit liquid crystal display panel. At this time, the bonding between the array substrate 310 and the color filter substrate 320 is performed through a bonding key (not shown) formed on the array substrate 310 or the color filter substrate 320.

Hereinafter, the thin film transistor of the present invention provided in the driving circuit-integrated liquid crystal display panel configured as described above will be described in detail through the manufacturing method thereof.

5A to 5I are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor using the crystallization method of the present invention.

In this case, the thin film transistors formed in the pixel portion and the driving circuit portion may be N type or P type. In particular, the driving circuit portion may have a CMOS type in which both the N type thin film transistor and the P type thin film transistor are formed. The method of manufacturing the CMOS of the circuit portion is shown.

In addition, the left side of the figure shows the method of manufacturing the NMOS which is an N type thin film transistor, and the right side of the figure shows the method of manufacturing the PMOS which is a P type thin film transistor.

First, as illustrated in FIG. 5A, a buffer layer 311 formed of a silicon oxide film SiO ₂ is formed on a substrate 310 made of a transparent insulating material such as glass.

Next, as shown in FIG. 5B, after depositing an amorphous silicon thin film to a predetermined thickness on the substrate 310 on which the buffer layer 311 is formed, the amorphous silicon thin film is crystallized using the crystallization method of the present invention described above. The crystalline silicon thin film 320 'is formed.

At this time, as described above, the crystallization is a two-step crystallization process, by forming a small amount of seeds on the surface of the silicon thin film through the first crystallization process and crystallizing the silicon thin film in the oxidation atmosphere of the second crystallization process, It is possible to minimize the contamination by the large-size silicon thin film at the same time uniformly.

Next, as shown in FIG. 5C, the crystallized polycrystalline silicon thin film is patterned using a photolithography process to form active layers 324N and 324P in the NMOS and PMOS regions, respectively.

Thereafter, as shown in FIG. 5D, a gate insulating film 315A is deposited on the entire surface of the substrate 310 on which the active layers 324N and 324P are formed.

As shown in FIG. 5E, gate electrodes 321N and 321P are formed in a predetermined region of the substrate 310 on which the gate insulating film 315A is deposited.

5F and 5G sequentially perform an N doping process and a P doping process, and n + ions are implanted into a predetermined region of an N type thin film transistor (i.e., an active layer 324N) to form an N type source / drain region. 324NS, 324ND) and P-type thin film transistors are shown.

First, as illustrated in FIG. 5F, the PMOS region is covered by the photoresist pattern 380 to implant an N-type thin film transistor, and then n + ions are implanted into the entire surface of the substrate 310.

That is, the NMOS region implants a high concentration of impurity ions into only a predetermined region of the N-type active layer 324N using the gate electrode 321N as a mask to form an N-type source / drain as an ohmic contact layer. Areas 324NS and 324ND are formed. In this case, the gate electrode 321N serves as an ion stopper to prevent the dopant from penetrating into the channel region of the active layer 324N.

In this case, the N-type source / drain regions 324NS and 324ND are formed by injecting a Group 5 element such as phosphorus (P) that can donate electrons.

Next, as shown in FIG. 5G, a photoresist pattern 380 covering the NMOS region is formed to form a P-type thin film transistor.

In this case, the P-type source / drain regions 324PS and 324PD are formed by injecting a group 3 element such as boron (B) which can provide a hole.

Next, as shown in FIG. 5H, the N-type source / drain regions 324NS and 324ND and the P-type source / are deposited using a photolithography process after depositing the interlayer insulating film 315B on the entire surface of the substrate 310. First contact holes 390N and second contact holes 390P exposing portions of the drain regions 324PS and 324PD are formed.

As illustrated in FIG. 5I, the N-type source / drain regions 324NS and 324ND and the P-type source / drain region 324PS may be formed through the first contact hole 390N and the second contact hole 390P. The N type source / drain electrodes 322N and 323N and P type source / drain electrodes 322P and 323P electrically connected to the 324PD are formed.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the crystallization method according to the present invention can crystallize the silicon thin film using a minimum amount of catalyst metal, thereby minimizing contamination of the silicon thin film by the catalyst metal.

In addition, the crystallization method according to the present invention is able to uniformly crystallize a large area of the silicon thin film through a relatively simple method and heat treatment equipment to provide an effect of improving productivity.

In addition, when the thin film transistor is manufactured using the silicon thin film crystallized in the above manner, the device characteristics such as low leakage current are improved.

Claims (23)

Forming an amorphous silicon thin film on the substrate; Forming a metal layer on the amorphous silicon thin film; Heat treating the substrate at a first temperature for t1 time to form a seed on the surface of the amorphous silicon thin film; And heat-treating the substrate at a second temperature in an oxidizing atmosphere for t2 hours to crystallize the amorphous silicon thin film. The method of claim 1, wherein the metal layer is a crystallization method, characterized in that the transition metal. 3. The method of claim 2 wherein the transition metal comprises nickel. The method of claim 1, further comprising forming a buffer layer over the substrate. The method of claim 1, further comprising forming a cap layer of an insulating film on the amorphous silicon thin film. The method of claim 1, wherein the substrate is heat-treated in a reducing or inert atmosphere to form a silicon seed on the surface of the amorphous silicon thin film. 7. The method of claim 6, wherein the reducing atmosphere is formed of H ₂ gas, and the inert atmosphere is formed of Ar gas or He gas. The crystallization method according to claim 1, wherein the oxidation atmosphere is formed of O ₂ gas. The method of claim 1, wherein the first temperature is a temperature at which a silicon seed is formed on a surface of the amorphous silicon thin film. The crystallization method of claim 1, wherein the t1 time means a minimum time at which a silicon seed required to crystallize the entire amorphous silicon thin film is formed. The crystallization method of claim 1, wherein the t2 time means a minimum time for all of the amorphous silicon thin films to crystallize. The method of claim 1, wherein said second temperature is the same as said first temperature. The method of claim 1, wherein the second temperature is lower or higher than the first temperature. Providing a substrate; Forming an amorphous silicon thin film on the substrate; Forming a metal layer on the amorphous silicon thin film; Heat treating the substrate at a first temperature for t1 time to form a seed on the surface of the amorphous silicon thin film; Heat treating the substrate at a second temperature in an oxidizing atmosphere for t2 hours to crystallize the amorphous silicon thin film; Patterning the crystallized silicon thin film to form an active layer; Forming a gate insulating film on the substrate; Forming a gate electrode on the substrate; Implanting impurity ions into a predetermined region of the active layer using the gate electrode as a mask to form a source region and a drain region; Forming an interlayer insulating film having contact holes formed on the substrate; And Forming a source electrode electrically connected to the source region through the contact hole and a drain electrode electrically connected to the drain region. 15. The method of claim 14, wherein the metal layer is made of a transition metal. 15. The method of claim 14, wherein the substrate is heat-treated in a reducing or inert atmosphere to form a silicon seed on the surface of the amorphous silicon thin film. The method of claim 16, wherein the reducing atmosphere is formed of H ₂ gas, and the inert atmosphere is formed of Ar gas or He gas. 15. The method of claim 14, wherein the oxidation atmosphere is formed of O ₂ gas. The method of claim 14, wherein the first temperature means a temperature at which a silicon seed is formed on a surface of the amorphous silicon thin film. 15. The method of claim 14, wherein the t1 time means a minimum time at which a silicon seed required to crystallize the entire amorphous silicon thin film is formed. 15. The method of claim 14, wherein the t2 time is a minimum time for all of the amorphous silicon thin film to crystallize. 15. The method of claim 14, wherein the second temperature is the same as the first temperature. 15. The method of claim 14, wherein the second temperature is lower or higher than the first temperature.

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