KR20060088023A - 반도체장치 및 그 제조 방법과 반도체 집적회로 - Google Patents

반도체장치 및 그 제조 방법과 반도체 집적회로 Download PDF

Info

Publication number
KR20060088023A
KR20060088023A KR1020060006168A KR20060006168A KR20060088023A KR 20060088023 A KR20060088023 A KR 20060088023A KR 1020060006168 A KR1020060006168 A KR 1020060006168A KR 20060006168 A KR20060006168 A KR 20060006168A KR 20060088023 A KR20060088023 A KR 20060088023A
Authority
KR
South Korea
Prior art keywords
type impurity
layer
region
insulating layer
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020060006168A
Other languages
English (en)
Korean (ko)
Inventor
토시키 카나모토
마스미 요시다
테쓰야 와타나베
타카시 이포우시
Original Assignee
가부시끼가이샤 르네사스 테크놀로지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 르네사스 테크놀로지 filed Critical 가부시끼가이샤 르네사스 테크놀로지
Publication of KR20060088023A publication Critical patent/KR20060088023A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020060006168A 2005-01-31 2006-01-20 반도체장치 및 그 제조 방법과 반도체 집적회로 Withdrawn KR20060088023A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP-P-2005-00022806 2005-01-31
JP2005022806 2005-01-31
JPJP-P-2005-00354478 2005-12-08
JP2005354478A JP2006237564A (ja) 2005-01-31 2005-12-08 半導体装置及びその製造方法並びに半導体集積回路

Publications (1)

Publication Number Publication Date
KR20060088023A true KR20060088023A (ko) 2006-08-03

Family

ID=36755625

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060006168A Withdrawn KR20060088023A (ko) 2005-01-31 2006-01-20 반도체장치 및 그 제조 방법과 반도체 집적회로

Country Status (4)

Country Link
US (2) US7432581B2 (https=)
JP (1) JP2006237564A (https=)
KR (1) KR20060088023A (https=)
TW (1) TW200636907A (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5520435B2 (ja) * 2007-05-11 2014-06-11 ラピスセミコンダクタ株式会社 半導体素子の製造方法
FR2968128B1 (fr) * 2010-11-26 2013-01-04 St Microelectronics Sa Cellule precaracterisee pour circuit intégré
US9318607B2 (en) * 2013-07-12 2016-04-19 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR102101836B1 (ko) 2014-07-24 2020-04-17 삼성전자 주식회사 딜레이 셀 및 이를 적용하는 지연 동기 루프 회로와 위상 동기 루프 회로
JP7228020B2 (ja) * 2017-11-14 2023-02-22 ルネサスエレクトロニクス株式会社 半導体装置
KR102918411B1 (ko) * 2021-03-12 2026-01-26 삼성전자주식회사 반도체 장치
TWI848274B (zh) * 2022-03-17 2024-07-11 旺宏電子股份有限公司 佈線圖案
US12205894B2 (en) 2022-03-17 2025-01-21 Macronix International Co., Ltd. Routing pattern

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6740958B2 (en) * 1985-09-25 2004-05-25 Renesas Technology Corp. Semiconductor memory device
US5452251A (en) * 1992-12-03 1995-09-19 Fujitsu Limited Semiconductor memory device for selecting and deselecting blocks of word lines
JP3173268B2 (ja) * 1994-01-06 2001-06-04 富士電機株式会社 Ｍｉｓ電界効果トランジスタを備えた半導体装置
US5702957A (en) * 1996-09-20 1997-12-30 Lsi Logic Corporation Method of making buried metallization structure
JP4278202B2 (ja) 1998-03-27 2009-06-10 株式会社ルネサステクノロジ 半導体装置の設計方法、半導体装置及び記録媒体
JP4540146B2 (ja) 1998-12-24 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TW498435B (en) * 2000-08-15 2002-08-11 Hitachi Ltd Method of producing semiconductor integrated circuit device and method of producing multi-chip module
US6627484B1 (en) * 2000-11-13 2003-09-30 Advanced Micro Devices, Inc. Method of forming a buried interconnect on a semiconductor on insulator wafer and a device including a buried interconnect
KR100672932B1 (ko) 2000-12-26 2007-01-23 삼성전자주식회사 실리콘 온 인슐레이터 트랜지스터 및 그 제조방법
TW533592B (en) * 2001-02-16 2003-05-21 Canon Kk Semiconductor device, method of manufacturing the same and liquid jet apparatus
JP4154578B2 (ja) 2002-12-06 2008-09-24 日本電気株式会社 半導体装置及びその製造方法
JP3809168B2 (ja) * 2004-02-03 2006-08-16 株式会社東芝 半導体モジュール
JP4814705B2 (ja) * 2005-10-13 2011-11-16 パナソニック株式会社 半導体集積回路装置及び電子装置
JP2007208004A (ja) * 2006-02-01 2007-08-16 Matsushita Electric Ind Co Ltd 半導体集積回路装置及び電子装置

Also Published As

Publication number Publication date
US7432581B2 (en) 2008-10-07
JP2006237564A (ja) 2006-09-07
TW200636907A (en) 2006-10-16
US20060170052A1 (en) 2006-08-03
US20090011568A1 (en) 2009-01-08

Similar Documents

Publication Publication Date Title
US8377778B2 (en) Asymmetric segmented channel transistors
US7786535B2 (en) Design structures for high-voltage integrated circuits
KR100220608B1 (ko) 반도체 장치
US9059018B2 (en) Semiconductor device layout reducing imbalance in characteristics of paired transistors
US20110033989A1 (en) Semiconductor device having multi-gate structure and method of manufacturing the same
US20060163665A1 (en) Dummy patterns in integrated circuit fabrication
KR20040064279A (ko) 반도체 장치 및 제조 방법
US8368170B2 (en) Reducing device performance drift caused by large spacings between active regions
KR20130100660A (ko) 반도체 소자와 그 제조 및 설계 방법
CN107180871A (zh) 半导体器件
US20090011568A1 (en) Semiconductor device, method of manufacture thereof and semiconductor integrated circuit
US20110042750A1 (en) Controlling gate formation for high density cell layout
JP2005101217A (ja) スタティックランダムアクセスメモリ
JP2007519239A (ja) 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化ｓｏｉ構造
KR890004797B1 (ko) 우물영역을 갖는 반도체기판상에 형성되는 mis형 반도체장치
US6111293A (en) Silicon-on-insulator MOS structure
CN120916455A (zh) 半导体结构的制备方法及半导体结构
JP2011243843A (ja) 半導体装置
US7683402B2 (en) Semiconductor device and manufacturing method thereof
CN223067438U (zh) 半导体装置
TWI903518B (zh) 半導體元件
US20250287639A1 (en) Semiconductor device and semiconductor device manufacturing method
US7638837B2 (en) Stress enhanced semiconductor device and methods for fabricating same
US20240371954A1 (en) Semiconductor device having reduced noise and method of manufacturing the same
US7772651B2 (en) Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000