KR20060075045A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR20060075045A KR20060075045A KR1020040113594A KR20040113594A KR20060075045A KR 20060075045 A KR20060075045 A KR 20060075045A KR 1020040113594 A KR1020040113594 A KR 1020040113594A KR 20040113594 A KR20040113594 A KR 20040113594A KR 20060075045 A KR20060075045 A KR 20060075045A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 66
- 239000011229 interlayer Substances 0.000 claims description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 239000002184 metal Substances 0.000 abstract description 15
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- 230000004888 barrier function Effects 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 16
- 238000010438 heat treatment Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910008938 W—Si Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 상부 게이트로 쓰이는 WSix층과 상부 배선과의 콘택 공정시 장벽금속층의 Ti가 원활하게 Si과 결합될 수 있도록 콘택 부위의 WSix상에 불순물을 이온주입하여 비정질층을 형성하고, 후속 공정을 진행하여 WSix층과 Ti층의 계면에 Ti가 남지 않도록 하였으므로, 콘택 저항이 감소되어 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있으며, 고집적 소자의 제조에 유리하다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, an ion is implanted with impurities on the WSix of a contact portion so that Ti of the barrier metal layer can be smoothly combined with Si during a contact process between the WSix layer used as the upper gate and the upper wiring. To form an amorphous layer and to proceed with subsequent steps to prevent Ti from remaining at the interface between the WSix layer and the Ti layer, thereby reducing contact resistance, thereby improving process yield and reliability of device operation. Do.
금속배선 콘택, WSix, 불순물 이온주입 Metallization Contact, WSix, Impurity Ion Implantation
Description
도 1은 종래 기술에 따른 반도체소자의 단면도. 1 is a cross-sectional view of a semiconductor device according to the prior art.
도 2는 WSix층에서 W-Si의 상태를 도시한 개략도.2 is a schematic diagram showing the state of W-Si in the WSix layer.
도 3a 및 도 3b는 본 발명에 따른 반도체소자의 제조 공정도.3a and 3b is a manufacturing process diagram of a semiconductor device according to the present invention.
도 4는 종래 기술과 본 발명에 따른 콘택 저항의 비교 그래프.
Figure 4 is a comparison graph of the contact resistance according to the prior art and the present invention.
<도면의 주요 부분에 대한 부호의 설명> <Explanation of symbols for the main parts of the drawings>
10, 30 : 제1층간절연막 12, 32 : WSix층10, 30: first interlayer
14, 34 : 제2층간절연막 16, 36 : Ti층14, 34: second interlayer
18, 38 : TiN층 20, 40 : W층 18, 38:
22, 42 : Ti 실리사이드층 35 : 비정질층
22, 42
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 WSix과 상부 금속 배선과의 콘택 공정시 장벽금속층의 Ti가 남는 것을 방지하여 콘택 저항을 감소시켜 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a semiconductor capable of improving the process yield and the reliability of device operation by reducing contact resistance by preventing Ti from remaining in the barrier metal layer during the contact process between WSix and the upper metal wiring. It relates to a method for manufacturing a device.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다. The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
이러한 감광막 패턴의 분해능(R)은 감광막 자체의 재질이나 기판과의 접착력 등과도 밀접한 연관이 있으나, 일차적으로는 사용되는 축소노광장치의 광원 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture; NA, 개구수)에 반비례한다. The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 라인/스페이스 패턴의 경우 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해서는 이보다 파장이 더 작은 원자외선(deep ultra violet; DUV), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하여야 한다. Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV) wavelengths, for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.
또한 축소노광장치와는 별도로 공정 상의 방법으로는 노광마스크(photo mask)로서 위상반전마스크(phase shift mask)를 사용하는 방법이나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법이나, 두층의 감광막 사이에 에스.오.지(spin on glass; SOG)등의 중간층을 개재시킨 삼층레지스트(Tri layer resister; 이하 TLR이라 칭함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다. In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.
또한 상하의 도전배선을 연결하는 콘택홀은 상기에서의 라인/스페이스 패턴에 비해 디자인 룰이 더 크게 나타나는데, 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 종횡비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다. In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the diameter of the contact hole is reduced. The aspect ratio, which is the ratio of depths, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 홀간의 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration)등과 같은 요인들을 고려하여 마스크를 형성하여야하므로 더욱 공정마진이 감소되어 소자의 고집적화를 방해한다. These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, Since the mask must be formed in consideration of factors such as registration between the masks, the process margin is further reduced to prevent high integration of the device.
도 1은 종래 기술에 따른 반도체소자의 단면도로서, 반도체기판상에 소자분리 산화막과 워드라인 등의 소정의 하부 구조물을 순차적으로 형성하고, 상기 구조의 전표면에 제1층간절연막(10)을 도포한 후, 상기 제1층간절연막(10)상에 하부 금속배선인 WSix층(12) 패턴을 형성하고, 상기 구조의 전표면에 제2층간절연막(14)을 형성한다. 1 is a cross-sectional view of a semiconductor device according to the prior art, in which predetermined lower structures such as a device isolation oxide film and a word line are sequentially formed on a semiconductor substrate, and a first
그다음 상기 제2층간절연막(14)을 콘택 마스크를 이용한 사진식각 공정을 상 기 WSix층(12) 패턴을 노출시키는 콘택홀을 형성하고, 상기 구조의 전표면에 장벽금속층인 Ti층(16)과 TiN층(18) 및 상부 금속배선인 W층(20)을 순차적으로 형성한 후, 열처리하여 상기 WSix층(12)의 Si과 Ti층(16)의 Ti를 반응시켜 Ti 실리사이드층(TiSi2; 22)을 형성시켜 콘택 저항을 감소시킨다. Then, a contact hole for exposing the pattern of the WSix
상기와 같은 종래 기술에 따른 반도체소자의 제조방법은 하부 WSix층과 상부 배선과의 콘택 공정에서 장벽금속층인 Ti층/TiN층 증착 및 열처리 공정시 WSix내의 과잉 Si이 Ti와 반응하는데, 이때 Ti 증착 온도와 열처리 온도만으로는 반응에너지가 부족하여 도 1에서와 같이 Ti층과 WSix의 계면에 반응하지 않은 Ti(24)가 남아 있게 되고, 이로 인하여 콘택 저항이 증가되어 공정 수율 및 소자 동작의 신뢰성을 떨어뜨리는 문제점이 있다.
In the method of manufacturing a semiconductor device according to the prior art as described above, excess Si in WSix reacts with Ti during the deposition and heat treatment of the Ti / TiN layer, which is a barrier metal layer, in the contact process between the lower WSix layer and the upper wiring. The reaction energy is insufficient only by the temperature and the heat treatment temperature. As shown in FIG. 1, Ti (24) which remains unreacted at the interface between the Ti layer and the WSix remains, resulting in an increase in contact resistance, which lowers process yield and reliability of device operation. There is a floating problem.
본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 금속배선 콘택시 하부 금속배선의 콘택 면에 불순물을 이온주입하여 Si가 충분히 존재하도록 하고, 후속 공정을 진행하여 WSix와 장벽금속층의 계면에 Ti가 남지 않도록 하여 콘택 저항을 감소시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.
The present invention is to solve the above problems, an object of the present invention is to implant the impurities into the contact surface of the lower metal wiring in the metal wiring contact to ensure that the Si is sufficiently present, and to proceed to the subsequent process WSix and barrier metal layer A method of manufacturing a semiconductor device capable of reducing contact resistance by preventing Ti from remaining at an interface of is provided.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법의 특징은,Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
소정의 하부 구조물을 가지는 반도체기판상에 제1층간절연막을 형성하는 공정과, Forming a first interlayer insulating film on a semiconductor substrate having a predetermined lower structure;
상기 제1층간절연막 상에 WSix층 패턴을 형성하는 공정과, Forming a WSix layer pattern on the first interlayer insulating film;
상기 구조의 전표면에 제2층간절연막을 형성하는 공정과, Forming a second interlayer insulating film on the entire surface of the structure;
상기 WSix층 패턴에서 콘택으로 예정되어 있는 부분상의 제2층간절연막을 제거하여 콘택홀을 형성하는 공정과, Forming a contact hole by removing a second interlayer insulating film on a portion of the WSix layer pattern, which is intended to be a contact;
상기 노출되어있는 WSix층에 불순물을 이온주입하여 비정질층을 형성하는 공정과, Ion implanting impurities into the exposed WSix layer to form an amorphous layer,
상기 구조의 전표면에 Ti층과 TiN층 및 W층을 순차적으로 형성하는 공정과, Sequentially forming a Ti layer, a TiN layer, and a W layer on the entire surface of the structure;
상기 구조의 반도체기판을 열처리하여 Ti 실리사이드층을 형성하는 공정을 구비함에 있다. And a step of forming a Ti silicide layer by heat-treating the semiconductor substrate having the above structure.
또한 본 발명의 다른 특징은, 상기 불순물이온은 B 또는 As인 것을 특징으로 한다. In addition, another feature of the present invention is characterized in that the impurity ion is B or As.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세히 설명하기로 한다. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 WSix층에서 W-Si의 상태를 도시한 개략도로서, WSix층에 B이나 As 등의 불순물을 이온주입하면, 불순물과의 충돌에 의해 W-Si의 결합이 떨어지거나, 구조적인 찌그러짐에 의해 결합력이 약해지는 부분이 생기게 되어, 비정질층이 형성되며, 이는 FIG. 2 is a schematic view showing the state of W-Si in the WSix layer. When an ion such as B or As is ion-implanted into the WSix layer, the W-Si bond is dropped or structural crushed due to collision with impurities. This results in a weakening of the bonding force, forming an amorphous layer, which
WSix + B(불순물이온) => WSix + WB + Si + B WSix + B (Impurity) => WSix + WB + Si + B
로 표시할 수 있다. Can be displayed as
도 3a 및 도 3b는 본 발명에 따른 반도체소자의 제조 공정도이다. 3A and 3B are process charts for manufacturing a semiconductor device according to the present invention.
먼저, 도시되어 있지는 않으나, 반도체기판상에 소정의 하부 구조물 예를 들어, 소자분리 산화막과 워드라인과 랜딩플러그 및 비트라인 등을 순차적으로 형성하고, 상기 구조의 전표면에 제1층간절연막(30)을 도포한다. First, although not shown, a predetermined lower structure, for example, a device isolation oxide film, a word line, a landing plug, a bit line, and the like are sequentially formed on a semiconductor substrate, and the first
그다음 상기 제1층간절연막(30)상에 하부 금속배선, 예를 들어 상부 게이트인 WSix층(32) 패턴을 형성하고, 상기 구조의 전표면에 제2층간절연막(34)을 형성한 후, 상기 WSix층(32)에서 상부 금속배선과의 콘택으로 예정되어 있는 부분상의 제2층간절연막(34)을 콘택 마스크를 이용한 사진식각 공정을 상기 WSix층(32) 패턴을 노출시키는 콘택홀을 형성한다. After that, a lower metal wiring, for example, a
그 후, 상기 노출되어 있는 WSix층(32) 패턴 상에 B 또는 As등의 불순물 이온을 이온주입하여 비정질층(35)을 형성한다. (도 3a 참조).Thereafter, the
그다음 상기 구조의 전표면에 장벽금속층인 Ti층(36)과 TiN층(38)을 형성하고, 상기 TiN층(38)상에 상부 금속배선인 W층(20)을 형성한 후, 열처리하면, 비정질층에서 충분한 Si을 제공하므로, Ti층(36) 증착시의 온도와 열처리 온도에 의해 Then, the Ti layer 36 and the
Ti + Si (이온주입으로 생긴 것) + WSix => TiSi2 + WSix Ti + Si (from ion implantation) + WSix => TiSi2 + WSix
반응이 원활하게 일어나, WSix층(12)의 Si과 Ti층(16)의 Ti가 반응하여 Ti 실리사이드층(42)을 형성시켜 콘택 저항을 감소시킨다. (도 3b 참조). The reaction occurs smoothly, and Si in the WSix
도 4는 종래 기술과 본 발명에 따른 콘택 저항을 비교한 그래프로서, 콘택 저항이 40% 감소되는 것을 볼 수 있으며, 따라서 콘택 크기를 40% 감소시킬 수 있다.
Figure 4 is a graph comparing the contact resistance according to the prior art and the present invention, it can be seen that the contact resistance is reduced by 40%, and thus the contact size can be reduced by 40%.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은 상부 게이트로 쓰이는 WSix층과 상부 배선과의 콘택 공정시 장벽금속층의 Ti가 원활하게 Si과 결합될 수 있도록 콘택 부위의 WSix상에 불순물을 이온주입하여 비정질층을 형성하고, 후속 공정을 진행하여 WSix층과 Ti층의 계면에 Ti가 남지 않도록 하였으므로, 콘택 저항이 감소되어 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있으며, 고집적 소자의 제조가 유리해지는 등의 이점이 있다. As described above, in the method of manufacturing a semiconductor device according to the present invention, impurity is formed on the WSix of the contact portion so that Ti of the barrier metal layer can be smoothly combined with Si during the contact process between the WSix layer used as the upper gate and the upper wiring. Ion-implanted to form an amorphous layer, and the subsequent process was performed so that no Ti remained at the interface between the WSix layer and the Ti layer. Therefore, contact resistance is reduced, thereby improving process yield and device operation reliability. There is such an advantage that manufacturing is advantageous.
Claims (2)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080062725A (en) * | 2006-12-29 | 2008-07-03 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device having low contact resistance |
| US10366918B2 (en) | 2016-10-04 | 2019-07-30 | International Business Machines Corporation | Self-aligned trench metal-alloying for III-V nFETs |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080062725A (en) * | 2006-12-29 | 2008-07-03 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device having low contact resistance |
| US10366918B2 (en) | 2016-10-04 | 2019-07-30 | International Business Machines Corporation | Self-aligned trench metal-alloying for III-V nFETs |
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