KR20080062725A - Method of fabricating semiconductor device having low contact resistance - Google Patents

Method of fabricating semiconductor device having low contact resistance Download PDF

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KR20080062725A
KR20080062725A KR1020060138807A KR20060138807A KR20080062725A KR 20080062725 A KR20080062725 A KR 20080062725A KR 1020060138807 A KR1020060138807 A KR 1020060138807A KR 20060138807 A KR20060138807 A KR 20060138807A KR 20080062725 A KR20080062725 A KR 20080062725A
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conductive layer
forming
impurity
semiconductor device
impurity region
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KR1020060138807A
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Korean (ko)
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김동석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

A method for manufacturing a semiconductor device having a low contact resistance is provided to reduce a contact resistance of a contact plug by forming a resistance reduction region at a boundary between the first conductive layer and the impurity region. Gate stacks(120) being separated from each other are formed on a substrate(100). An impurity region is formed in the substrate between the gate stacks. A first conductive layer(151) is formed to cover the impurity region and the gate stacks. An ion implantation process for reducing a contact resistance is performed to form an impurity resistance reduction region(160) at a boundary between the first conductive layer and the impurity region. A contact plug(150) is formed between the gate stacks. A thickness of the first conductive layer is 100 Å to 500 Å. The first conductive layer is formed with an n-type impurity doped poly silicon layer. The ion implantation process for reducing a contact resistance is performed by implanting phosphorous ion.

Description

낮은 컨택 저항을 갖는 반도체소자의 제조방법{Method of fabricating semiconductor device having low contact resistance}Method of fabricating semiconductor device having low contact resistance

도 1 내지 도 5는 본 발명에 따른 낮은 컨택 저항을 갖는 반도체소자의 제조방법을 설명하기 위하여 나타내 보인 단면도들이다.1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a low contact resistance according to the present invention.

본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 낮은 컨택 저항을 갖는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a low contact resistance.

반도체소자의 집적도가 증가함에 따라, 트랜지스터와 커패시터로 구성되는 디램(DRAM; Dynamic Random Access Memory) 소자의 경우, 반도체기판의 소스/드레인영역과 같은 불순물영역과 비트라인 사이의 전기적 연결, 그리고 불순물영역과 스토리지노드 사이의 전기적 연결을 위해 컨택플러그(contact plug)를 이용하고 있다. 즉 게이트스택으로 이루어지는 워드라인 사이의 공간 중에서 반도체기판의 불순물영역과 접하는 공간에 도전막을 채워 컨택플러그를 형성하고, 후속 공정에서 비트라인컨택 및 스토리지노드컨택을 이 랜딩플러그컨택에 연결되도록 형성한다.As the degree of integration of semiconductor devices increases, in the case of dynamic random access memory (DRAM) devices consisting of transistors and capacitors, an electrical connection between an impurity region and a bit line, such as a source / drain region of a semiconductor substrate, and an impurity region Contact plugs are used to make electrical connections between the storage node and the storage node. That is, a contact plug is formed by filling a conductive film in a space between the word lines formed of a gate stack and a contact with an impurity region of a semiconductor substrate, and a bit line contact and a storage node contact are formed to be connected to the landing plug contact in a subsequent process.

그런데 최근 디자인 룰(design rule)의 축소가 더욱 더 요구됨에 따라, 워드 라인 사이의 폭도 점점 더 좁아지고 있다. 이에 따라 워드라인 사이의 컨택플러그의 면적 또한 작아지고 있으며, 그 결과 작아지는 면적에 비례하여 컨택 저항이 증가하고 있다. 이와 같은 컨택 저항의 증가는 전류량의 여유 부족에 의한 리프레시(refresh)성 오동작을 유발하는 원인으로 작용하여 소자의 신뢰성을 저하시킨다.However, in recent years, as the reduction of design rules is increasingly demanded, the widths between word lines are becoming narrower. As a result, the area of the contact plug between the word lines is also reduced, and as a result, the contact resistance is increased in proportion to the area being smaller. Such an increase in contact resistance acts as a cause of refreshing malfunction due to lack of a sufficient amount of current, thereby lowering the reliability of the device.

컨택 저항의 증가를 억제하기 위해서는, 불순물영역의 농도를 더 증가시켜야 한다. 그러나 불순물영역의 농도 증가는 불순물영역의 접합에 인가되는 전계(electric field)를 증가시켜 핫 캐리어 열화(hot carrier degradation)를 증대시키고, 리프레시를 감소시켜 소자의 동작 특성과 신뢰성을 저하시킨다.In order to suppress the increase in contact resistance, the concentration of the impurity region must be further increased. However, increasing the concentration of the impurity region increases the electric field applied to the junction of the impurity region, thereby increasing hot carrier degradation and reducing refresh, thereby degrading the operation characteristics and reliability of the device.

본 발명이 이루고자 하는 기술적 과제는, 불순물영역의 접합에 인가되는 전계의 증가 없이 낮은 컨택 저항을 갖도록 하는 반도체소자의 제조방법을 제공하는 것이다.An object of the present invention is to provide a method of manufacturing a semiconductor device having a low contact resistance without increasing the electric field applied to the junction of the impurity region.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 낮은 컨택 저항을 갖는 반도체소자의 제조방법은, 기판 위에 상호 이격된 게이트스택들을 형성하는 단계; 게이트스택들 사이의 기판 내에 불순물영역을 형성하는 단계; 상기 불순물영역 및 게이트스택들을 덮는 제1 도전막을 형성하는 단계; 컨택저항 감소를 위한 이온주입을 수행하여 상기 제1 도전막과 불순물영역의 경계부분에 불순물 저항감소영역을 형성하는 단계; 및 상기 게이트스택들 사이에 컨택 플러그를 형성하는 단계를 포함한다.In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a low contact resistance according to the present invention, forming a gate stack spaced apart from each other on the substrate; Forming an impurity region in the substrate between the gate stacks; Forming a first conductive layer covering the impurity region and the gate stack; Forming an impurity resistance reducing region at an interface between the first conductive layer and the impurity region by performing ion implantation to reduce contact resistance; And forming a contact plug between the gate stacks.

상기 제1 도전막은 100Å 내지 500Å의 두께로 형성하는 것이 바람직하다.The first conductive film is preferably formed to a thickness of 100 kPa to 500 kPa.

상기 제1 도전막은 n형 불순물이 도핑된 폴리실리콘막으로 형성할 수 있다. 상기 n형 불순물은 포스포러스(P)이고, 도핑농도는 2.0×1020/㎤ 내지 7.0×1020/㎤인 것이 바람직하다.The first conductive layer may be formed of a polysilicon layer doped with n-type impurities. The n-type impurity is preferably a phosphorus (P), and the doping concentration is 2.0 × 10 20 / ㎤ to 7.0 × 10 20 / ㎤.

상기 컨택저항 감소를 위한 이온주입은, 5KeV 내지 50KeV의 주입에너지로 상기 불순물 저항감소영역이 상기 제1 도전막과 불순물영역의 경계부분에 형성되도록 하는 이온주입 조건하에서 수행되는 것이 바람직하다.The ion implantation for reducing the contact resistance is preferably performed under an ion implantation condition such that the impurity resistance reduction region is formed at the boundary between the first conductive layer and the impurity region with an implantation energy of 5 KeV to 50 KeV.

상기 컨택저항 감소를 위한 이온주입은 포스포러스 이온을 주입하여 수행할 수 있다.Ion implantation for reducing the contact resistance may be performed by implanting phosphorus ions.

상기 컨택 플러그를 형성하는 단계는, 상기 제1 도전막 위에 제2 도전막을 형성하는 단계와, 그리고 상기 게이트스택 상부면이 노출되도록 상기 제2 도전막을 평탄화시켜 상기 제1 도전막 및 제2 도전막으로 이루어진 컨택 플러그를 형성하는 단계를 포함할 수 있다. 상기 제2 도전막은 1000Å 내지 2000Å의 두께로 형성하는 것이 바람직하다. 상기 제2 도전막은 n형 불순물이 도핑된 폴리실리콘막으로 형성할 수 있다. 상기 n형 불순물은 포스포러스(P)이고, 도핑농도는 2.0×1020/㎤ 내지 7.0×1020/㎤인 것이 바람직하다.The forming of the contact plug may include forming a second conductive layer on the first conductive layer, and planarizing the second conductive layer to expose the upper surface of the gate stack, thereby forming the first conductive layer and the second conductive layer. It may include forming a contact plug consisting of. The second conductive film is preferably formed to a thickness of 1000 kPa to 2000 kPa. The second conductive layer may be formed of a polysilicon layer doped with n-type impurities. The n-type impurity is preferably a phosphorus (P), and the doping concentration is 2.0 × 10 20 / ㎤ to 7.0 × 10 20 / ㎤.

상기 제1 도전막을 형성하기 전에 상기 불순물영역의 상부에 대해 전계완화를 위한 이온주입을 수행하는 단계를 더 포함할 수 있다.The method may further include performing ion implantation for electric field relaxation on the impurity region before forming the first conductive layer.

이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

도 1 내지 도 5는 본 발명에 따른 낮은 컨택 저항을 갖는 반도체소자의 제조방법을 설명하기 위하여 나타내 보인 단면도들이다.1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a low contact resistance according to the present invention.

도 1을 참조하면, 소자분리막(110)에 의해 한정되는 액티브영역을 갖는 기판(100) 위에 게이트스택(120)을 형성한다. 기판(100)은 실리콘기판이지만 이에 한정되는 것은 아니다. 게이트스택(120)은 게이트절연막패턴(121), 게이트전극막패턴(122) 및 게이트하드마스크막패턴(123)이 순차적으로 적층되는 구조로 형성한다. 게이트절연막패턴(121)은 산화막으로 형성한다. 게이트전극막패턴(122)은 폴리실리콘막으로 형성한다. 그리고 게이트하드마스크막패턴(123)은 질화막으로 형성한다.Referring to FIG. 1, a gate stack 120 is formed on a substrate 100 having an active region defined by an isolation layer 110. The substrate 100 is a silicon substrate, but is not limited thereto. The gate stack 120 has a structure in which the gate insulating film pattern 121, the gate electrode film pattern 122, and the gate hard mask film pattern 123 are sequentially stacked. The gate insulating film pattern 121 is formed of an oxide film. The gate electrode film pattern 122 is formed of a polysilicon film. The gate hard mask film pattern 123 is formed of a nitride film.

도 2를 참조하면, 게이트스택(120) 측벽에 게이트스페이서막(130)을 형성한다. 이를 위하여 먼저 전면에 게이트스페이서용 절연막(미도시)을 증착한다. 게이트스페이서용 절연막은 질화막으로 형성한다. 다음에 전면에 이방성식각, 예컨대 에치백(etch back)을 수행하여 게이트스택(120) 상부 및 기판(100) 상부의 게??스페이서용 절연막은 제거되도록 하고, 게이트스택(120) 측벽에만 게이트스페이서용 절연막이 남도록 한다.Referring to FIG. 2, a gate spacer layer 130 is formed on sidewalls of the gate stack 120. To this end, an insulating film for a gate spacer (not shown) is first deposited on the entire surface. The gate spacer insulating film is formed of a nitride film. Next, anisotropic etching (eg, etch back) is performed on the entire surface so that the insulating film for the spacers on the gate stack 120 and the substrate 100 is removed, and the gate spacer only on the sidewalls of the gate stack 120. The insulating film is left.

다음에, 도면에 나타내지는 않았지만, 불순물 이온주입공정을 수행하여 기판(100)의 활성영역 내에 소스/드레인영역과 같은 불순물영역(미도시)을 형성한다. 경우에 따라서는 LDD(Lightly Doped Drain) 구조로 상기 불순물영역을 형성할 수도 있는데, 이 경우에는 게이트스페이서막(130)을 형성하기 전에 얕은 소스/드레인 연장영역(source/drain extension region)을 먼저 형성하고, 이어서 게이트스페이서막(130)을 형성한 후에 딥 소스/드레인영역(deep source/drain region)을 형성한다.Next, although not shown, an impurity ion implantation process is performed to form an impurity region (not shown) such as a source / drain region in the active region of the substrate 100. In some cases, the impurity region may be formed by a lightly doped drain (LDD) structure. In this case, a shallow source / drain extension region is first formed before the gate spacer layer 130 is formed. Subsequently, a deep source / drain region is formed after the gate spacer layer 130 is formed.

소스/드레인영역을 형성한 후에는, 도면에서 화살표로 나타낸 바와 같이, 불순물영역 접합에서의 전계 감소를 위한 이온주입을 수행한다. 이 이온주입은, n형인 PH3 가스를 소스로 사용하여 n형 불순물이온인 포스포러스(P)를 빔라인(beamline) 형태로 주입함으로써 수행된다. 이때 에너지는 불순물영역 접합에서의 전계가 충분히 감소할 정도가 되어야 하는데, 대략 10KeV 내지 100KeV가 되도록 한다. 도핑 농도는 대략 1.0×1012/㎠ 내지 1.0×1014/㎠가 되도록 한다. 상기 이온주입은 싱글타입(single type) 장비에서 수행될 수도 있고, 또는 대략 9장 내지 13장 웨이퍼 단위의 세미-배치타입(semi-batch type) 장비에서 수행될 수도 있다.After the source / drain regions are formed, ion implantation is performed to reduce the electric field at the impurity region junction, as indicated by the arrows in the figure. This ion implantation is performed by injecting phosphorus P, which is an n-type impurity ion, in the form of a beamline, using an n-type PH 3 gas as a source. At this time, the energy should be such that the electric field at the impurity region junction is sufficiently reduced to be approximately 10 KeV to 100 KeV. The doping concentration is about 1.0 × 10 12 / cm 2 to 1.0 × 10 14 / cm 2. The ion implantation may be performed in a single type device, or may be performed in a semi-batch type device of approximately 9 to 13 wafer units.

도 3을 참조하면, 게이트스택(120), 게이트스페이서막(130) 및 불순물영역의 표면 위에 제1 도전막(151)을 형성한다. 이를 위해, 제1 도전막(151) 형성전에 절연막을 형성하고, 절연막의 일부를 제거하여 불순물영역 표면을 노출시키는 컨택을 형성한다. 제1 도전막(151)은 후속의 이온주입깊이를 조절하기 위한 막으로서, 불순물이 도핑된 폴리실리콘막으로 형성한다. 불순물로는, n형 불순물, 예컨대 포스포러스(P)를 사용하고, 그 도핑농도는 대략 2.0×1020/㎤ 내지 7.0×1020/㎤가 되도록 한다. 그리고 증착온도는 대략 450℃ 내지 700℃가 되도록 한다. 제1 도전 막(151)의 두께는 후속의 이온주입깊이를 조절할 정도면 되므로, 대략 100Å 내지 500Å의 두께가 되도록 한다. 제1 도전막(151)의 증착은 매엽식 장비 또는 퍼니스(furnace) 형태의 장비를 사용하여 수행할 수 있다.Referring to FIG. 3, a first conductive layer 151 is formed on the surfaces of the gate stack 120, the gate spacer layer 130, and the impurity region. To this end, an insulating film is formed before the first conductive film 151 is formed, and a portion of the insulating film is removed to form a contact exposing the impurity region surface. The first conductive film 151 is a film for controlling subsequent ion implantation depth, and is formed of a polysilicon film doped with impurities. As the impurity, an n-type impurity such as phosphorus (P) is used, and its doping concentration is set to be approximately 2.0 × 10 20 / cm 3 to 7.0 × 10 20 / cm 3. And the deposition temperature is to be approximately 450 ℃ to 700 ℃. Since the thickness of the first conductive film 151 is enough to control the subsequent ion implantation depth, the thickness of the first conductive film 151 is approximately 100 kPa to 500 kPa. Deposition of the first conductive layer 151 may be performed by using a sheet-type equipment or equipment in the form of a furnace (furnace).

제1 도전막(151)을 형성한 후에는, 도면에서 화살표로 나타낸 바와 같이, 컨택저항 감소를 위한 이온주입을 수행한다. 주입되는 이온으로는 포스포러스(P) 이온을 사용한다. 이 이온주입시 여러 조건, 특히 이온주입깊이에 대한 조건은, 주입되는 이온이 제1 도전막(151)과 불순물영역의 경계부분에 집중되어, 그 경계부분에 포스포러스(P) 이온에 의한 불순물 저항감소영역(160)이 만들어지도록 조절한다. 이온주입 에너지는 대략 5KeV 내지 50KeV가 되도록 하고, 도핑 농도는 대략 1.0×1013/㎠ 내지 1.0×1014/㎠가 되도록 한다. 상기 이온주입도 싱글타입 장비에서 수행될 수도 있고, 또는 대략 9장 내지 13장 웨이퍼 단위의 세미-배치타입 장비에서 수행될 수도 있다.After the first conductive layer 151 is formed, ion implantation is performed to reduce contact resistance, as indicated by arrows in the figure. Phosphorus (P) ions are used as implanted ions. In the ion implantation, various conditions, in particular, conditions for the ion implantation depth, include implanted ions concentrated at the boundary between the first conductive film 151 and the impurity region, and impurities caused by phosphorus (P) ions at the boundary portion. The resistance reduction area 160 is adjusted to be made. The ion implantation energy is about 5KeV to 50KeV, and the doping concentration is about 1.0 × 10 13 / cm 2 to 1.0 × 10 14 / cm 2. The ion implantation may be performed in a single type device, or may be performed in a semi-batch type device of approximately 9 to 13 wafer units.

도 4를 참조하면, 제1 도전막(151) 위에 제2 도전막(152)을 형성한다. 제2 도전막(152)은 제1 도전막(151)과 함께 컨택 플러그를 형성하는 물질막으로서, 대략 1000Å 내지 2000Å 두께의 불순물이 도핑된 폴리실리콘막으로 형성한다. 도핑된 불순물은 포스포러스(P)이며, 포스포러스(P)의 도핑농도는 대략 2.0×1020/㎠ 내지 7.0×1020/㎠가 되도록 한다. 제2 도전막(152)의 증착도, 제1 도전막(151)과 마찬가지로 매엽식 장비 또는 퍼니스(furnace) 형태의 장비를 사용하여 수행할 수 있다.Referring to FIG. 4, a second conductive film 152 is formed on the first conductive film 151. The second conductive layer 152 is a material layer forming a contact plug together with the first conductive layer 151 and is formed of a polysilicon layer doped with impurities having a thickness of about 1000 GPa to 2000 GPa. The doped impurity is phosphorus (P), and the doping concentration of the phosphorus (P) is about 2.0 × 10 20 / cm 2 to 7.0 × 10 20 / cm 2. The deposition of the second conductive film 152 may also be performed by using a sheet type equipment or a furnace type equipment similar to the first conductive film 151.

도 5를 참조하면, 게이트스택(120) 상부면, 즉 게이트 하드마스크막(123) 상부가 제2 도전막(152) 및 제1 도전막(151)을 평탄화시켜, 게이트스택(120) 사이를 채우는 제1 도전막(151) 및 제2 도전막(152)으로 이루어지는 컨택 플러그(150)를 형성한다. 상기 평탄화를 위해 화학적기계적폴리싱(CMP; Chemical Mechanical Polishing) 방법을 사용할 수 있으며, 또는 에치백을 사용할 수도 있다. 최종적으로 형성된 컨택 플러그(150)는 불순물영역과 불순물 저항감소영역(160)을 통해 컨택되며, 불순물 저항감소영역(160)을 구성하는 불순물에 의해 컨택 플러그(150)의 컨택저항은 감소된다.Referring to FIG. 5, the upper surface of the gate stack 120, that is, the upper portion of the gate hard mask layer 123, may planarize the second conductive layer 152 and the first conductive layer 151, and may be disposed between the gate stacks 120. The contact plug 150 including the filling first conductive film 151 and the second conductive film 152 is formed. The chemical mechanical polishing (CMP) method may be used for the planarization, or an etch back may be used. The finally formed contact plug 150 is contacted through the impurity region and the impurity resistance reduction region 160, and the contact resistance of the contact plug 150 is reduced by the impurities constituting the impurity resistance reduction region 160.

지금까지 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법에 의하면, 컨택이 형성될 기판 표면에 컨택저항 감소를 위한 불순물 저항감소영역을 형성함으로써 컨택플러그의 컨택저항을 감소시킬 수 있으며, 특히 이온주입조건을 조절하여 불순물 저항감소영역의 위치를 소스/드레인영역의 표면에 위치시킴으로써, 유효-셀 채널 길이의 감소에 따른 셀 문턱전압 특성의 저하을 방지할 수 있는 동시에, 기판의 누설전류로 감소시킬 수 있다는 이점이 제공된다.As described above, according to the method of manufacturing a semiconductor device according to the present invention, the contact resistance of the contact plug can be reduced by forming an impurity resistance reduction region for reducing the contact resistance on the surface of the substrate on which the contact is to be formed. By adjusting the implantation conditions, the position of the impurity resistance reduction region is placed on the surface of the source / drain region, thereby reducing the cell threshold voltage characteristic caused by the reduction of the effective-cell channel length, and reducing the leakage current of the substrate. The advantage is that it can.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (11)

기판 위에 상호 이격된 게이트스택들을 형성하는 단계;Forming gate stacks spaced apart from each other on the substrate; 게이트스택들 사이의 기판 내에 불순물영역을 형성하는 단계;Forming an impurity region in the substrate between the gate stacks; 상기 불순물영역 및 게이트스택들을 덮는 제1 도전막을 형성하는 단계;Forming a first conductive layer covering the impurity region and the gate stack; 컨택저항 감소를 위한 이온주입을 수행하여 상기 제1 도전막과 불순물영역의 경계부분에 불순물 저항감소영역을 형성하는 단계; 및Forming an impurity resistance reducing region at an interface between the first conductive layer and the impurity region by performing ion implantation to reduce contact resistance; And 상기 게이트스택들 사이에 컨택 플러그를 형성하는 단계를 포함하는 반도체소자의 제조방법.Forming a contact plug between the gate stacks. 제1항에 있어서,The method of claim 1, 상기 제1 도전막은 100Å 내지 500Å의 두께로 형성하는 반도체소자의 제조방법.The first conductive film is a manufacturing method of a semiconductor device to form a thickness of 100 ~ 500Å. 제1항에 있어서,The method of claim 1, 상기 제1 도전막은 n형 불순물이 도핑된 폴리실리콘막으로 형성하는 반도체소자의 제조방법.And the first conductive film is formed of a polysilicon film doped with n-type impurities. 제3항에 있어서,The method of claim 3, 상기 n형 불순물은 포스포러스(P)이고, 도핑농도는 2.0×1020/㎤ 내지 7.0×1020/㎤인 반도체소자의 제조방법.The n-type impurity is phosphorus (P), the doping concentration is 2.0 × 10 20 / cm 3 To 7.0 × 10 20 / cm 3 A manufacturing method of a semiconductor device. 제1항에 있어서,The method of claim 1, 상기 컨택저항 감소를 위한 이온주입은, 5KeV 내지 50KeV의 주입에너지로 상기 불순물 저항감소영역이 상기 제1 도전막과 불순물영역의 경계부분에 형성되도록 하는 이온주입 조건하에서 수행되는 반도체소자의 제조방법.The ion implantation for reducing the contact resistance is a semiconductor device manufacturing method is carried out under the ion implantation conditions such that the impurity resistance reduction region is formed at the boundary between the first conductive film and the impurity region with an implantation energy of 5KeV to 50KeV. 제1항에 있어서,The method of claim 1, 상기 컨택저항 감소를 위한 이온주입은 포스포러스 이온을 주입하여 수행하는 반도체소자의 제조방법.The implantation method for reducing the contact resistance is performed by implanting phosphorus ions. 제1항에 있어서, 상기 컨택 플러그를 형성하는 단계는,The method of claim 1, wherein the forming of the contact plug comprises: 상기 제1 도전막 위에 제2 도전막을 형성하는 단계; 및Forming a second conductive film on the first conductive film; And 상기 게이트스택 상부면이 노출되도록 상기 제2 도전막을 평탄화시켜 상기 제1 도전막 및 제2 도전막으로 이루어진 컨택 플러그를 형성하는 단계를 포함하는 반도체소자의 제조방법.And planarizing the second conductive layer to expose the upper surface of the gate stack, thereby forming a contact plug formed of the first conductive layer and the second conductive layer. 제7항에 있어서,The method of claim 7, wherein 상기 제2 도전막은 1000Å 내지 2000Å의 두께로 형성하는 반도체소자의 제조방법.The second conductive film is a manufacturing method of a semiconductor device to form a thickness of 1000 ~ 2000Å. 제7항에 있어서,The method of claim 7, wherein 상기 제2 도전막은 n형 불순물이 도핑된 폴리실리콘막으로 형성하는 반도체소자의 제조방법.And the second conductive film is formed of a polysilicon film doped with n-type impurities. 제9항에 있어서,The method of claim 9, 상기 n형 불순물은 포스포러스(P)이고, 도핑농도는 2.0×1020/㎤ 내지 7.0×1020/㎤인 반도체소자의 제조방법.The n-type impurity is phosphorus (P), the doping concentration is 2.0 × 10 20 / cm 3 To 7.0 × 10 20 / cm 3 A manufacturing method of a semiconductor device. 제1항에 있어서,The method of claim 1, 상기 제1 도전막을 형성하기 전에 상기 불순물영역의 상부에 대해 전계완화를 위한 이온주입을 수행하는 단계를 더 포함하는 반도체소자의 제조방법.And performing ion implantation for electric field relaxation on the upper portion of the impurity region before forming the first conductive layer.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000020742A (en) * 1998-09-23 2000-04-15 윤종용 Method for improving contact resistor of semiconductor device
KR20010004991A (en) * 1999-06-30 2001-01-15 김영환 Method of forming a cell contact in a flash EEPROM cell
KR20050114989A (en) * 2004-06-02 2005-12-07 주식회사 하이닉스반도체 Method for forming the mos transistor of semiconductor device
KR20060075045A (en) * 2004-12-28 2006-07-04 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000020742A (en) * 1998-09-23 2000-04-15 윤종용 Method for improving contact resistor of semiconductor device
KR20010004991A (en) * 1999-06-30 2001-01-15 김영환 Method of forming a cell contact in a flash EEPROM cell
KR20050114989A (en) * 2004-06-02 2005-12-07 주식회사 하이닉스반도체 Method for forming the mos transistor of semiconductor device
KR20060075045A (en) * 2004-12-28 2006-07-04 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

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