KR20030002840A - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
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- KR20030002840A KR20030002840A KR1020010038562A KR20010038562A KR20030002840A KR 20030002840 A KR20030002840 A KR 20030002840A KR 1020010038562 A KR1020010038562 A KR 1020010038562A KR 20010038562 A KR20010038562 A KR 20010038562A KR 20030002840 A KR20030002840 A KR 20030002840A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 소자분리막의 절연 특성을 향상시키고 소오스/ 드레인 전계를 감소하여 셀 트랜지스터의 전기적 특성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving electrical characteristics of a cell transistor by improving insulation characteristics of a device isolation layer and reducing a source / drain electric field.
반도체 장치의 고집적화 됨에 따라 메모리 셀 크기가 점점 감소되면서 워드 라인 또는 비트라인 사이의 콘택 마진이 점차 작아지고 있다. 이에 따라, 콘택 마진을 높이기 위한 방안으로서, 널리 알려진 자기정렬 콘택(self-aligned contact: 이하 SAC라 함) 제조 기술이 있다. 이는 주변구조물의 단차를 이용하여 콘택홀을 형성하는 것으로, 주변구조물의 높이, 콘택홀이 형성될 절연물질의 두께 및 식각방법 등에 의해 다양한 크기의 콘택홀을 마스크 사용없이 얻을 수 있기 때문에 고집적화에 의해 미세화되는 반도체장치의 실현에 적합한 방법이다.As the semiconductor devices are highly integrated, as the memory cell size is gradually reduced, the contact margin between word lines or bit lines is gradually decreasing. Accordingly, as a method for increasing the contact margin, there is a well-known self-aligned contact (hereinafter referred to as SAC) manufacturing technology. This is to form a contact hole by using the step of the peripheral structure, because the contact hole of various sizes can be obtained without using a mask by the height of the peripheral structure, the thickness of the insulating material to be formed and the etching method, etc. It is a method suitable for realizing a semiconductor device to be miniaturized.
도 1은 일반적인 메모리 셀 어레이 구조를 나타낸 레이아웃도이다. 도 2a 및 도 2b는 종래 기술에 의한 SAC 공정으로 제조된 트랜지스터의 수직 단면도로서, 각각 도 1의 C 라인 및 D 라인으로 절단한 수직 단면도들이다.1 is a layout diagram illustrating a general memory cell array structure. 2A and 2B are vertical cross-sectional views of transistors manufactured by the SAC process according to the prior art, and are vertical cross-sectional views cut along lines C and D of FIG. 1, respectively.
이들 도면을 참조하면, 종래 기술에 의한 SAC 콘택 제조 공정은 다음과 같다.Referring to these drawings, the SAC contact manufacturing process according to the prior art is as follows.
우선, 반도체 기판(10)에 소자분리막(12)을 형성하고, 기판 상부에 게이트 산화막(22)과, 도프트 폴리실리콘(24)과, 텅스텐실리사이드층(26) 및 하드마스크(28)를 적층하고 이들을 패터닝한 후에 이들 패턴의 측벽에 스페이서(29)를 형성하여 워드 라인(20)을 형성한다.First, the device isolation film 12 is formed on the semiconductor substrate 10, and the gate oxide film 22, the doped polysilicon 24, the tungsten silicide layer 26, and the hard mask 28 are stacked on the substrate. After patterning them, spacers 29 are formed on the sidewalls of these patterns to form word lines 20.
워드 라인(20)이 형성된 결과물 전면에 절연막을 증착하고 전면 식각하여 워드 라인(20) 사이의 공간에 SAC 콘택홀(미도시함)을 형성한다. 그리고 SAC 콘택홀에 도전체 물질로서 도프트 폴리실리콘을 매립하고 CMP(Chemical Mechanical Polishing)을 진행하여 워드 라인 사이에 분리되면서 소오스/드레인 영역(미도시함)과 연결되는 콘택 플러그(30)를 형성한다.An insulating film is deposited on the entire surface of the resultant word line 20 and etched to form an SAC contact hole (not shown) in the space between the word lines 20. In addition, a dopant polysilicon is embedded in the SAC contact hole as a conductive material and chemical mechanical polishing (CMP) is performed to form a contact plug 30 connected to a source / drain region (not shown) while being separated between word lines. do.
그러나, 종래 기술에 의한 트랜지스터 제조 방법에 있어서, SAC 식각 공정시 콘택 플러그의 미스-얼라인이 발생할 경우 SAC 불량(도면부호 a)의 발생이 높다. 그리고, 고집적화 트랜지스터의 채널 감소에 의해 펀치쓰루 방지용 이온 농도가 증가하게 되고 이로 인해 소오스/드레인 영역의 전계가 증가(도면부호 b)하게 되어 셀 트랜지스터의 리프레시 특성이 감소하게 된다.However, in the transistor manufacturing method according to the prior art, the occurrence of the SAC defect (reference numeral a) is high when the mis-alignment of the contact plug occurs during the SAC etching process. As the channel of the highly integrated transistor decreases, the punch-through prevention ion concentration increases, thereby increasing the electric field of the source / drain regions (reference numeral b), thereby reducing the refresh characteristics of the cell transistor.
또한, 종래 기술에서는 칩 사이즈 감소에 의해 충분한 영역의 STI 소자분리막을 확보할 수 없으며 이로 인해 소자분리막 상부의 워드 라인과 고농도의 소오스/드레인 영역 사이에서 접합 커패시턴스가 증가하게 되는 문제가 있었다.In addition, in the related art, it is not possible to secure a sufficient area of the STI device isolation layer by reducing the chip size, which causes a problem in that the junction capacitance between the word line and the high concentration source / drain region on the device isolation layer increases.
또한, 종래에는 워드라인 또는 비트 라인 사이의 공간이 축소되기 때문에 상기 워드 라인과 콘택 플러그 사이가 얇은 스페이서에 의해 절연되기 때문에 커플링 커패시턴스가 발생하게 되고, 이로 인해 워드라인으로부터 비트라인에 유입되는 커플링 노이즈 문제와 비선택된 워드라인의 전압이 변화하는 등 트랜지스터가 불안정하게 동작하게 된다.In addition, since the space between the word line or the bit line is conventionally reduced, the coupling capacitance is generated because the space between the word line and the contact plug is insulated by a thin spacer, which causes the couple to enter the bit line from the word line. Transistors become unstable, such as ring noise problems and variations in the voltage of unselected word lines.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 STI 공정 전에 플러그 영역을 선택적 에피택셜로 성장시키고 플러그를 형성함으로써 SAC 불량을 방지하면서 소오스/드레인 영역과 게이트 채널을 격리시켜 소오스/드레인 영역의 전계 감소에 의한 리프레시를 개선할 수 있고, 플러그가 형성된 구조물에 STI 공정을 실시함으로써 인접 셀 트랜지스터와의 소자분리 영역을 격층화하여 소자분리 효과를 높이고 플러그가 게이트 스페이서와 소자분리막 사이에 존재하게 되고 워드 라인을 폴리사이드 구조로 형성함으로써 커플링 커패시턴스를 낮출 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.An object of the present invention is to isolate the source / drain region and the gate channel while preventing the SAC defect by growing the plug region selectively epitaxially and forming the plug prior to the STI process to solve the problems of the prior art as described above. Refreshing by reducing the electric field of the region can be improved, and the STI process is performed on the structure in which the plug is formed to increase the device isolation effect by layering the device isolation region with adjacent cell transistors, and the plug is present between the gate spacer and the device isolation film. The present invention provides a method of manufacturing a semiconductor device capable of lowering coupling capacitance by forming a word line in a polyside structure.
도 1은 일반적인 메모리 셀 어레이 구조를 나타낸 레이아웃도,1 is a layout diagram illustrating a general memory cell array structure;
도 2a 및 도 2b는 종래 기술에 의한 SAC 공정으로 제조된 트랜지스터의 수직 단면도들,2A and 2B are vertical cross-sectional views of a transistor manufactured by the SAC process according to the prior art,
도 3 내지 도 10b는 본 발명에 따른 반도체 소자의 제조 공정을 순차적으로 나타낸 공정 순서도.3 to 10b is a process flowchart sequentially showing a manufacturing process of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100 : 반도체 기판 102 : 산화막100 semiconductor substrate 102 oxide film
104 : 문턱전압 조절 영역 106 : 게이트 산화막104: threshold voltage adjusting region 106: gate oxide film
108 : 도프트 폴리실리콘 110 : 하드 마스크108: doped polysilicon 110: hard mask
112 : 스페이서 114 : 워드 라인112: spacer 114: word line
116 : 에피층 118 : 소오스/드레인 영역116: epi layer 118: source / drain regions
120 : 플러그 122 : 절연막120: plug 122: insulating film
124 : 활성 영역 마스크 126 : STI 소자분리막124: active region mask 126: STI device isolation film
128 : 금속 또는 실리사이드막128: metal or silicide film
이러한 목적을 달성하기 위하여 본 발명의 방법은 반도체 기판 상부에 게이트 전극 및 하드 마스크를 형성하고 이들 측벽에 스페이서를 형성하는 단계와, 스페이서가 형성된 기판을 선택적 에피택셜 성장시켜 에피층을 형성시키고 에피층에 이온 주입을 하여 소오스/드레인 영역을 형성하는 단계와, 에피층이 형성된 스페이서 사이에 도전물질을 매립하고 평탄화공정으로 연마하여 플러그를 형성하는 단계와, 플러그가 형성된 결과물 상부에 절연막을 형성하는 단계와, 결과물에 활성 영역 마스크를 이용한 식각 공정을 진행하여 절연막에서부터 기판이 소정 깊이 식각된 트렌치를 형성하고 트렌치에 산화막을 매립하여 소자분리막을 형성하는 단계를 포함한다.In order to achieve the above object, the method of the present invention comprises forming a gate electrode and a hard mask on the semiconductor substrate and forming spacers on the sidewalls, and forming an epitaxial layer by selectively epitaxially growing the substrate on which the spacer is formed. Forming a source / drain region by ion implantation, filling a conductive material between the spacers on which the epi layer is formed, and polishing by a planarization process to form a plug, and forming an insulating layer on the plug formed product And forming a trench in which the substrate is etched to a predetermined depth from the insulating layer by etching the resultant using an active region mask in the resultant, and forming an isolation layer by burying an oxide film in the trench.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 3 내지 도 10b는 본 발명에 따른 반도체 소자의 제조 공정을 순차적으로 나타낸 공정 순서도이다. 이들 도면을 참조하면, 본 발명의 제조 방법은 다음과 같다.3 to 10b are process flowcharts sequentially illustrating a manufacturing process of a semiconductor device according to the present invention. Referring to these drawings, the production method of the present invention is as follows.
도 3 및 도 4에 도시된 바와 같이, 반도체 기판(100)으로서 실리콘 기판에 웰(well) 이온 주입 및 어닐링 공정을 실시하여 웰 영역(미도시함)을 형성한다. 그리고 트랜지스터의 문턱 전압(Vt)을 조절하기 위한 이온 주입 공정을 실시하여 문턱 전압 조절 영역(104)을 형성하고, 기판 상부에 게이트 산화막(106)과, 게이트전극용 도프트 폴리실리콘층(108)과, 하드 마스크(110)용 질화막을 순차적으로 적층한다. 미설명된 도면 부호 102는 산화막이다.3 and 4, a well region (not shown) is formed by performing well ion implantation and annealing processes on a silicon substrate as the semiconductor substrate 100. In addition, an ion implantation process for adjusting the threshold voltage Vt of the transistor is performed to form the threshold voltage adjusting region 104, and the gate oxide layer 106 and the doped polysilicon layer 108 for the gate electrode are formed on the substrate. And a nitride film for the hard mask 110 are sequentially stacked. Unexplained reference numeral 102 denotes an oxide film.
도 5a 및 도 5b는 본 발명에 따른 워드 라인 패터닝 공정을 나타낸 수직 단면도 및 평면도이다. 게이트 마스크를 이용한 식각 공정을 진행하여 적층된 하드 마스크(110) 내지 게이트 산화막(106)을 패터닝한다. 도면 부호 g는 가상의 활성 영역을 나타낸 것이다.5A and 5B are vertical cross-sectional views and plan views illustrating a word line patterning process according to the present invention. An etching process using a gate mask is performed to pattern the stacked hard mask 110 to the gate oxide layer 106. Reference numeral g denotes a virtual active area.
그리고 도 6에 도시된 바와 같이, 패터닝된 하드 마스크(110) 내지 게이트 산화막(106)의 측벽에 스페이서(112)를 형성하여 워드 라인(114)을 정의한다. 이때, 스페이서(112)는 절연물질의 하드 마스크(110)와 같은 높이가 되기 때문에 이후 플러그와 절연 상태를 유지하는 역할을 한다.6, spacers 112 are formed on sidewalls of the patterned hard mask 110 to the gate oxide layer 106 to define a word line 114. At this time, since the spacer 112 is the same height as the hard mask 110 of the insulating material serves to maintain the insulating state with the plug.
그 다음 스페이서(112)가 형성된 기판을 선택적 에피택셜 성장(SelectiveEpitaxial Growth: 이하 SEG라 함)시켜 에피층(116)을 형성시킨다. 이 에피층(116)은 플러그 용 콘택홀의 높은 에스팩트 비율을 낮추면서 이후 플러그가 콘택되는 접합 영역이다. 에피층(116)에 n형 불순물을 이온 주입하여 소오스/드레인 영역(118)을 형성한다. 이러한 소오스/드레인 영역(118)에 의해 이후 형성될 플러그의 콘택 저항이 감소하게 되어 셀 트랜지스터의 구동력이 개선된다. 또한 본 발명에 따른 제조 공정에 의해 워드 라인(114) 하부의 채널과 소오스/드레인 영역(118)이 스페이서(112) 및 에피층(116)에 의해 격리되고 고집적화 트랜지스터의 채널을 증가시킬 수 있다.The epitaxial layer 116 is then formed by selectively epitaxial growth (hereinafter referred to as SEG) of the substrate on which the spacer 112 is formed. The epi layer 116 is a junction region where the plug is subsequently contacted while lowering the high aspect ratio of the plug contact hole. An n-type impurity is ion-implanted into the epi layer 116 to form a source / drain region 118. This source / drain region 118 reduces the contact resistance of the plug to be formed later, thereby improving the driving force of the cell transistor. In addition, by the fabrication process according to the present invention, the channel and the source / drain region 118 under the word line 114 may be isolated by the spacer 112 and the epi layer 116 and increase the channel of the highly integrated transistor.
그 다음 도 7에 도시된 바와 같이, 에피층(116)이 형성된 스페이서(112) 사이의 공간에 도전물질로서 도프트 폴리실리콘을 매립하고 CMP로 연마하여 워드 라인(114)과 분리된 플러그(120)를 형성한다. 이때, 플러그(120)의 두께는 200Å∼500Å으로 얇게 형성한다.Then, as shown in FIG. 7, the doped polysilicon is embedded as a conductive material in the space between the spacers 112 on which the epi layer 116 is formed and polished with CMP to separate the plug 120 from the word line 114. ). At this time, the thickness of the plug 120 is 200 Å to 500 thin.
그리고 플러그(120)가 형성된 결과물 상부에 절연막(122)을 증착하는데, 이 절연막(122)은 질화막, BPSG(Boro Phospho Silicate Glass), PSG(Phospho Silicate Glass), BSG(Boro Silicate Glass), HDP(High Density Plasma) 산화막, USG(Undoped Silicate Glass) 중에서 어느 하나로 형성한다.In addition, an insulating film 122 is deposited on the resultant on which the plug 120 is formed. The insulating film 122 is formed of a nitride film, Boro Phospho Silicate Glass (BPSG), Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), or HDP ( High Density Plasma oxide film, USG (Undoped Silicate Glass) is formed of any one.
이러한 본 발명의 플러그 제조 공정에 의해 SAC 콘택홀의 에스팩트 비율을 낮출 수 있어 SAC 식각 공정으로 야기되는 소오스/드레인 영역의 식각 손상을 방지하여 누설전류로 인한 셀 트랜지스터의 리프레시 특성 저하를 막을 수 있다.By using the plug manufacturing process of the present invention, the aspect ratio of the SAC contact hole can be lowered, thereby preventing the damage of the source / drain regions caused by the SAC etching process, thereby preventing the refresh characteristics of the cell transistor due to the leakage current.
계속해서 도 8에 도시된 바와 같이, 결과물에 활성 영역 마스크(124)를 이용한 식각 공정을 진행한다.Subsequently, as shown in FIG. 8, an etching process using the active region mask 124 is performed on the resultant.
도 9a 내지 도 9c는 본 발명의 제조 공정에 따라 트렌치 및 소자분리막이 형성된 구조물을 나타낸 평면도 및 수직 단면도들이다.9A through 9C are plan and vertical cross-sectional views illustrating structures in which trenches and device isolation layers are formed according to a manufacturing process of the present invention.
상기 활성 영역 마스크(124)에 의해 소자 분리 영역에 대응하는 절연막(122)에서부터 기판(100)이 소정 깊이로 식각되어 트렌치(125)가 형성된다. 이로 인해, 기판의 활성 영역에만 워드라인(114)이 존재하도록 한다.A trench 125 is formed by etching the substrate 100 to a predetermined depth from the insulating layer 122 corresponding to the device isolation region by the active region mask 124. This allows the word line 114 to exist only in the active region of the substrate.
그리고, 트렌치(126)에 산화막을 매립하고 결과물을 CMP로 평탄화하여 STI구조의 소자분리막(126)을 형성하는데, 하드 마스크(110)가 드러날 때까지 CMP를 진행한다. 이때, 소자 분리막(126)은 워드라인 모양에 의해 트렌치의 수평 방향 길이가 너비 방향에 대비하여 격층화되어 소자 분리특성이 개선된다.An oxide film is embedded in the trench 126 and the resultant is flattened with CMP to form an isolation layer 126 having an STI structure. The CMP is performed until the hard mask 110 is exposed. In this case, the device isolation layer 126 has a word line shape, so that the horizontal length of the trench is laminated in comparison with the width direction, thereby improving device isolation characteristics.
도 10a 및 도 10b는 본 발명에 따라 제조된 게이트전극에 폴리사이드층을 형성한 구조물을 나타낸 수직 단면도들이다. 상기와 같이 소자 분리막(126)을 형성한 후에, 하드 마스크(110) 및 소자분리막(126)의 소정 영역을 식각하고 식각된 홈에 도전체 물질로서 텅스텐 실리사이드(WSix)를 형성한다. 이로 인해, 게이트 전극(108) 상부와 소자분리막(126)의 홈에는 실리사이드막(128)이 추가 형성된다.10A and 10B are vertical cross-sectional views illustrating a structure in which a polyside layer is formed on a gate electrode manufactured according to the present invention. After the device isolation layer 126 is formed as described above, predetermined regions of the hard mask 110 and the device isolation layer 126 are etched to form tungsten silicide (WSix) as a conductor material in the etched groove. As a result, a silicide layer 128 is further formed on the gate electrode 108 and the groove of the device isolation layer 126.
그러므로, 본 발명의 워드라인은 폴리사이드 구조를 갖고 셀 트랜지스터의 워드 라인사이가 소자분리막에 의해 절연되기 때문에 워드 라인과 비트 라인과의 커플링 커패시턴스가 감소되고 STI 소자분리막의 모트 영향을 방지하여 셀 트랜지스터의 전계 감소에 의한 리프레시 특성을 개선한다.Therefore, since the word line of the present invention has a polyside structure and the word lines of the cell transistors are insulated by the device isolation film, the coupling capacitance between the word line and the bit line is reduced and the influence of the STI device isolation film prevents the cell effect. The refresh characteristic by the electric field reduction of a transistor is improved.
본 발명은 도 10a 및 도 10b에 도시된 바와 같이, STI 공정 전에 플러그 영역을 SEG로 성장시킨 후에, 플러그(116)를 형성함으로써 SAC 불량을 방지(h)하면서 소오스/드레인 영역(118)과 게이트 채널을 격리시킨다.10A and 10B, the source / drain region 118 and the gate are formed while the plug region is grown to SEG before the STI process, and then the plug 116 is formed to prevent (h) SAC defects. Isolate the channel.
그리고 본 발명은 플러그(116)가 형성된 구조물에 STI 공정을 실시함으로써 인접 셀 트랜지스터와의 소자분리영역을 격층화(j)하여 소자분리 효과를 높이고 소오스/드레인 영역(118)의 전계 감소(i)에 의한 리프레시를 개선할 수 있다. 플러그(116)가 스페이서(112)와 STI 소자분리막(126) 사이에 존재하게 되고 워드 라인을 폴리사이드 구조로 형성함으로써 커플링 커패시턴스(k)를 낮출 수 있다.In addition, according to the present invention, an STI process is performed on the structure in which the plug 116 is formed to increase the device isolation effect by stacking the device isolation region with the adjacent cell transistor (j) and to reduce the electric field of the source / drain region 118 (i). The refresh by can be improved. The coupling capacitance k may be lowered by the plug 116 being present between the spacer 112 and the STI device isolation layer 126 and forming a word line in a polyside structure.
그러므로, 본 발명은 셀 트랜지스터의 동작을 안정화하고 동작 속도를 개선하여 스피드 효과를 증가시킬 수 있는 효과가 있다.Therefore, the present invention has the effect of increasing the speed effect by stabilizing the operation of the cell transistor and improving the operation speed.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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