KR20060020822A - 반도체 칩 패키지 및 그 제조방법 - Google Patents

반도체 칩 패키지 및 그 제조방법 Download PDF

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KR20060020822A
KR20060020822A KR1020040069510A KR20040069510A KR20060020822A KR 20060020822 A KR20060020822 A KR 20060020822A KR 1020040069510 A KR1020040069510 A KR 1020040069510A KR 20040069510 A KR20040069510 A KR 20040069510A KR 20060020822 A KR20060020822 A KR 20060020822A
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South Korea
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electrode
semiconductor chip
chip package
forming
package manufacturing
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KR1020040069510A
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English (en)
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KR100604049B1 (ko
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강병영
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동부아남반도체 주식회사
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Priority to KR1020040069510A priority Critical patent/KR100604049B1/ko
Priority to US11/026,661 priority patent/US7119001B2/en
Publication of KR20060020822A publication Critical patent/KR20060020822A/ko
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Publication of KR100604049B1 publication Critical patent/KR100604049B1/ko

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Abstract

본 발명은 반도체 칩 패키지 및 그 제조방법에 관한 것으로, 보다 자세하게는 웨이퍼를 관통하는 관통전극을 형성하여 웨이퍼 전극 패드와 외부 회로를 연결함으로써 공정 단축, 소자 특성 향상 및 소형화가 가능한 웨이퍼 레벨의 반도체 칩 패키지 및 그 제조방법에 관한 것이다.
본 발명의 상기 목적은 다수의 전극 패드를 포함한 반도체 소자가 위치한 제 1 면 및 상기 제 1 면에 대향된 제 2 면을 포함하는 실리콘 웨이퍼; 상기 제 1 면을 덮는 보호막; 상기 제 2 면으로부터 상기 전극 패드까지 관통하는 관통홀에 도전체가 충진된 관통전극; 및 상기 관통전극과 외부 회로와의 전기적 연결을 위한 솔더 범프 또는 솔더 볼을 포함하는 것을 특징으로 하는 반도체 칩 패키지에 의해 달성된다.
따라서, 본 발명의 반도체 칩 패키지 및 그 제조방법은 전극 패드까지 연결되는 관통전극을 형성하여 외부 회로와 연결함으로써 공정 단축, 소자 특성 향상, 소형화, 박형화 및 열방출 효과가 우수하며 환경 친화적이고 제조 단가를 낮추는 효과가 있다.
관통전극, 웨이퍼 레벨 패키지(WLP), 칩 스케일 패키지(CSP)

Description

반도체 칩 패키지 및 그 제조방법{Semiconductor package and method for fabricating the same}
도 1은 종래의 BGA 패키지의 단면도.
도 2a 내지 도 2e는 본 발명에 의한 반도체 칩 패키지 제조 공정 단면도.
도 3a 내지 도 3d는 본 발명의 다른 실시예에 의한 반도체 칩 패키지 제조 공정 단면도.
본 발명은 반도체 칩 패키지 및 그 제조방법에 관한 것으로, 보다 자세하게는 웨이퍼를 관통하는 관통전극을 형성하여 웨이퍼 전극 패드와 외부 회로를 연결함으로써 공정 단축, 소자 특성 향상 및 소형화가 가능한 웨이퍼 레벨의 반도체 칩 패키지 및 그 제조방법에 관한 것이다.
일반적으로 다이오드, 트랜지스터 등의 반도체 소자로 구성되는 집적회로(IC: Integrated Circuit)는 패키지를 형성하여 인쇄회로기판 상에 실장된 다. 이러한 반도체 소자의 패키지는 제품의 소형화 추세에 맞춰 점차 소형화되고 있다. 1990년대 전반에 출현한 볼 그리드 어레이(Ball Grid Array, 이하 BGA)라는 패키지는 현재 다기능, 고성능을 특징으로 하는 전자기기에 많이 사용되고 있다.
도 1은 이러한 BGA 패키지의 구성을 나타낸 단면도이다.
도 1에 도시된 바와 같이, 기판(100)은 칩 패드(102)와 에폭시 접착제(104)를 매개로 칩(106)과 부착되어 있다. 기판(100)과 칩(106)을 전기적으로 연결하기 위해 기판 상의 본딩 패드(108)와 칩 상의 칩 패드(도시하지 않음)를 연결하는 와이어 본딩(110)이 있고 상기 와이어 본딩(110)을 보호하기 위해 에폭시 몰딩 화합물(112)로 봉지되어 있다. 또한 기판의 바닥면에 형성된 솔더볼(114)을 통해 최종 제품의 인쇄회로기판(PCB: Printed Circuit Board)에 칩 패키지를 기계 및 전기적으로 고정시킨다.
종래의 BGA 패키지는 웨이퍼 배면을 연마하는 단계, 웨이퍼를 칩별로 절단(sawing)하는 단계. 칩을 부착하는 단계, 와이어 본딩하는 단계, 몰딩하는 단계를 포함하는 일련의 공정을 거쳐 완성된 후 인쇄회로기판 상에 고정되게 된다.
이러한 BGA 칩 패키지는 와이어 본딩을 통해 기판과 칩을 연결하기 때문에 그 구조상 패키지의 소형화에는 한계가 있으며 제조 공정이 복잡하고 환경오염 물질인 에폭시 몰딩 화합물을 사용함으로 인해 친환경적이지 못하다. 또한, 웨이퍼를 칩별로 절단한 후 패키지를 구성하였다.
그러나 웨이퍼를 개별 칩으로 절단하기 전에 집적회로 패키지를 형성하는 웨이퍼 레벨 패키지(WLP: Wafer Level Package) 기술이 등장하였고 이러한 방식은 칩 패키지의 대량 생산을 용이하게 하고 웨이퍼 상에서 행렬 형태로 배열되는 여러 개의 칩 패키지를 한번에 모두 제조하여 테스트할 수 있게 되어 집적회로 칩의 패키지 공정과 테스트 공정에서 시간과 비용을 모두 절감시킬 수 있게 되었다.
우드(Wood) 등의 미합중국 특허 제5,851,845호는 복수의 다이를 포함하는 웨이퍼의 후면을 연마하거나 에칭함으로써 얇게 한 후 얇아진 웨이퍼를 기판에 부착하여 절단함으로써 반도체 패키지를 형성하는 웨이퍼 레벨 패키지 제조 방법을 개시하고 있고, 상후동(Sang Hoo Dhong) 등의 미합중국 특허 제6,221,769호는 실리콘 기판을 관통하는 관통홀을 기계적인 방법으로 형성한 후 그 관통홀을 통해 칩 패드와 연결하는 패키지 제조 방법을 개시하고 있으며, 대한민국 공개특허공보 제2003-56174호는 칩의 일면에 도전층을 형성하고 도전성 비아홀이 형성된 기판을 인쇄회로기판과 칩 사이에 부착하여 와이어 본딩이 필요없는 웨이퍼 레벨 칩 스케일 패키지(CSP: Chip Scale Package) 및 그 제조방법을 개시하고 있다.
이러한 WLP 방식에서는 기존의 패키지에서의 칩과 패키지 사이의 접속기술(와이어 본딩, TAB, 플립칩 본딩 등) 대신에 다이싱하기 전에 플립칩(flip chip)과 같은 원리로 반도체 전(前)공정의 배선기술을 사용하여 칩 패드와 외부 단자를 결선하는 방법이 기본이다.
그러나 이러한 결선 방법은 그 공정이 복잡할 뿐만 아니라 대개의 경우 추가적인 기판을 칩과 인쇄회로기판 사이에 개재하기 때문에 그 두께가 얇아지는데 한계가 있으며 칩의 신뢰성이 저하되는 문제가 있다.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 실리콘 웨이퍼의 제 2 면으로부터 상기 제 2 면에 대향한 제 1 면의 전극 패드까지 관통하는 관통전극을 형성한 후 솔더 범프 또는 솔더 볼을 형성하여 외부 회로와 연결함으로써 공정 단축, 소자 특성 향상, 소형화 및 박형화가 가능한 웨이퍼 레벨의 반도체 칩 패키지 및 그 제조방법을 제공함에 본 발명의 목적이 있다.
본 발명의 상기 목적은 다수의 전극 패드를 포함한 반도체 소자가 위치한 제 1 면 및 상기 제 1 면에 대향된 제 2 면을 포함하는 실리콘 웨이퍼; 상기 제 1 면을 덮는 보호막; 상기 제 2 면으로부터 상기 전극 패드까지 관통하는 관통홀에 도전체가 충진된 관통전극; 및 상기 관통전극과 외부 회로와의 전기적 연결을 위한 솔더 범프 또는 솔더 볼을 포함하는 것을 특징으로 하는 반도체 칩 패키지에 의해 달성된다.
본 발명의 상기 목적은 다수의 전극 패드를 포함한 반도체 소자를 실리콘 웨이퍼의 제 1 면 상에 형성하는 단계; 상기 제 1 면에 대향된 제 2 면으로부터 상기 전극 패드까지 관통하는 관통홀을 형성하는 단계; 상기 관통홀에 도전성 금속을 매립하여 관통전극을 형성하는 단계; 상기 제 1 면을 덮는 보호막을 형성하는 단계; 상기 제 2 면의 일부를 연마하여 제거하는 단계; 상기 관통전극과 외부 회로와의 연결을 위한 솔더 범프 또는 솔더 볼을 형성하는 단계; 및 상기 웨이퍼를 절단하여 각각의 칩으로 분리하는 단계를 포함하는 것을 특징으로 하는 반도체 칩 패키지 제조방법에 의해서도 달성된다.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.
<실시예 1>
도 2a 내지 도 2d는 본 발명에 의한 반도체 칩 패키지 제조 공정의 단면도이다.
먼저, 도 2a에 도시된 바와 같이, 실리콘 웨이퍼(200)의 제 1 면(200a)에는 소정의 공정을 거쳐 외부 회로와의 전기적 연결을 위한 전극 패드(202)를 포함한 반도체 소자(도시하지 않음)가 형성되어 있으며 상기 실리콘 웨이퍼(200)의 제 2 면(200b)로부터 상기 제 1 면(200a)의 전극 패드(202)까지 관통하는 관통홀(Via hole 또는 through hole, 204)을 형성한다.
상기 관통홀(204)을 형성하는 방법은 레이저 가공 또는 반응성 이온 식각(Reactive Ion Etch, 이하 RIE)과 같은 건식 식각 공정 등을 사용할 수 있다. 상기 관통홀(204)의 형상은 원형, 삼각형, 사각형 또는 다각형과 같이 다양한 형상이 가능하며 상기 관통홀(204)의 단면적은 일정할 수도 있고 제 1 면(200a)에 가까울수록 단면적이 크거나 작을 수도 있다.
다음, 도 2b에 도시된 바와 같이, 상기 관통홀(204)을 도전체로 매립하여 관 통전극(206)을 형성한 후 제 1 면(200a)을 덮는 보호막(208)을 형성한다.
상기 관통전극(206)을 형성하는 방법은 전기도금을 이용하는 것이 가능하며 상기 도전체로는 전기도금이 가능한 모든 금속 예를 들어, 금(Au), 은(Ag), 구리(Cu), 알루미늄(Al), 니켈(Ni) 및 텅스텐(W) 등이 가능하다.
또한, 상기 관통전극(206)을 진공증착(vacuum evaporation), 스퍼터링(sputtering), 화학기상증착(Chemical Vapor Deposition, 이하 CVD) 및 전도성 페이스트(paste)를 매립한 후 소성하는 방법 등으로 형성하는 방법도 가능하다. 상기 관통전극(206)용 물질로는 전도성 물질(예를 들어, 금, 은, 구리, 알루미늄, 니켈, 크롬(Cr) 및 텅스텐 등과 같은 전도성 금속 및 그 합금)이면 무엇이든 가능하다.
상기 보호막(208)은 반도체 칩을 외부 환경으로부터 보호하기 위한 것으로서 유기 절연막 또는 무기 절연막으로 형성한다. 상기 보호막(208)의 일례로 폴리이미드(polyimide), 질화막 등을 들 수 있다.
다음, 도 2c에 도시된 바와 같이, 상기 관통전극(206)을 포함한 실리콘 웨이퍼(200)를 제 2 면(200b)으로부터 소정 두께(t)만큼 연마하여 제거함으로써 원하는 두께의 실리콘 웨이퍼(200)를 형성한다. 실리콘 웨이퍼(200)의 두께는 이후 형성될 칩의 두께를 결정하게 된다. 상기 실리콘 웨이퍼(200)의 연마는 화학적 기계적 연마(Chemical Mechanical Polsihing, 이하 CMP)를 통해 수행하는 것이 바람직하다.
다음, 도 2d에 도시된 바와 같이, 실리콘 웨이퍼의 제 2 면(200b)쪽으로 노출된 상기 관통전극(206) 상에 배리어(barrier) 금속막(210)을 형성한다.
상기 배리어 금속막(210)은 이후의 솔더 범프 또는 솔더 볼 형성시 그 접착을 용이하게 하며 칩의 사용시 발생하는 열에 의한 크랙(Crack)을 방지하여 칩의 신뢰성을 확보하는 역할을 한다. 상기 배리어 금속막(210)으로는 티타늄(Ti), 티타늄 나이트라이드(TiN), 탄탈륨 나이트라이드(TaN), Ti/TiN 또는 Ta/TaN 등이 가능하다. 상기 배리어 금속막(210)은 CVD 공정을 통해 형성하는 것이 바람직하다.
다음, 도 2e에 도시된 바와 같이, 상기 배리어 금속막 상에 칩과 외부 회로와의 전기적 연결을 위한 솔더 범프(214) 또는 솔더 볼(216)을 형성한다. 상기 솔더 범프(214) 또는 솔더 볼(216)은 전도성 물질이면 무엇이든 가능하나 구리, 금 또는 주석계의 전도성 금속이 바람직하다.
상기 솔더 범프(214) 또는 솔더 볼(216)을 형성하기 전에 솔더 마스크(212)를 추가적으로 더 형성하는 것도 가능하다. 솔더 레지스트(resist)를 도포하고 열처리한 후 솔더 범프(214) 또는 솔더 볼(216)이 형성될 영역을 노출함으로써 솔더 마스크(212)를 형성한다.
마지막으로, 도면에 도시되지 않았으나 상기 실리콘 웨이퍼(200)를 각각의 칩으로 분리하기 위해 절단하고 후속 공정을 진행하여 웨이퍼 레벨 패키지를 완성한다.
<실시예 2>
도 3a 내지 도 3d는 본 발명의 다른 실시예에 의한 반도체 칩 패키지 제조 공정의 단면도이다.
먼저, 도 3a에 도시된 바와 같이, 실리콘 웨이퍼(300)의 제 1 면(300a)에는 소정의 공정을 거쳐 외부 회로와의 전기적 연결을 위한 전극 패드(302)를 포함한 반도체 소자(도시하지 않음)가 형성되어 있으며 상기 실리콘 웨이퍼(300)의 제 2 면(300b)로부터 상기 제 1 면(300a)의 전극 패드(302)까지 관통하는 관통홀(304)을 형성한다. 상기 관통홀(304)의 형성 방법은 실시예 1과 동일하다.
다음, 도 3b에 도시된 바와 같이, 상기 관통홀(304)의 표면을 따라 배리어 금속막(310)을 증착하고 상기 배리어 금속막(310)으로 이루어지는 홀을 도전체로 매립하여 관통전극(306)을 형성한 후 제 1 면(300a)을 덮는 보호막(308)을 형성한다.
상기 배리어 금속막(310), 관통전극(306) 및 보호막(308)의 형성 방법 및 그 재료는 실시예 1과 동일하다.
다음, 도 3c에 도시된 바와 같이, 상기 관통전극(306) 및 배리어 금속막(310)을 포함한 실리콘 웨이퍼(300)를 제 2 면(300b)으로부터 소정 두께(t)만큼 연마하여 제거함으로써 원하는 두께의 실리콘 웨이퍼(300)를 형성한다. 상기 실리콘 웨이퍼(300)의 연마는 CMP 공정을 통해 수행하는 것이 바람직하다.
다음, 도 3d에 도시된 바와 같이, 실리콘 웨이퍼의 제 2 면(300b)에 노출된상기 관통전극(306) 상에 칩과 외부 회로와의 전기적 연결을 위한 솔더 범프(314) 또는 솔더 볼(316)을 형성한다. 상기 솔더 범프(314) 또는 솔더 볼(316)은 전도성 물질이면 무엇이든 가능하나 구리, 금 또는 주석계의 전도성 금속이 바람직하다. 상기 솔더 범프(314) 또는 솔더 볼(316)을 형성하기 전에 솔더 마스크(312)를 실시 예 1에 설명된 방법과 동일한 방법으로 형성하는 것도 가능하다.
또한 도면에 도시하지 않았으나 상기 솔더 범프(314) 또는 솔더 볼(316) 형성 전에, 솔더 범프(314) 또는 솔더 볼(316)과 관통전극(306) 사이에 배리어 금속막을 추가적으로 더 형성할 수 있다. 상기 추가적으로 형성되는 배리어 금속막으로는 티타늄, 티타늄 나이트라이드, 탄탈륨 나이트라이드, Ti/TiN 또는 Ta/TaN 등이 가능하며 CVD 공정을 통해 형성하는 것이 바람직하다.
마지막으로, 도면에 도시되지 않았으나 상기 실리콘 웨이퍼(300)를 각각의 칩으로 분리하기 위해 절단하고 후속 공정을 진행하여 웨이퍼 레벨 패키지를 완성한다.
상술한 바와 같이, 본 발명은 실리콘 웨이퍼의 제 2 면으로부터 반도체 소자가 형성된 제 1 면의 전극 패드까지 연결되는 관통전극을 형성함으로써 반도체 패키지의 공정 단축, 소자 특성 향상, 소형화 및 박형화가 가능하며 배리어 금속막의 형성을 통해서 열충격에 강하고 신뢰성 있는 반도체 칩 패키지의 제조가 가능하다. 또한, 종래의 에폭시 몰딩 화합물을 사용하지 않기 때문에 오염 물질의 생성을 억제할 수 있다.
따라서, 점차 소형화되고 있는 반도체 소자의 칩 스케일 패키기를 효과적으로 구현할 수 있으며 나아가 멀티 칩 모듈(MCM: Multi Chip Module) 등에 응용이 가능하다.
본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.
따라서, 본 발명의 반도체 칩 패키지 및 그 제조방법은 전극 패드까지 연결되는 관통전극을 형성하여 외부 회로와 연결함으로써 공정 단축, 소자 특성 향상, 소형화, 박형화 및 열방출 효과가 우수하며 환경 친화적이고 제조 단가를 낮추는 효과가 있다.

Claims (17)

  1. 반도체 칩 패키지에 있어서,
    다수의 전극 패드를 포함한 반도체 소자가 위치한 제 1 면 및 상기 제 1 면에 대향된 제 2 면을 포함하는 실리콘 웨이퍼;
    상기 제 1 면을 덮는 보호막;
    상기 제 2 면으로부터 상기 전극 패드까지 관통하는 관통홀에 도전체가 충진된 관통전극; 및
    상기 관통전극과 외부 회로와의 전기적 연결을 위한 솔더 범프 또는 솔더 볼
    을 포함하는 것을 특징으로 하는 반도체 칩 패키지.
  2. 제 1 항에 있어서,
    상기 관통전극과 상기 실리콘 웨이퍼가 접촉하는 계면을 따라 존재하는 배리어 금속막을 더 포함하는 것을 특징으로 하는 반도체 칩 패키지.
  3. 제 1 항에 있어서,
    상기 제 2 면쪽으로 노출된 관통전극의 표면에 존재하는 배리어 금속막을 더 포함하는 것을 특징으로 하는 반도체 칩 패키지.
  4. 제 1 항에 있어서,
    상기 제 2 면을 덮는 솔더 마스크를 더 포함하는 것을 특징으로 하는 반도체 칩 패키지.
  5. 제 2 항 또는 제 3 항에 있어서,
    상기 배리어 금속막은 티타늄, 티타늄 나이트라이드, 탄탈륨 나이트라이드, Ti/TiN 또는 Ta/TaN 중 어느 하나로 이루어지는 것을 특징으로 하는 반도체 칩 패키지.
  6. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,
    상기 보호막은 폴리이미드인 것을 특징으로 하는 반도체 칩 패키지.
  7. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,
    상기 관통 전극은 금, 은, 구리, 알루미늄, 니켈, 텅스텐 중 어느 하나인 것을 특징으로 하는 반도체 칩 패키지.
  8. 반도체 칩 패키지 제조방법에 있어서,
    다수의 전극 패드를 포함한 반도체 소자를 실리콘 웨이퍼의 제 1 면 상에 형성하는 단계;
    상기 제 1 면에 대향된 제 2 면으로부터 상기 전극 패드까지 관통하는 관통홀을 형성하는 단계;
    상기 관통홀에 도전성 금속을 매립하여 관통전극을 형성하는 단계;
    상기 제 1 면을 덮는 보호막을 형성하는 단계;
    상기 제 2 면의 일부를 연마하여 제거하는 단계;
    상기 관통전극과 외부 회로와의 연결을 위한 솔더 범프 또는 솔더 볼을 형성하는 단계; 및
    상기 웨이퍼를 절단하여 각각의 칩으로 분리하는 단계
    를 포함하는 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  9. 제 8 항에 있어서,
    상기 관통전극을 형성하는 단계 전에 상기 관통홀의 표면을 따라 배리어 금속막을 형성하는 단계
    를 더 포함하는 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  10. 제 8 항에 있어서,
    상기 솔더 범프 또는 솔더 볼을 형성하는 단계 전에 상기 제 2 면쪽으로 노출된 상기 관통전극 상에 배리어 금속막을 형성하는 단계
    를 더 포함하는 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  11. 제 8 항에 있어서,
    상기 솔더 범프 또는 솔더 볼을 형성하는 단계 전에 솔더 마스크를 형성하는 단계
    를 더 포함하는 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  12. 제 9 항 또는 제 10 항에 있어서,
    상기 배리어 금속막은 티타늄, 티타늄 나이트라이드, 탄탈륨 나이트라이드, Ti/TiN 또는 Ta/TaN 중 어느 하나로 이루어지는 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  13. 제 8 항 내지 제 11 항 중 어느 한 항에 있어서,
    상기 보호막은 폴리이미드인 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  14. 제 8 항 내지 제 11 항 중 어느 한 항에 있어서,
    상기 관통홀은 레이저 가공 또는 RIE 공정에 의해 형성하는 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  15. 제 8 항 내지 제 11 항 중 어느 한 항에 있어서,
    상기 관통전극은 전기도금, 진공증착, 스퍼터링, CVD 및 스크린 프린팅 중 어느 하나의 방법으로 형성되는 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  16. 제 8 항 내지 제 11 항 중 어느 한 항에 있어서,
    상기 관통 전극은 금, 은, 구리, 알루미늄, 니켈 중 어느 하나인 것을 특징으로 하는 반도체 칩 패키지 제조방법.
  17. 제 8 항 내지 제 11 항 중 어느 한 항에 있어서,
    상기 제 2 면의 연마는 CMP 공정을 통해 수행하는 것을 특징으로 하는 반도체 칩 패키지 제조방법.
KR1020040069510A 2004-09-01 2004-09-01 반도체 칩 패키지 및 그 제조방법 KR100604049B1 (ko)

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