KR20050085833A - 반도체 디바이스 형성 방법 및 구조 - Google Patents

반도체 디바이스 형성 방법 및 구조 Download PDF

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Publication number
KR20050085833A
KR20050085833A KR1020057011564A KR20057011564A KR20050085833A KR 20050085833 A KR20050085833 A KR 20050085833A KR 1020057011564 A KR1020057011564 A KR 1020057011564A KR 20057011564 A KR20057011564 A KR 20057011564A KR 20050085833 A KR20050085833 A KR 20050085833A
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KR
South Korea
Prior art keywords
forming
dielectric layer
dummy
conductive
current transport
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020057011564A
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English (en)
Korean (ko)
Inventor
신디 케이. 골드버그
스탠리 엠. 필리피악
존 시. 플레이크
영지 티. 리
브래들리 피. 스미스
유리 이. 솔로멘츠브
테리 지. 스팍스
키크 제이. 스트로제스키
케이스린 시. 유
Original Assignee
프리스케일 세미컨덕터, 인크.
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Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20050085833A publication Critical patent/KR20050085833A/ko
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020057011564A 2002-12-20 2003-09-23 반도체 디바이스 형성 방법 및 구조 Ceased KR20050085833A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/327,403 2002-12-20
US10/327,403 US6838354B2 (en) 2002-12-20 2002-12-20 Method for forming a passivation layer for air gap formation

Publications (1)

Publication Number Publication Date
KR20050085833A true KR20050085833A (ko) 2005-08-29

Family

ID=32594241

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057011564A Ceased KR20050085833A (ko) 2002-12-20 2003-09-23 반도체 디바이스 형성 방법 및 구조

Country Status (8)

Country Link
US (1) US6838354B2 (https=)
EP (1) EP1579497A3 (https=)
JP (2) JP4799868B2 (https=)
KR (1) KR20050085833A (https=)
CN (1) CN100378948C (https=)
AU (1) AU2003279030A1 (https=)
TW (1) TWI367543B (https=)
WO (1) WO2004061948A2 (https=)

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KR101054709B1 (ko) * 2006-07-11 2011-08-05 인터내셔널 비지네스 머신즈 코포레이션 유전체 에어 갭을 갖는 상호접속 구조물
US9209073B2 (en) 2013-03-12 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Metal cap apparatus and method
KR20170109878A (ko) * 2016-03-22 2017-10-10 삼성전자주식회사 반도체 장치 및 그의 제조 방법

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US7361991B2 (en) * 2003-09-19 2008-04-22 International Business Machines Corporation Closed air gap interconnect structure
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US7405147B2 (en) 2004-01-30 2008-07-29 International Business Machines Corporation Device and methodology for reducing effective dielectric constant in semiconductor devices
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JP5650878B2 (ja) * 2007-06-20 2015-01-07 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． ダミーパターンの設計方法、露光マスク、半導体装置、半導体装置の製造方法およびダミーパターンの設計プログラム
US7879683B2 (en) 2007-10-09 2011-02-01 Applied Materials, Inc. Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay
JP2009094378A (ja) * 2007-10-11 2009-04-30 Panasonic Corp 半導体装置及びその製造方法
JP4856107B2 (ja) * 2008-02-14 2012-01-18 パナソニック株式会社 半導体装置の製造方法及び半導体装置
KR101382564B1 (ko) * 2008-05-28 2014-04-10 삼성전자주식회사 에어갭을 갖는 층간 절연막의 형성 방법
US8108820B2 (en) * 2008-09-11 2012-01-31 International Business Machines Corporation Enhanced conductivity in an airgapped integrated circuit
DE102008059650B4 (de) * 2008-11-28 2018-06-21 Globalfoundries Inc. Verfahren zur Herstellung einer Mikrostruktur mit einer Metallisierungsstruktur mit selbstjustierten Luftspalten zwischen dichtliegenden Metallleitungen
US8497203B2 (en) 2010-08-13 2013-07-30 International Business Machines Corporation Semiconductor structures and methods of manufacture
US8530347B2 (en) * 2010-10-05 2013-09-10 Freescale Semiconductor, Inc. Electronic device including interconnects with a cavity therebetween and a process of forming the same
CN107104092B (zh) 2011-12-29 2020-02-21 英特尔公司 具有罩层的气隙互连以及形成的方法
JP5696679B2 (ja) * 2012-03-23 2015-04-08 富士通株式会社 半導体装置
KR102003881B1 (ko) * 2013-02-13 2019-10-17 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102154112B1 (ko) * 2013-08-01 2020-09-09 삼성전자주식회사 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법
JP6295802B2 (ja) * 2014-04-18 2018-03-20 ソニー株式会社 高周波デバイス用電界効果トランジスタおよびその製造方法、ならびに高周波デバイス
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9583380B2 (en) 2014-07-17 2017-02-28 Globalfoundries Inc. Anisotropic material damage process for etching low-K dielectric materials
US9443956B2 (en) 2014-12-08 2016-09-13 Globalfoundries Inc. Method for forming air gap structure using carbon-containing spacer
US10553532B2 (en) 2014-12-24 2020-02-04 Intel Corporation Structure and method to self align via to top and bottom of tight pitch metal interconnect layers
US9768058B2 (en) 2015-08-10 2017-09-19 Globalfoundries Inc. Methods of forming air gaps in metallization layers on integrated circuit products
CN108028224B (zh) * 2015-10-16 2022-08-16 索尼公司 半导体装置以及半导体装置的制造方法
US9922940B2 (en) * 2016-02-22 2018-03-20 Toshiba Memory Corporation Semiconductor device including air gaps between interconnects and method of manufacturing the same
US10020260B1 (en) * 2016-12-22 2018-07-10 Globalfoundries Inc. Corrosion and/or etch protection layer for contacts and interconnect metallization integration
TW202445617A (zh) * 2023-01-12 2024-11-16 美商阿特拉斯磁性公司 利用無電電鍍技術增加非磁性複合材料之集膚深度並減少其渦流之方法及裝置

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KR101054709B1 (ko) * 2006-07-11 2011-08-05 인터내셔널 비지네스 머신즈 코포레이션 유전체 에어 갭을 갖는 상호접속 구조물
US9209073B2 (en) 2013-03-12 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Metal cap apparatus and method
US9786604B2 (en) 2013-03-12 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Metal cap apparatus and method
KR20170109878A (ko) * 2016-03-22 2017-10-10 삼성전자주식회사 반도체 장치 및 그의 제조 방법
US12142558B2 (en) 2016-03-22 2024-11-12 Samsung Electronics Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
EP1579497A2 (en) 2005-09-28
US6838354B2 (en) 2005-01-04
JP2006511955A (ja) 2006-04-06
EP1579497A3 (en) 2005-12-07
AU2003279030A1 (en) 2004-07-29
US20040119134A1 (en) 2004-06-24
CN1820365A (zh) 2006-08-16
JP2006324689A (ja) 2006-11-30
TWI367543B (en) 2012-07-01
JP4799868B2 (ja) 2011-10-26
CN100378948C (zh) 2008-04-02
TW200414414A (en) 2004-08-01
WO2004061948A3 (en) 2005-10-13
WO2004061948A2 (en) 2004-07-22
JP4794389B2 (ja) 2011-10-19

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