KR20050018521A - Manufacturing method of thin film transistor array panel - Google Patents

Abstract

PURPOSE: A method for manufacturing a TFT(Thin Film Transistor) substrate is provided to reduce processing time and improve production yield by forming source and drain regions and lightly doped impurity regions in the same ion implantation chamber through a single process. CONSTITUTION: A polysilicon layer is formed on an insulating substrate(110). A gate insulating layer is formed on the polysilicon layer. A metal layer is formed on the gate insulating layer. A photoresist pattern is formed on the metal layer. The metal layer is patterned using the photoresist pattern as a mask using an isotropic etching process to form a gate line having a gate electrode(124). The gate insulating layer is patterned using the photoresist pattern as a mask to form gate insulating patterns(140p,140q) and the photoresist pattern is removed. Impurities are heavily doped into the polysilicon layer to form source and drain regions(153,155) and a channel region(154). A lightly doped impurity region(152) is formed in the polysilicon layer. The first interlevel insulating layer(601) having the first and second contact holes(141,142) is formed on the substrate to cover the gate line. A data line having a source electrode(173) connected to the source region through the first contact hole and a drain electrode(175) connected to the drain region through the second contact hole are formed on the first interlevel insulating layer. The second interlevel insulating layer(602) having the third contact hole(143) is formed on the substrate to cover the data line and the drain electrode. A pixel electrode(190) is formed on the second interlevel insulating layer to be connected to the drain electrode through the third contact hole. The source and drain regions are formed by heavily doping impurities with low energy and the lightly doped impurity region is formed by lightly doping impurities with high energy.

Description

Manufacturing method of thin film transistor array panel

The present invention relates to a method for manufacturing a thin film transistor array panel, and more particularly, to a method for manufacturing a thin film transistor array panel using polycrystalline silicon as a semiconductor layer.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor array panel includes a scan signal line or gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like. It includes.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode which is a part of the gate line, a source electrode which is a part of the data line, and a drain electrode facing the source electrode around the semiconductor layer. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

In this case, the semiconductor layer is made of amorphous silicon, polycrystalline silicon, or the like, and the thin film transistor may be divided into a top gate method and a bottom gate method according to a position relative to the gate electrode. In the case of a polysilicon thin film transistor array panel, a top gate method in which a gate electrode is located above the semiconductor layer is mainly used.

The top gate method has the advantage of forming a driving circuit for operating the thin film transistor together with the thin film transistor in the pixel region because the driving speed of the thin film transistor is much faster than that of the bottom gate method. It is desirable to form a lightly doped region between the channel region and the source and drain regions of the layer.

The lightly doped region forms the channel region and the source region and the drain region of the semiconductor layer and then forms it therebetween. That is, the channel region, the source region, and the drain region of the semiconductor layer are formed in the ion implantation chamber, and the substrate is unloaded out of the ion implantation chamber to form a mask defining a lightly doped region on the substrate. The substrate having the mask defining the lightly doped region is reloaded into the ion implantation chamber to form a lightly doped region between the channel region, the source region, and the drain region of the semiconductor layer.

However, the method of forming the low concentration doped region according to the prior art forms the channel region, the source region and the drain region in the ion implantation chamber, and unloads the substrate out of the ion implantation chamber to form a mask defining the low concentration doped region. There is a cumbersome problem of having to reload the ion implantation chamber again. In addition, the process time is lengthened thereby, the production yield is lowered.

It is an object of the present invention to provide a method of manufacturing a thin film transistor array panel in which a source region, a drain region, and a lightly doped region can be formed in a single process in the same ion implantation chamber.

In order to achieve the above object, the present invention provides a method of manufacturing the following thin film transistor array panel.

More specifically, forming a polycrystalline silicon layer on an insulating substrate, forming a gate insulating film on the polycrystalline silicon layer, laminating a metal film on the gate insulating film, forming a photosensitive film pattern defining a formation region of the gate line on the metal film Forming a gate line having a gate electrode by patterning a metal film using an anisotropic etching process using a photosensitive film pattern as a mask, forming a gate insulating pattern by patterning a gate insulating film using an isotropic etching process using the photosensitive film pattern as a mask, and then forming a gate insulating pattern Removing the pattern, forming a source region, a drain region, and a channel region which is not doped with impurities, by doping a highly conductive dopant in the polysilicon layer, forming a low concentration doped region in the polycrystalline silicon layer, a gate line Covering and having first and second contact holes Forming a first interlayer insulating film, forming a data line having a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole on the first interlayer insulating film Forming a second interlayer insulating film covering the line and drain electrodes and having a third contact hole, and forming a pixel electrode connected to the drain electrode through the third contact hole on the second interlayer insulating film, the source region The forming of the drain region may include a method of manufacturing a thin film transistor array panel in which the doping region may be doped with high energy at low energy, and the doping region may be doped at low concentration with high energy.

Here, in the forming of the source region and the drain region, it is preferable to dope the conductive impurities with an energy of 3 to 20 eV.

In addition, the step of forming the low concentration doped region is preferably doped with a conductive impurity of 50 ~ 100eV energy.

In addition, the source region, the drain region, and the lightly doped region are preferably formed by continuously doping conductive impurities of different energies in the same ion implantation chamber.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′.

1 and 2, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and the source region 153 and the drain region ( The polycrystalline silicon layer 150 including the 155 and the channel region 154 is formed.

Gate insulating patterns 140p and 140q are formed on the substrate 110 including the polysilicon layer 150. Gate lines 121 that extend in one direction are formed on the gate insulation patterns 140p and 140q, and a portion of the gate lines 121 extend to overlap the channel region 154 of the polysilicon layer 150. A portion of the overlapping gate line 121 is used as the gate electrode 124 of the thin film transistor. A lightly doped region 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and the polycrystalline silicon layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 to connect to an external circuit.

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 on which the gate line 121 and the storage electrode line 131 are formed. The first interlayer insulating layer 601 includes first and second contact holes 141 and 142 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or the branched portion of the data line 171 is connected to the source region 153 through the first contact hole 141 and the portion connected to the source region 153 is the source electrode 173 of the thin film transistor. Used. One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown).

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 142.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 143 exposing the drain electrode 173.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 143.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention described above will be described in detail with reference to the accompanying drawings.

3, 6, 8, 12, 14, and 16 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in Figs. 1 and 2, respectively, according to one embodiment of the present invention; 4, 7, 9, 13, 15, and 17 illustrate IV-IV thin film transistor array panels of FIGS. 3, 6, 8, 12, 14, and 16. FIG. 5 is a cross-sectional view taken along lines VII-VII IX-IX, XIII-XIII ', XV-XV', and XVII-XVII ', and FIG. 5 is a thin film transistor array panel of FIG. 4 is a cross-sectional view taken along the line IX-IX of the thin film transistor array panel of FIG. 8, and is a diagram taken in the next step of FIG. 9, and FIG. Is a cross-sectional view of the thin film transistor array panel taken along the line IX-IX and shown in the next step of FIG. 10.

First, as shown in FIGS. 3 and 4, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO 2) or silicon nitride (SiN x). An amorphous silicon film is deposited on the blocking layer 111 to form an amorphous silicon film.

Thereafter, the amorphous silicon film is crystallized into amorphous silicon through laser annealing, furnace annealing, or solid crystallization, and then patterned by photolithography to form a polysilicon layer 150.

Subsequently, as shown in FIG. 5, an insulating material such as silicon nitride or silicon oxide is deposited on the polycrystalline silicon layer 150 to form a gate insulating layer 140. Then, a gate metal layer 120 is formed by depositing a metal material such as molybdenum tungsten on the gate insulating layer 140, and then a photoresist layer is formed on the gate metal layer 120 and exposed and developed through a photomask pattern. 53, 54).

Next, as shown in FIGS. 6 and 7, the gate metal layer isotropically etched using the photoresist patterns 53 and 54 as a mask to form the gate electrode 121 having the gate electrode 124 and the storage electrode line having the storage electrode 133. 131 is formed.

The cut surfaces of the gate line 121 and the storage electrode line 131 are preferably formed to be inclined in order to increase the adhesion to the upper layer.

8 and 9, the gate insulating pattern is anisotropically etched using the photoresist patterns 53 and 54 as a mask to have a width slightly larger than that of the gate electrode 124 and the sustain electrode 133. (140p, 140q) are formed. In this case, the gate insulating patterns 140p and 140q are disposed between the polysilicon layer 150, the gate electrode 124, and the storage electrode 133, respectively, and the polysilicon layer, the gate electrode 124, and the storage electrode 133 are respectively disposed. At the same time as doping the conductive impurities to form the source region and the drain region to be described later, and also serves as an ion implantation mask.

Next, as shown in FIGS. 10 and 11, after removing the photoresist pattern, the source energy of the conductive impurities implanted in the same ion implantation chamber using the gate electrode 124 and the sustain electrode 133 as a mask is varied. The region 153, the drain region 154, and the lightly doped region 152 are formed.

Next, a method of forming the source region 153, the drain region 154, the channel region 154, and the lightly doped region 152 will be described in more detail.

First, the source region 153 and the drain region 155 may be scanned by first scanning N-type conductivity impurities at a high concentration using low energy using the gate insulation patterns 140p and 140q as masks in one ion implantation chamber. And a channel region 154. In this case, the channel region 154 is a polycrystalline silicon layer 150 under the gate electrode 124 and is not doped with impurities and separates the source region 153 and the drain region 155. Here, the low energy uses energy of 3 to 20 (eV).

Subsequently, in the first scanned ion implantation chamber, the second concentration of the N-type conductive impurities is low-concentrated using high energy using the gate electrode 124 and the sustain electrode 133 as masks to form the low-doped doping region 152. do. Here, the high energy uses energy of 50 to 100 (eV).

Next, as shown in FIGS. 12 and 13, an insulating material is stacked on the entire surface of the substrate to cover the polysilicon layer 150 to form a first interlayer insulating film 601. A first contact hole 141 and a second contact hole 142 exposing the source region 153 and the drain region 155 are formed in the first interlayer insulating layer 601 by a photolithography method.

As shown in FIGS. 14 and 15, a data metal film is formed on the first interlayer insulating layer 601 including the first contact hole 141 and the second contact hole 142 and then patterned to form a data line 171. ) And the drain electrode 175 are formed. The data line 171 is connected to the source region 153 through the first contact hole 141, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 142.

The data line 171 is formed by depositing a single layer of an aluminum-containing metal such as aluminum or aluminum neodymium (AlND) or a plurality of conductive materials including an aluminum alloy layer and a chromium (Cr) or molybdenum (Mo) alloy layer. After the film is formed, it is formed by patterning. The cut surfaces of the data line 171 and the drain electrode 173 are preferably formed to have a constant inclination for adhesion to the upper layer.

As shown in FIGS. 16 and 17, an insulating material is stacked on the first interlayer insulating layer 601 including the data line 171 and the drain electrode 175 to form a second interlayer insulating layer 602. Thereafter, a third contact hole 143 exposing the drain electrode 175 is formed in the second interlayer insulating layer 602 by a photolithography method.

1 and 2, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the inside of the third contact hole 143. This is then patterned to form a contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or the data line. The pixel electrode 190 is connected to the drain electrode 175 through the third contact hole 143. The contact auxiliary member may include a fourth contact hole (not shown) formed over the first and second interlayer insulating layers 601 and 602, the first and second interlayer insulating layers 601 and 102, and the gate insulating layer 140. It is connected to one end of the data line 171 and the gate line 121, respectively, through a fifth contact hole (not shown) formed over the gap.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, by forming the source region, the drain region, and the lightly doped region in a single process in the same ion implantation chamber, the process time can be shortened, thereby improving the yield of the product.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II, respectively.

3, 6, 8, 12, 14, and 16 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in Figs. 1 and 2, respectively, according to one embodiment of the present invention; The drawings are listed in the order of the process.

4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along the line IV-IV.

FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along the line VII-VII.

FIG. 9 is a cross-sectional view of the thin film transistor array panel of FIG. 8 taken along the line IX-IX.

FIG. 13 is a cross-sectional view of the thin film transistor array panel of FIG. 12 taken along the line XIII-XIII ′,

FIG. 15 is a cross-sectional view of the thin film transistor array panel of FIG. 14 taken along the line XV-XV ′. FIG.

FIG. 17 is a cross-sectional view of the thin film transistor array panel of FIG. 16 taken along the line XVII-XVII ′,

FIG. 5 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along the line IV-IV.

FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 8 taken along the line IX-IX.

FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 8 taken along the line IX-IX.

Claims (4)

Forming a polycrystalline silicon layer on the insulating substrate; Forming a gate insulating film on the polycrystalline silicon layer; Stacking a metal film on the gate insulating film; Forming a photoresist pattern on the metal layer, the photoresist pattern defining a region in which a gate line is formed; Forming a gate line having a gate electrode by patterning the metal layer by an isotropic etching process using the photoresist pattern as a mask; Patterning the gate insulating film by an anisotropic etching process using the photosensitive film pattern as a mask to form a gate insulating pattern, and then removing the photosensitive film pattern; Doping the polycrystalline silicon layer at a high concentration to form a source region, a drain region, and a channel region not doped with impurities; Forming a lightly doped region in the polycrystalline silicon layer; Forming a first interlayer insulating film covering the gate line and having first and second contact holes; Forming a data line having a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole on the first interlayer insulating layer; Forming a second interlayer insulating layer covering the data line and the drain electrode and having a third contact hole; Forming a pixel electrode on the second interlayer insulating layer, the pixel electrode being connected to the drain electrode through the third contact hole; The method of claim 1, wherein the forming of the source region and the drain region comprises doping the conductive dopant with low energy at a high concentration, and forming the low concentration doping region with the dopant using a high energy at low concentration. In claim 1, In the forming of the source region and the drain region, a method of manufacturing a thin film transistor array panel doped with a conductive impurity of 3 ~ 20eV energy. In claim 1, The method of claim 1, wherein the forming of the lightly doped region comprises doping conductive impurities with energy of 50 to 100 eV. In claim 1, The source region, the drain region, and the lightly doped region are formed by successively doping conductive impurities using different energies in the same ion implantation chamber.