KR20050048316A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on an insulating substrate, an insulating substrate, and is formed on a polycrystalline silicon layer having a source region, a channel region, a drain region, and a lightly doped region, a gate insulating film formed on the polycrystalline silicon layer, and a gate insulating film. A gate line including a gate electrode overlapping a portion of the lightly doped region, and a first interlayer insulating layer and a first interlayer insulating layer having first and second contact holes exposing source and drain regions, respectively; And a data line formed on the first interlayer insulating layer through the first contact hole, and formed on the drain electrode, the data line and the drain electrode connected to the drain area through the second contact hole and exposing the drain electrode. A second interlayer insulating film having a third contact hole, and formed on the second interlayer insulating film And a pixel electrode connected to the drain electrode through the third contact hole, wherein the gate insulating film is formed by sequentially stacking first, second and third insulating films, and the first insulating film covers the polysilicon layer. An insulating film is formed over the channel region between the lightly doped regions on the first insulating film, and the third insulating film partially overlaps the lightly doped region on the second insulating film.

Description

Thin film transistor array panel and manufacturing method thereof

     BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a method for manufacturing the same, and more particularly, to a thin film transistor array panel using polycrystalline silicon as a semiconductor layer and a method for manufacturing the same.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor array panel includes a scan signal line or gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like. It includes.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode which is a part of the gate line, a source electrode which is a part of the data line, and a drain electrode facing the source electrode around the semiconductor layer. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

In this case, the semiconductor layer is made of amorphous silicon, polycrystalline silicon, or the like, and the thin film transistor may be divided into a top gate method and a bottom gate method according to a position relative to the gate electrode. In the case of a polysilicon thin film transistor array panel, a top gate method in which a gate electrode is located above the semiconductor layer is mainly used.

The top gate method has the advantage of forming a driving circuit for operating the thin film transistor together with the thin film transistor in the pixel region because the driving speed of the thin film transistor is much faster than that of the bottom gate method. It is desirable to form a lightly doped region that partially overlaps the gate electrode between the channel region and the source and drain regions of the layer.

However, the method of forming a lightly doped region overlapping a portion of the gate electrode according to the prior art first forms a mask defining the first gate electrode on the semiconductor layer and defining the lightly doped region thereon. In addition, the process may be complicated by forming a low concentration doped region using a mask as an ion implantation mask and then forming a second gate electrode overlapping a portion of the low concentration doped region on the first gate electrode. In addition, the process time is lengthened thereby, the production yield is lowered.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a method of manufacturing the same, by forming a gate insulating layer capable of increasing capacitance while simplifying a process for forming a low concentration doped region.

In order to achieve the above object, the present invention provides the following thin film transistor array panel and its manufacturing method.

Specifically, a polycrystalline silicon layer formed on an insulating substrate, an insulating substrate and having a source region, a channel region, a drain region, and a lightly doped region, a gate insulating film and a gate insulating film formed on the polycrystalline silicon layer, A first interlayer insulating layer formed on the first interlayer insulating layer, the first interlayer insulating layer having a gate line including a gate electrode overlapping a portion thereof, and having a first and a second contact hole exposing a source region and a drain region, respectively; A third contact hole formed on the data line connected to the source region through the sphere and the first interlayer insulating layer and formed on the drain electrode, the data line and the drain electrode connected to the drain region through the second contact hole and exposing the drain electrode. The branch is formed on the second interlayer insulating film, the second interlayer insulating film and drains through the third contact hole. And a pixel electrode connected to the electrode, wherein the gate insulating film is formed by sequentially stacking first, second and third insulating films, and the first insulating film covers the polysilicon layer, and the second insulating film is formed on the first insulating film. A thin film transistor array panel is formed on the channel region between the lightly doped regions and the third insulating layer overlaps the lightly doped region on the second insulating layer.

Here, it is preferable that the 1st and 3rd insulating films are formed with the silicon oxide, and the 2nd insulating film is formed with the silicon nitride.

Alternatively, forming an amorphous silicon layer on the insulating substrate, crystallizing and patterning the amorphous silicon layer to form a polycrystalline silicon layer, forming a first insulating film covering the polycrystalline silicon layer on the polycrystalline silicon layer, first insulating film Stacking and patterning an insulating material thereon to form a second insulating film in which a portion of the polycrystalline silicon layer overlaps, forming a low concentration doped region by doping impurities to the polycrystalline silicon layer with a low concentration using the second insulating film as a mask; Stacking and patterning an insulating material on the insulating film to form a third insulating film overlapping a portion with the low concentration doped region, and doping the polycrystalline silicon layer with a high concentration of impurities using the third insulating film as a mask to obtain a source region, a channel region, and a drain. Forming a region, and then patterning the metal layer on the third insulating layer to form a lightly doped region Forming a gate line including the overlapping gate electrode, forming a first interlayer insulating film to cover the polysilicon layer, a data line and a drain region having a source electrode connected to the source region on the first interlayer insulating film; Forming a drain electrode to be connected; forming a second interlayer insulating film on the data line and the drain electrode; and forming a pixel electrode connected to the drain electrode on the second interlayer insulating film. Prepare.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′.

1 and 2, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and the source region 153 and the drain region ( 155, the polysilicon layer 150 including the channel region 154 and the lightly doped region 152 is formed.

A gate insulating layer 140 is formed on the substrate 110 including the polysilicon layer 150. At this time, the first insulating film 140p, the second insulating film 140q, and the third insulating film 140r are sequentially stacked on the gate insulating film 140. In this case, the first insulating layer 140p is made of silicon oxide (SiO ₂ ), the second insulating layer 140q is made of silicon nitride (SiNx) having a higher dielectric constant than silicon oxide, and the third insulating layer 140r is oxidized. Made of silicon (SiO ₂ ). That is, the gate insulating layer 140 has an oxide-nitride-oxide (ONO) structure formed by the first, second, and third insulating layers that are sequentially stacked, thereby increasing capacitance. As a result, the on current Ion value increases and the threshold voltage Vth value decreases, and the threshold voltage distribution can be maintained uniformly. Thus, the current driving capability of the pixel and circuit parts and the margin of low voltage driving can be maintained. Can be improved.

The first insulating layer 140p constituting the gate insulating layer 140 is formed on the blocking layer 111 and covers the polysilicon layer 150. The second insulating layer 140q is formed to overlap the channel region 154 on the first insulating layer 140q and does not overlap the lightly doped region 152. The third insulating layer 140r is formed on the second insulating layer 140q and overlaps a portion of the lightly doped region 152.

The gate line 121 is formed to extend in one direction on the gate insulating layer 140, and a portion of the gate line 121 extends to overlap the channel region 154 of the polysilicon layer 150. A portion of the gate line 121 is used as the gate electrode 124 of the thin film transistor. The gate electrode 124 overlaps the channel region 154 and the lightly doped region 152 of the polysilicon layer 150.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and the polycrystalline silicon layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 on which the gate line 121 and the storage electrode line 131 are formed. The first interlayer insulating layer 601 includes first and second contact holes 141 and 142 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or the branched portion of the data line 171 is connected to the source region 153 through the first contact hole 141 and the portion connected to the source region 153 is the source electrode 173 of the thin film transistor. Used. One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown).

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 142.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 143 exposing the drain electrode 173.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 143.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention described above will be described in detail with reference to the accompanying drawings.

3, 5, 9, 11, 13, and 15 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in Figs. 1 and 2, respectively, according to one embodiment of the present invention; 4, 6, 10, 12, 14, and 16 illustrate IV-IV thin film transistor array panels of FIGS. 3, 5, 9, 11, 13, and 15. FIG. 7 is a cross-sectional view taken along the line 'VI, VI-VI', XX, XII-XII ', XIV-XIV' and XVI-XVI ', and FIG. 7 illustrates the thin film transistor array panel of FIG. 6 is a cross-sectional view taken along the line of FIG. 6, and FIG. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI.

First, as shown in FIGS. 3 and 4, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO 2) or silicon nitride (SiN x). An amorphous silicon film is deposited on the blocking layer 111 to form an amorphous silicon film.

Thereafter, the amorphous silicon film is crystallized into amorphous silicon through laser annealing, furnace annealing, or solid crystallization, and then patterned by photolithography to form a polysilicon layer 150.

5 and 6, the first insulating film 140p is formed by depositing silicon oxide on the polycrystalline silicon layer 150. After the silicon nitride is deposited on the first insulating layer 140p, a photolithography process is performed to form the second insulating layer 140q.

Next, using the second insulating layer 140q as an ion implantation mask, the polycrystalline silicon layer 150 is doped with N-type conductive impurities at low concentration to form a low concentration doped region 152.

Subsequently, as illustrated in FIG. 7, silicon oxide is deposited on the second insulating layer 140q and then a photolithography process is performed to form a third insulating layer 140r partially overlapping the low concentration doped region 152. As a result, the gate insulating film 140 having the ONO structure in which the first, second, and third insulating films 140p, 140q, and 140r are stacked in this order is formed.

Subsequently, as shown in FIG. 8, the N-type conductive dopant is heavily doped into the polysilicon layer 150 using the third insulating layer 140r as an ion implantation mask, so that the source region 153 and the drain, which are highly doped regions, are drained. Regions 155 and channel regions 154 are formed. In this case, the channel region 154 is a polycrystalline silicon layer 150 under the gate electrode 124 and is not doped with impurities and separates the source region 153 and the drain region 155.

Next, as shown in FIGS. 9 and 10, a metal material such as molybdenum tungsten is deposited on the gate insulating layer 140 to form a gate conductive layer (not shown), and then a photolithography process is performed to form a lightly doped region 152. ) And a storage electrode line 131 having a gate electrode 121 having a gate electrode 124 partially overlapping each other) and a storage electrode 133.

The gate electrode 124 preferably does not overlap the source region 153 and the drain region 155. In addition, it is preferable that the cut surfaces of the gate line 121 and the storage electrode line 131 be formed to be inclined in order to increase adhesion with the upper layer.

As shown in FIGS. 11 and 12, an insulating material is stacked on the entire surface of the substrate to cover the polysilicon layer 150 to form a first interlayer insulating layer 601. A first contact hole 141 and a second contact hole 142 exposing the source region 153 and the drain region 155 are formed in the first interlayer insulating layer 601 by a photolithography method.

As shown in FIGS. 13 and 14, the data metal layer is formed on the first interlayer insulating layer 601 including the first contact hole 141 and the second contact hole 142 and then patterned to form a data line 171. ) And the drain electrode 175 are formed. The data line 171 is connected to the source region 153 through the first contact hole 141, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 142.

The data line 171 is formed by depositing a single layer of an aluminum-containing metal such as aluminum or aluminum neodymium (AlND) or a plurality of conductive materials including an aluminum alloy layer and a chromium (Cr) or molybdenum (Mo) alloy layer. After the film is formed, it is formed by patterning. The cut surfaces of the data line 171 and the drain electrode 173 are preferably formed to have a constant inclination for adhesion to the upper layer.

15 and 16, a second interlayer insulating layer 602 is formed by stacking an insulating material on the first interlayer insulating layer 601 including the data line 171 and the drain electrode 175. Thereafter, a third contact hole 143 exposing the drain electrode 175 is formed in the second interlayer insulating layer 602 by a photolithography method.

1 and 2, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the inside of the third contact hole 143. This is then patterned to form a contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or the data line. The pixel electrode 190 is connected to the drain electrode 175 through the third contact hole 143. The contact auxiliary member may include a fourth contact hole (not shown) formed over the first and second interlayer insulating layers 601 and 602, the first and second interlayer insulating layers 601 and 102, and the gate insulating layer 140. It is connected to one end of the data line 171 and the gate line 121, respectively, through a fifth contact hole (not shown) formed over the gap.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, each of the ONO films for forming the gate insulating film of the ONO structure is used as an ion implantation mask, thereby facilitating a low concentration doping region and a high concentration doping region source and drain regions without a separate ion implantation mask forming process. Can be formed.

In addition, by forming the gate insulating film in the ONO structure, the capacitance increases, thereby increasing the on-current value, lowering the threshold voltage value, and maintaining the distribution of the threshold voltage uniformly. The margin of current driving capability and low voltage driving can be improved.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II ',

3, 5, 9, 11, 13, and 15 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in Figs. 1 and 2, respectively, according to one embodiment of the present invention; The drawings are listed in the order of the process.

FIG. 4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along the line IV-IV '.

6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI '.

FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI ′, and is a diagram illustrating the next step in FIG. 6.

FIG. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI ′, and is a view of the next step of FIG. 7.

FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along the line X-X '.

FIG. 12 is a cross-sectional view of the thin film transistor array panel of FIG. 11 taken along the line XII-XII ′,

FIG. 14 is a cross-sectional view of the thin film transistor array panel of FIG. 13 taken along the line XIV-XIV ′.

FIG. 16 is a cross-sectional view of the thin film transistor array panel of FIG. 15 taken along the line XVI-XVI '.

Claims (4)

Insulation board, A polycrystalline silicon layer formed on the insulating substrate and having a source region, a channel region, a drain region, and a lightly doped region; A gate insulating film formed on the polycrystalline silicon layer, A gate line formed on the gate insulating layer and including a gate electrode partially overlapping the lightly doped region; A first interlayer insulating layer formed on the gate line and having first and second contact holes exposing the source region and the drain region, respectively; A data line formed on the first interlayer insulating layer and connected to the source region through the first contact hole; A drain electrode formed on the first interlayer insulating layer and connected to the drain region through the second contact hole; A second interlayer insulating layer formed on the data line and the drain electrode and having a third contact hole exposing the drain electrode, A pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode through the third contact hole; The gate insulating film is formed by sequentially stacking first, second and third insulating films, and the first insulating film covers the polysilicon layer, and the second insulating film is formed between the low concentration doped regions on the first insulating film. A thin film transistor array panel formed on the channel region, wherein the third insulating layer is formed to partially overlap the lightly doped region on the second insulating layer. In claim 1, The thin film transistor array panel of which the first and third insulating layers are formed of silicon oxide. In claim 1, And the second insulating film is formed of silicon nitride. Forming an amorphous silicon layer on the insulating substrate, Crystallizing and patterning the amorphous silicon layer to form a polycrystalline silicon layer, Forming a first insulating film on the polycrystalline silicon layer to cover the polycrystalline silicon layer, Stacking an insulating material on the first insulating film and then patterning the second insulating film to partially overlap the polycrystalline silicon layer; A low concentration doped region is formed by doping impurities in the polysilicon layer with a low concentration using the second insulating layer as a mask; Stacking and patterning an insulating material on the second insulating film to form a third insulating film overlapping a portion with the lightly doped region; Doping the polycrystalline silicon layer with a high concentration of impurities using the third insulating film as a mask to form a source region, a channel region and a drain region, Forming and forming a metal film on the third insulating film to form a gate line including a gate electrode partially overlapping the lightly doped region; Forming a first interlayer insulating film to cover the polycrystalline silicon layer, Forming a data line having a source electrode connected to the source region and a drain electrode connected to the drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line and the drain electrode; And forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer.