KR20040089292A - 반도체 패키지 및 그 제조방법 - Google Patents
반도체 패키지 및 그 제조방법 Download PDFInfo
- Publication number
- KR20040089292A KR20040089292A KR1020030023007A KR20030023007A KR20040089292A KR 20040089292 A KR20040089292 A KR 20040089292A KR 1020030023007 A KR1020030023007 A KR 1020030023007A KR 20030023007 A KR20030023007 A KR 20030023007A KR 20040089292 A KR20040089292 A KR 20040089292A
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- KR
- South Korea
- Prior art keywords
- semiconductor package
- solder balls
- semiconductor
- package
- side surfaces
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
Description
Claims (7)
- 리드가 없는 평판형 반도체 패키지에 있어서,적어도 둘이상의 반도체 패키지가 적층된 구조를 갖고, 상기 적어도 둘이상의 반도체 패키지는 측면부가 노출된 제 1 및 제 2단자부를 포함하는 반도체 패키지 몸체부; 및상기 노출된 제 1 및 제 2단자부의 측면부를 따라 각각이 부착된 복수의 제 1솔더볼과 복수의 제 2솔더볼을 구비하며,상기 복수의 제 1 및 제 2솔더볼은 서로 대응하여 결합되어 상기 적어도 둘 이상의 반도체 패키지를 전기적으로 결합시키는 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서,상기 복수의 제 1 및 제 2솔더볼은 리플로우 공정에 의해 상기 노출된 제 1 및 제 2단자부의 측면부를 따라 부착되는 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서,상기 복수의 제 1 및 제 2솔더볼은 리플로우 공정에 의해 상호 전기적으로 결합되는 것을 특징으로 하는 반도체 패키지.
- 리드가 없는 평판형 반도체 패키지를 제조하는 방법에 있어서,복수의 단자부를 갖는 리드프레임을 고정시키는 단계;접착부재를 개재하여 상기 리드프레임에 반도체 다이를 부착하는 단계;상기 반도체 다이와 상기 복수의 단자부를 와이어 본딩하는 단계;봉지제를 이용하여 상기 결과물의 전면을 몰딩하는 단계;상기 복수의 단자부의 측면부를 따라 복수의 제 1솔더볼이 전기적으로 결합된 제 1반도체 패키지를 형성하는 단계;상기의 단계를 반복수행하여 복수의 제 2솔더볼이 전기적으로 결합된 제 2반도체 패키지를 형성하는 단계; 및상기 제 1반도체 패키지의 상부에 상기 제 2반도체 패키지를 적층한 후 상기 복수의 제 1 및 제 2솔더볼을 대응하여 전기적으로 결합시키는 단계를 구비하는 것을 특징으로 하는 반도체 패키지 제조방법.
- 제 4 항에 있어서,상기 리드프레임은 접착부를 갖는 커버레이 필름에 고정되는 것을 특징으로 하는 반도체 패키지 제조방법.
- 제 4 항에 있어서,상기 복수의 제 1 및 제 2솔더볼은 리플로우 공정에 의해 상기 복수의 단자부의 측면부를 따라 부착되는 것을 특징으로 하는 반도체 패키지 제조방법.
- 제 4 항에 있어서,상기 복수의 제 1 및 제 2솔더볼은 리플로우 공정에 의해 상호 전기적으로 결합되는 것을 특징으로 하는 반도체 패키지 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020030023007A KR100967668B1 (ko) | 2003-04-11 | 2003-04-11 | 반도체 패키지 및 그 제조방법 |
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KR1020030023007A KR100967668B1 (ko) | 2003-04-11 | 2003-04-11 | 반도체 패키지 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR20040089292A true KR20040089292A (ko) | 2004-10-21 |
KR100967668B1 KR100967668B1 (ko) | 2010-07-07 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100843205B1 (ko) * | 2006-09-21 | 2008-07-02 | 삼성전자주식회사 | 반도체 패키지 및 적층형 반도체 패키지 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US11830746B2 (en) * | 2021-01-05 | 2023-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
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KR200182574Y1 (ko) * | 1997-12-30 | 2000-06-01 | 김영환 | 적층형 패키지 |
JP3625714B2 (ja) * | 1999-10-20 | 2005-03-02 | 株式会社三井ハイテック | 半導体装置 |
KR100347706B1 (ko) * | 2000-08-09 | 2002-08-09 | 주식회사 코스타트반도체 | 이식성 도전패턴을 포함하는 반도체 패키지 및 그 제조방법 |
DE10110203B4 (de) | 2001-03-02 | 2006-12-14 | Infineon Technologies Ag | Elektronisches Bauteil mit gestapelten Halbleiterchips und Verfahren zu seiner Herstellung |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100843205B1 (ko) * | 2006-09-21 | 2008-07-02 | 삼성전자주식회사 | 반도체 패키지 및 적층형 반도체 패키지 |
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