KR20040051713A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20040051713A KR20040051713A KR1020020078672A KR20020078672A KR20040051713A KR 20040051713 A KR20040051713 A KR 20040051713A KR 1020020078672 A KR1020020078672 A KR 1020020078672A KR 20020078672 A KR20020078672 A KR 20020078672A KR 20040051713 A KR20040051713 A KR 20040051713A
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- Prior art keywords
- film
- tungsten
- layer
- semiconductor device
- bit line
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 52
- 239000010937 tungsten Substances 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims abstract description 49
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 10
- 125000004430 oxygen atom Chemical group O* 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 18
- 239000002184 metal Substances 0.000 abstract description 18
- 230000004888 barrier function Effects 0.000 abstract description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000635 electron micrograph Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 라인 패턴을 형성하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method for forming line patterns of semiconductor devices.
전통적으로, 반도체 소자 제조시 게이트 전극(워드라인), 비트라인 등의 라인 패턴은 도핑된 폴리실리콘을 사용하여 형성해 왔다. 한편, 반도체 소자의 고집적가 급속하게 진행됨에 따라 도핑된 폴리실리콘으로는 저항 특성을 확보하는데 한계가 있어 실리사이드를 도입하게 되었다. 그러나, 이러한 실리사이드 역시 저항 특성을 확보하는데 그 한계에 직면하고 있으며, 이에 따라 텅스텐 등의 금속막을 사용하여 워드라인, 비트라인 등의 라인 패턴을 형성하는 기술이 제안되고 있다.Traditionally, line patterns such as gate electrodes (word lines) and bit lines have been formed using doped polysilicon in semiconductor device manufacturing. Meanwhile, as high integration of semiconductor devices proceeds rapidly, doped polysilicon has a limit in securing resistance characteristics, thereby introducing silicide. However, such silicides also face limitations in securing resistance characteristics. Accordingly, techniques for forming line patterns such as word lines and bit lines using metal films such as tungsten have been proposed.
통상적으로, 텅스텐막을 사용한 비트라인을 형성할 때, 베리어 금속막 증착/CVD 텅스텐막 증착/질화막 하드 마스크층 증착/텅스텐 하드 마스크층 증착/사진 식각 등의 공정을 진행하고 있다.Generally, when forming a bit line using a tungsten film, processes such as barrier metal film deposition, CVD tungsten film deposition, nitride film hard mask layer deposition, tungsten hard mask layer deposition, and photolithography are performed.
그러나, 소자의 집적도 증가에 따른 셀 피치 감소 및 비트라인간 간격의 감소로 인하여 기생 비트라인 캐패시턴스(Cb)가 증가하고, 이에 따라 소자의 동작 특성이 열화되는 문제점이 있었다. DRAM의 경우, 기생 비트라인 캐패시턴스(Cb)는 감지신호 마진의 확보를 위해서 가장 중요한 파라메터 중 하나이다.However, the parasitic bit line capacitance Cb increases due to a decrease in cell pitch and a decrease in gap between bit lines due to an increase in the degree of integration of the device, thereby degrading operation characteristics of the device. In the case of DRAM, the parasitic bit line capacitance (Cb) is one of the most important parameters for securing the sense signal margin.
따라서, 90nm급 이하의 비트라인 기술에서는 비트라인 자체의 저항은 낮은 상태로 유지하면서 낮은 기생 비트라인 캐패시턴스(Cb)를 확보하는 공정 기술의 개발이 중요한 과제로 대두되으며, 최근 이러한 연구 개발의 일환으로 비트라인을 이루는 도전층의 높이를 낮추고 단면적을 감소시키는 기술이 제안되고 있다.Therefore, the development of process technology that secures low parasitic bit line capacitance (Cb) while maintaining the resistance of the bit line itself in the 90-nm or smaller bit line technology has become an important task. As a result, a technique for reducing the cross-sectional area and decreasing the height of the conductive layer forming the bit line has been proposed.
도 1a 내지 도 1e는 종래의 반도체 소자의 비트라인 형성 공정을 설명하기 위한 각 공정별 단면도이다.1A to 1E are cross-sectional views of respective processes for describing a bit line forming process of a conventional semiconductor device.
종래기술에 따른 반도체 소자의 비트라인 형성 공정은, 우선 도 1a에 도시된 바와 같이 모스 트랜지스터(도시되지 않음)가 형성된 반도체 기판(10)상에 평탄화막(15)을 형성한 다음, 평탄화막(15)의 소정 부분, 예를 들어 모스 트랜지스터의 소오스, 드레인 영역(도시되지 않음)이 노출되도록 평탄화막(15)을 식각하여 콘택홀을 형성한다. 콘택홀 내에 공지의 방식으로 랜딩 플러그(20)를 형성한다. 그리고나서, 결과물 상에 실리콘 산화막 계열의 층간절연막(25)을 증착한다. 그후, 드레인 영역(도시되지 않음)과 콘택되는 랜딩 플러그(20)가 노출되도록 층간절연막(25)을 식각하여, 비트라인 콘택 영역(30)을 한정한다.In the bit line forming process of the semiconductor device according to the related art, first, as shown in FIG. 1A, a planarization film 15 is formed on a semiconductor substrate 10 on which a MOS transistor (not shown) is formed. The planarization layer 15 is etched to expose a predetermined portion of, for example, a source and a drain region (not shown) of the MOS transistor to form a contact hole. The landing plug 20 is formed in the contact hole in a known manner. Then, the silicon oxide film-based interlayer insulating film 25 is deposited on the resultant. Thereafter, the interlayer insulating film 25 is etched to expose the landing plug 20 contacting the drain region (not shown), thereby defining the bit line contact region 30.
이어서, 도 1b에 도시된 바와 같이 층간절연막(25) 및 비트라인 콘택 영역(30) 내부에 베리어 금속막(35)을 형성한 다음, 베리어 금속막(35) 상부에 CVD(chemical vapor deposition) 텅스텐막(40)을 증착한다.Subsequently, as shown in FIG. 1B, a barrier metal film 35 is formed inside the interlayer insulating film 25 and the bit line contact region 30, and then tungsten chemical vapor deposition (CVD) is formed on the barrier metal film 35. A film 40 is deposited.
다음으로, 도 1c에 도시된 바와 같이 CVD 텅스텐막(40) 및 베리어 금속막(35)을 에치백한다. 이때, 베리어 금속막(35)이 CVD 텅스텐막(40)에 비하여 더 많이 식각될 수 있다. 이러한 에치백 공정으로 CVD 텅스텐(40) 및 베리어 금속막(35)이 비트라인 콘택 영역(30)에만 잔류하게 된다.Next, as shown in FIG. 1C, the CVD tungsten film 40 and the barrier metal film 35 are etched back. At this time, the barrier metal film 35 may be etched more than the CVD tungsten film 40. In this etch back process, the CVD tungsten 40 and the barrier metal film 35 remain only in the bit line contact region 30.
계속하여, 도 1d에 도시된 바와 같이 결과물 상부에 비트라인용 텅스텐막(45)을 PVD(physical vapor deposition) 방식으로 증착하고, 비트라인용 텅스텐막(45) 상부에 질화막 하드 마스크층(50) 및 텅스텐 하드 마스크층(55)을 순차적으로 증착한다. 여기서, 텅스텐 하드 마스크층(55)은 PVD 방식으로 증착한다.Subsequently, as shown in FIG. 1D, the tungsten film 45 for the bit line is deposited on the resultant by physical vapor deposition (PVD), and the nitride film hard mask layer 50 is disposed on the tungsten film 45 for the bit line. And tungsten hard mask layer 55 are sequentially deposited. Here, the tungsten hard mask layer 55 is deposited by PVD method.
이어서, 도 1e에 도시된 바와 같이 비트라인 마스크를 이용한 사진 및 식각 공정을 통해 텅스텐 하드 마스크층(55), 질화막 하드 마스크층(50) 및 비트라인용 텅스텐막(45)을 식각하여 비트라인 구조물(60)을 형성한다. 이때, 비트라인구조물(60)을 형성하기 위한 식각 공정시, 비트라인용 텅스텐막(45)과 동일 물질로 이루어진 텅스텐 하드 마스크층(55)은 대부분 제거된다.Subsequently, as illustrated in FIG. 1E, the tungsten hard mask layer 55, the nitride film hard mask layer 50, and the bit line tungsten film 45 are etched through a photolithography and etching process using a bit line mask to form a bit line structure. Form 60. At this time, during the etching process for forming the bit line structure 60, the tungsten hard mask layer 55 made of the same material as the tungsten film 45 for the bit line is mostly removed.
그런데, 상기와 같은 종래의 비트라인 형성 공정은 낮은 기생 비트라인 캐패시턴스(Cb)를 구현할 수 있는 반면, 비트라인용 텅스텐막(45) 식각시 노출되는 하부층의 종류에 따라 비트라인용 텅스텐막(45)의 식각 프로파일이 크게 변동된다는 문제점을 가지고 있다. 특히, 비트라인용 텅스텐막(45)의 하부층으로 실리콘산화막 계열의 물질이 제공되는 경우, 식각시 발생한 산소에 의해 비트라인용 텅스텐막(45)의 측벽에 패시베이션된 폴리머(식각시 발생되는 부산물)가 제거됨으로써 측벽 식각이 증대된다. 이에 따라, 비트라인용 텅스텐막(45)이 도 1e와 같이 네가티브 슬로프를 갖게 되고, 심한 경우, 패턴 불량 또는 패턴 쓰러짐 현상이 발생될 수 있다.However, the conventional bit line forming process as described above may implement a low parasitic bit line capacitance Cb, while the tungsten film 45 for the bit line may vary depending on the type of the lower layer exposed during etching of the bit line tungsten film 45. ), There is a problem that the etching profile of) is greatly changed. In particular, when a silicon oxide film-based material is provided as a lower layer of the tungsten film 45 for the bit line, a polymer passivated on the sidewall of the tungsten film 45 for the bit line by oxygen generated during etching (by-product generated during etching). The sidewall etching is increased by eliminating. Accordingly, the tungsten film 45 for the bit line has a negative slope as shown in FIG. 1E, and in a severe case, a pattern defect or a pattern collapse phenomenon may occur.
도 2는 종래기술에 따라 형성된 텅스텐 비트라인의 단면 전자현미경 사진으로서, 텅스텐막이 네가티브 슬로프를 가지는 상태를 확인할 수 있다. 이러한 식각 프로파일의 열화는 장비 내에서의 공정 파라메터(예컨대, 식각 소오스 가스(SF6/N2)의 유량비, 파워 등)를 변동시키더라도 개선되지 않는다.2 is a cross-sectional electron micrograph of a tungsten bit line formed according to the prior art, it can be confirmed that the tungsten film has a negative slope. This deterioration of the etching profile is not improved even by changing the process parameters (eg, the flow rate ratio, power, etc. of the etching source gas SF 6 / N 2 ) in the equipment.
한편, 이러한 현상은 비단 비트라인 뿐만 아니라, 금속배선과 같은 라인 패턴 형성시에도 나타날 수 있다.On the other hand, such a phenomenon may occur not only in the bit line but also in the formation of a line pattern such as metal wiring.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 낮은 기생 캐패시턴스의 구현을 위하여 베리어 금속막을 매개로 하지 않고 층간절연막 상에 직접 텅스텐 라인 패턴을 형성하는 경우에 있어서, 라인 패턴 측벽이 네가티브 슬로프 형태로 식각되는 것을 방지할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and in the case of forming a tungsten line pattern directly on the interlayer insulating film without a barrier metal film for realizing low parasitic capacitance, the line pattern sidewalls It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing etching in the form of this negative slope.
도 1a 내지 도 1e는 종래의 반도체 소자의 비트라인 형성 공정을 설명하기 위한 각 공정별 단면도.1A to 1E are cross-sectional views of respective processes for explaining a bit line forming process of a conventional semiconductor device.
도 2는 종래기술에 따라 형성된 텅스텐 비트라인의 단면 전자현미경 사진.2 is a cross-sectional electron micrograph of a tungsten bit line formed according to the prior art.
도 3a 내지 도 3f는 본 발명의 일 실시예에 따른 반도체 소자의 제조 공정을 설명하기 위한 각 공정별 단면도.3A to 3F are cross-sectional views of respective processes for describing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
100 : 반도체 기판 115 : 층간절연막100 semiconductor substrate 115 interlayer insulating film
120 : 버퍼막 160 : 비트라인 구조물120: buffer film 160: bit line structure
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 실리콘산화막 계열의 층간절연막이 형성된 기판을 준비하는 단계; 상기 실리콘산화막 계열의 층간절연막 상부에 산소 원자를 포함하지 않는 버퍼막을 형성하는 단계; 상기 버퍼막 상부에 라인 패턴용 텅스텐막 및 하드 마스크막을 순차적으로 적층하는 단계; 및 상기 하드 마스크막 및 라인 패턴용 텅스텐막을 선택 식각하여 라인 패턴을 형성하는 단계를 포함하는 반도체 소자 제조방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, preparing a substrate on which a silicon oxide film-based interlayer insulating film is formed; Forming a buffer layer on the silicon oxide layer based interlayer insulating layer, the buffer layer including no oxygen atoms; Sequentially depositing a line pattern tungsten film and a hard mask film on the buffer film; And selectively etching the hard mask film and the tungsten film for line pattern to form a line pattern.
본 발명은 낮은 기생 캐패시턴스를 구현하기 위하여 베리어 금속막을 매개로 하지 않고 층간절연막 상에 직접 텅스텐 라인 패턴을 형성하는 경우에 있어서, 텅스텐막의 식각 과정에서 하부의 층간절연막(실리콘산화막 계열)이 노출되지 않도록 하기 위하여 층간절연막 상부에 버퍼층을 제공하는 것이다. 버퍼층으로는 실리콘질화막 등이 사용될 수 있다.In the present invention, when the tungsten line pattern is directly formed on the interlayer insulating film without using the barrier metal film to realize low parasitic capacitance, the lower interlayer insulating film (silicon oxide based) is not exposed during the etching process of the tungsten film. To provide a buffer layer on top of the interlayer insulating film. A silicon nitride film or the like may be used as the buffer layer.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 3a 내지 도 3f는 본 발명의 일 실시예에 따른 반도체 소자 제조 공정을 설명하기 위한 각 공정별 단면도이다.3A to 3F are cross-sectional views of respective processes for describing a semiconductor device manufacturing process according to an embodiment of the present invention.
본 실시예에 따른 반도체 소자의 제조 공정은, 먼저 도 3a에 도시된 바와 같이 모스 트랜지스터(도시되지 않음)가 형성된 반도체 기판(100)상에 평탄화막(105), 예를 들어 BPSG막을 형성하고, 평탄화막(105)의 소정 부분, 예를 들어 모스 트랜지스터의 소오스, 드레인 영역(도시되지 않음)이 노출되도록 평탄화막(105)을 식각하여 콘택홀을 형성한 다음, 콘택홀 내에 공지의 방식으로 랜딩 플러그(110)를 형성한다. 이어서, 결과물 상에 실리콘산화막 계열의 층간절연막(115)을 증착하고, 층간절연막(115) 상부에 산소 원자의 공급을 차단할 수 있는 버퍼막(120)을 증착한다. 이때, 층간절연막(115)으로는 HDP(high density plasma) 산화막이 사용될 수 있으며, 버퍼막(120)으로는 PECVD(plasma enhanced CVD) 또는 LPCVD(low pressure CVD) 방식으로 증착된 실리콘질화막을 사용하는 것이 바람직하다. 한편, 공정을 용이하게 하도록 버퍼막(120)의 두께는 약 200∼400Å 정도가 바람직하다. 이는 버퍼막(120)의 두께가 100Å 이하로 얇게 형성할 경우, 과도 식각 과정에서 버퍼막(120)이 바로 노출되어 층간절연막(115)이 노출될 우려가 있으며, 또 400Å 이상으로 두껍게 형성하면 공정 진행 및 소자 특성에 부담이 되기 때문이다.In the manufacturing process of the semiconductor device according to the present embodiment, first, as shown in FIG. 3A, a planarization film 105, for example, a BPSG film is formed on a semiconductor substrate 100 on which a MOS transistor (not shown) is formed. The planarization film 105 is etched to expose a predetermined portion of the planarization film 105, for example, a source and a drain region (not shown) of the MOS transistor, thereby forming a contact hole, and then landing in the contact hole in a known manner. The plug 110 is formed. Subsequently, a silicon oxide film-based interlayer insulating film 115 is deposited on the resultant, and a buffer film 120 capable of blocking the supply of oxygen atoms is deposited on the interlayer insulating film 115. In this case, a high density plasma (HDP) oxide film may be used as the interlayer insulating film 115, and a silicon nitride film deposited by plasma enhanced CVD (PECVD) or low pressure CVD (LPCVD) may be used as the buffer film 120. It is preferable. On the other hand, the thickness of the buffer film 120 is preferably about 200 to 400 kPa to facilitate the process. If the thickness of the buffer layer 120 is less than 100 GPa, the buffer layer 120 may be directly exposed during the excessive etching process, and the interlayer insulating layer 115 may be exposed. This is because a burden is placed on progress and device characteristics.
다음으로, 도 3b에 도시된 바와 같이 드레인 영역(도시되지 않음)과 콘택되는 랜딩 플러그(110)가 노출되도록 버퍼막(120) 및 층간절연막(115)을 식각하여,비트라인 콘택 영역(125)을 한정한다.Next, as illustrated in FIG. 3B, the buffer layer 120 and the interlayer insulating layer 115 are etched to expose the landing plug 110 contacting the drain region (not shown), thereby forming the bit line contact region 125. To qualify.
이어서, 도 3c에 도시된 바와 같이 버퍼막(120) 및 비트라인 콘택 영역(125) 내부에 베리어 금속막(130)을 형성한 다음, 베리어 금속막(130) 상부에 CVD(chemical vapor deposition) 텅스텐막(135)을 증착하고, 공지의 방식으로 열처리를 수행한다.Subsequently, as shown in FIG. 3C, a barrier metal layer 130 is formed in the buffer layer 120 and the bit line contact region 125, and then tungsten chemical vapor deposition (CVD) is formed on the barrier metal layer 130. The film 135 is deposited and heat treated in a known manner.
계속하여, 도 3d에 도시된 바와 같이 CVD 텅스텐막(135) 및 베리어 금속막(130)을 에치백하여 CVD 텅스텐막(135) 및 베리어 금속막(130)이 비트라인 콘택 영역(125) 내에 잔류되도록 한다. 이때, 에치백 공정을 대신하여 CMP(chemical mechanical polishing) 또는 에치백/CMP 혼합 방식이 이용될 수 있고, 평탄화 공정시 버퍼막(120)이 잔류하도록 한다. 여기서, 잔류된 CVD 텅스텐막(135) 및 베리어 금속막(130)은 비트라인 콘택 패드가 된다.Subsequently, as shown in FIG. 3D, the CVD tungsten film 135 and the barrier metal film 130 are etched back so that the CVD tungsten film 135 and the barrier metal film 130 remain in the bit line contact region 125. Be sure to In this case, instead of the etch back process, chemical mechanical polishing (CMP) or an etch back / CMP mixed method may be used, and the buffer layer 120 remains during the planarization process. Here, the remaining CVD tungsten film 135 and the barrier metal film 130 become bit line contact pads.
다음으로, 도 3e에 도시된 바와 같이 결과물 상부에 비트라인용 텅스텐막(140)을 PVD 방식으로 형성한다. 비트라인용 텅스텐막(140) 상부에 질화막 하드 마스크층(145) 및 텅스텐막 하드 마스크층(150)을 순차적으로 증착한다. 여기서, 질화막 하드 마스크층(145) 및 텅스텐막 하드 마스크층(150)은 식각 특성이 유사한 다른 물질(단일막 포함)로 대체할 수 있다.Next, as shown in FIG. 3E, a tungsten film 140 for bit lines is formed on the resultant by PVD method. The nitride film hard mask layer 145 and the tungsten film hard mask layer 150 are sequentially deposited on the bit line tungsten film 140. Here, the nitride hard mask layer 145 and the tungsten hard mask layer 150 may be replaced with another material (including a single layer) having similar etching characteristics.
계속하여, 도 3f에 도시된 바와 같이 비트라인 마스크를 사용한 사진 및 식각 공정을 통해 텅스텐막 하드 마스크층(150), 질화막 하드 마스크층(145) 및 비트라인용 텅스텐막(140)을 식각하여 비트라인 구조물(60)을 형성한다. 이때, 텅스텐 식각 가스로는 SF6/N2가스를 사용하며, 10mTorr의 압력에서 식각 장비의 상부 파워는 636W로 하고, 하부 파워는 45W로 하여 식각을 진행하는 것이 바람직하다. 또한, 질화막 식각 가스로는 Cl2가스, BCl3가스 등을 사용하는 것이 바람직하다.Subsequently, as illustrated in FIG. 3F, the tungsten film hard mask layer 150, the nitride film hard mask layer 145, and the bit line tungsten film 140 may be etched through a photolithography and etching process using a bit line mask. The line structure 60 is formed. In this case, SF 6 / N 2 gas is used as the tungsten etching gas, and the etching process is performed at an upper pressure of 636 W and a lower power of 45 W at a pressure of 10 mTorr. In addition, it is preferable to use a Cl 2 gas, a BCl 3 gas, or the like as the nitride film etching gas.
상기와 같은 공정을 진행하여 비트라인을 형성하는 경우, 비트라인용 텅스텐막(140) 식각시, 버퍼층(120)의 도입에 의해 비트라인용 텅스텐막(140) 하부에 산소 원자를 제공하는 층이 존재하지 않으므로, 즉, 산소 원자 공급을 차단하므로써, 비트라인 구조물(60) 측벽의 폴리머가 제거되지 않으며, 이에 따라 비트라인용 텅스텐막(140)이 정상적인 식각 프로파일을 갖게 된다.When the bit line is formed by the above process, when the bit line tungsten film 140 is etched, a layer providing oxygen atoms under the bit line tungsten film 140 is introduced by the buffer layer 120. Since it does not exist, that is, by blocking the supply of oxygen atoms, the polymer on the sidewalls of the bitline structure 60 is not removed, so that the tungsten film 140 for the bitline has a normal etching profile.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
예컨대, 전술한 실시예에서는 버퍼층으로 실리콘질화막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 실리콘질화막을 대신하여 산소를 포함하지 않는 다른 절연막을 사용하는 경우에도 적용된다.For example, in the above-described embodiment, the case where the silicon nitride film is used as the buffer layer has been described as an example. However, the present invention is also applied to the case where another insulating film containing no oxygen is used in place of the silicon nitride film.
또한, 전술한 실시예에서는 비트라인 형성 공정을 일례로 들어 설명하였으나, 본 발명은 텅스텐 금속배선 형성 공정에도 적용할 수 있다.In addition, in the above-described embodiment, the bit line forming process has been described as an example, but the present invention can also be applied to the tungsten metal wiring forming process.
또한, 전술한 실시예에서는 베리어 금속막/CVD 텅스텐막을 사용하여 콘택 패드를 형성하는 공정을 포함하는 경우를 일례로 들어 설명하였으나, 콘택 패드의 유무는 본 발명의 기술적 원리와 직접적인 연관이 없다.In addition, in the above-described embodiment, a case of forming a contact pad using a barrier metal film / CVD tungsten film is described as an example, but the presence or absence of the contact pad is not directly related to the technical principle of the present invention.
전술한 본 발명은 낮은 라인 캐패시턴스를 확보하면서 텅스텐 비트라인의 식각 프로파일을 확보할 수 있으며, 이에 따라 반도체 소자의 신뢰도를 높이는 효과가 있다.The present invention described above can secure the etching profile of the tungsten bit line while ensuring a low line capacitance, thereby increasing the reliability of the semiconductor device.
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| KR19990086473A (en) * | 1998-05-28 | 1999-12-15 | 김영환 | Wiring Formation Method of Semiconductor Device |
| KR100587037B1 (en) * | 1999-10-28 | 2006-06-07 | 주식회사 하이닉스반도체 | Semiconductor apparatus forming method |
| KR100370241B1 (en) * | 2000-10-31 | 2003-01-30 | 삼성전자 주식회사 | Conducting line of semiconductor device using aluminum oxide as a hard mask and manufacturing method thereof |
| KR100546092B1 (en) * | 2000-12-12 | 2006-01-24 | 주식회사 하이닉스반도체 | Contact hole formation method of semiconductor device |
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