KR20040021394A - A contact portion of a wires, a method for manufacturing the contact portion, a thin film transistor array panel including the contact portion, and a method for manufacturing the panel - Google Patents

Abstract

PURPOSE: An interconnection contact structure, a method of forming the structure, a thin film transistor array substrate including the interconnection contact structure, and a method of fabricating the array substrate are provided to form an interconnection contact part of a material having a low resistance. CONSTITUTION: An interconnection contact structure includes an interconnection line(11), an insulating layer(12), and a conductive layer(14). The interconnection line is formed on a substrate(10) and includes a lower layer(111) and an upper layer(112). The lower layer is formed of a conductive material that is dry-etched. The upper layer is formed of aluminum or aluminum alloy on the lower layer. The boundary of the upper layer is located on the lower layer. The insulating layer has a contact hole(13) that exposes the interconnection line. The conductive layer is formed of IZO on the insulating layer and connected to the lower layer of the interconnection line through the contact hole.

Description

A contact portion of a wiring, a method of manufacturing the same, and a thin film transistor array substrate including the same, and a method of manufacturing the same MANUFACTURING THE PANEL}

The present invention relates to a contact portion of a wiring, a method of manufacturing the same, and a thin film transistor array substrate including the same, and a method of manufacturing the same.

In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.

In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since the wiring of aluminum or aluminum alloy has a weak physical or chemical property, corrosion occurs when the contact portion is connected to another conductive material, thereby deteriorating the characteristics of the semiconductor device. In particular, when the pixel electrode is formed using indium tin oxide (ITO), which is a transparent conductive material, as in a liquid crystal display device, the wiring of aluminum or an aluminum alloy is corroded at the contact portion that contacts the wiring of the ITO and aluminum or an aluminum alloy. This happens. In order to solve this problem, a technique of forming a pixel electrode using IZO, which does not cause corrosion even when contacted with aluminum-based wiring instead of ITO, has been developed.However, in the case of using IZO, there is a problem of increasing contact resistance at the contact portion. have. In order to solve this problem, a method of interposing a conductive material having excellent contact properties with IZO or ITO has been developed, but there is a problem in that a manufacturing process is complicated and manufacturing cost increases due to the addition of a photolithography process.

On the other hand, in the manufacturing method of the liquid crystal display device, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a contact portion of a wiring made of a low resistance material and having a low resistance contact characteristic and a method of manufacturing the same.

Another object of the present invention is to provide a thin film transistor array substrate including a contact portion of a wiring having excellent contact characteristics and a method of manufacturing the same.

Another object of the present invention is to simplify a method of manufacturing a thin film transistor array substrate including a contact portion of a wiring having excellent contact characteristics.

1A and 1B are diagrams showing a contact structure of a wiring in an embodiment of the present invention,

2 is a cross-sectional view showing a method for manufacturing a contact structure of a wire according to an embodiment of the present invention;

3 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

4 is a cross-sectional view of the thin film transistor substrate of FIG. 3 taken along the line III-III;

5A, 6A, 7A, and 8A are layout views of a thin film transistor substrate, illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof;

5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A and is a cross-sectional view showing the next step in FIG. 7B;

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

10 and 11 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 9 taken along lines X-X 'and XI-XI',

12A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

12B and 12C are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively.

13A and 13B are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, and are cross-sectional views in the next steps of FIGS. 12B and 12C;

FIG. 14A is a layout view of a thin film transistor substrate at a next step of FIGS. 13A and 13B;

14B and 14C are cross-sectional views taken along the lines XIVb-XIVb ′ and XIVc-XIVc ′ in FIG. 14A, respectively.

15A, 16A, 17A and 15B, 16B, 17B are cross-sectional views taken along lines XIVb-XIVb 'and XIVc-XIVc', respectively, in FIG. 14A, showing the following steps in the order of the process. ,

18A is a layout view of a thin film transistor substrate at a next step of FIGS. 17A and 17B,

18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIc-XVIIc' in FIG. 18A, respectively.

In order to solve this problem, in the present invention, the wiring has a low contact resistance with IZO, and the lower layer of the conductive material capable of dry etching and the upper layer of the conductive material having a low resistivity, such as aluminum or an aluminum alloy, are sequentially stacked. The lower layer is patterned by wet etching to form an undercut under the photoresist pattern, and the lower layer is patterned by dry etching to expose the lower layer out of the upper layer to contact the IZO and the lower layer.

At this time, the lower layer is preferably made of chromium.

The contact portion of the wiring can also be applied to the thin film transistor array substrate and its manufacturing method.

More specifically, in the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode connected to the gate line is formed on the insulating substrate, and a semiconductor layer is formed on the gate insulating film covering the gate wiring. . A data line including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode separated from and facing the source electrode is formed on the semiconductor layer or the gate insulating layer, and a protective film covering the semiconductor layer is formed thereon. Formed. An upper portion of the passivation layer is made of IZO, and a conductive layer connected to the gate line or the data line is formed through the contact hole of the passivation layer.

In this case, the gate wiring or the data wiring includes a lower layer made of a conductive material capable of dry etching and an upper layer made of aluminum or aluminum alloy and having a boundary line positioned on the lower layer, wherein the conductive layer is at least outside the upper layer through the contact hole. It is in contact with the exposed underlayer.

It is preferable that the lower film is made of chromium, and the thickness of the lower film is preferably 500 kPa or less.

The gate line may include a gate pad configured to receive a scan signal from the outside and transmit the scan signal to the gate line, and the data line may include a data pad configured to transfer the image signal from the outside to the data line. The contact hole may include a drain electrode, First and third contact holes exposing the gate pad or the data pad, wherein the conductive layer is connected to the drain electrode, the gate pad, or the data pad through the first to third contact holes, respectively, the auxiliary gate pad or It may include an auxiliary data pad.

The semiconductor layer except for the channel portion between the source and drain electrodes may have the same shape as the data line.

In the method of manufacturing a thin film transistor array substrate according to the present invention, a gate line including a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line is formed on the insulating substrate. Subsequently, a semiconductor layer pattern is formed on the gate insulating layer covering the gate wiring, and the data line extends in the vertical direction crossing the gate line, the source electrode connected to the data line, the drain electrode separated from the source electrode, and the data. A data line including a data pad connected to a line is formed. Subsequently, a protective layer covering the semiconductor layer pattern and having a contact hole exposing the gate wiring or data wiring is formed, and an IZO is stacked and patterned thereon to form a conductive layer connected to the gate wiring or data wiring through the contact hole. do. In this case, the gate wiring or the data wiring is formed by sequentially stacking and patterning a lower layer made of a conductive material capable of dry etching and an upper layer made of aluminum or an aluminum alloy.

In this case, the gate line and the data line forming step may be performed by a photolithography process using a photoresist pattern, the upper layer may be etched by wet etching, and the lower layer may be etched by dry etching.

The lower layer is preferably formed of chromium and has a thickness of 500 kPa or less.

The method may further include forming a contact layer pattern between the semiconductor layer pattern and the data line. The data line and the semiconductor layer pattern may be formed through a photolithography process using a single photoresist pattern, and the photoresist pattern may include a source electrode and a drain. It is preferable to include a first portion having a first thickness, a second portion having a thickness thicker than the first thickness, and a third portion having a thickness thinner than the first portion, which is located in the channel portion between the electrodes.

It is preferable to form the photosensitive film pattern using one mask.

In order to form the gate insulating film, the semiconductor layer pattern, the contact layer pattern, and the data wirings, first, the gate insulating film, the semiconductor layer, the contact layer, and the lower film and the upper film are sequentially stacked, and a photosensitive film is coated on the upper film. Subsequently, the photoresist film is exposed and developed through a mask to form a photoresist pattern such that the second portion is positioned above the data line, and then the upper and lower layers under the third portion, the contact layer and semiconductor layer, and the lower portion under the third portion. The thicknesses of the first layer, the upper layer and the lower layer, the contact layer, and the thicknesses of the second portion are etched to form data wirings, contact layer patterns, and semiconductor layer patterns each consisting of the lower layer, the upper layer, the contact layer, and the semiconductor layer. Form.

More specifically, in order to form the data wiring, the contact layer pattern, and the semiconductor layer pattern, the upper layer under the third part is wet etched and the lower layer is dry etched to expose the contact layer. Subsequently, the contact layer under the third portion and the semiconductor layer under the third portion are dry-etched together with the first portion to expose the gate insulating film under the third portion and the upper layer under the first portion to complete a semiconductor layer pattern composed of a semiconductor layer. . Subsequently, the upper layer and the lower layer under the first portion are wet-etched to complete the data wiring, and the contact layer under the first portion is etched to complete the contact layer pattern.

In this case, the second portion may be removed between the etching of the upper layer and the etching of the lower layer.

Then, a person having ordinary knowledge in the technical field to which the present invention belongs with respect to the contact portion of the wiring according to the embodiment of the present invention, the manufacturing method thereof, the thin film transistor array substrate including the same, and the manufacturing method thereof with reference to the accompanying drawings. It demonstrates in detail so that implementation may be carried out easily. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a contact portion of a wiring, a method of manufacturing the same, a thin film transistor array substrate including the same, and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the drawings.

1A and 1B show a contact portion of a wire in an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a manufacturing method of a contact portion of a wire according to an embodiment of the present invention.

As a semiconductor device, especially a wiring for transmitting a signal, a metal material of aluminum or aluminum alloy having a low resistivity of 15 μΩcm or less is suitable to minimize signal delay. In this case, the wiring should be connected to another conductive layer in order to receive a signal from the outside or to transmit a signal to the outside, and the contact resistance at the contact portion should be small when contacting the other conductive material in the manufacturing process. To this end, in the contact portion of the wiring according to the embodiment of the present invention, the wiring 11 formed on the substrate 10 has a low contact resistance with IZO such as chromium or molybdenum or molybdenum alloy as shown in FIGS. 1A and 1B. And a lower layer 111 of a conductive material capable of dry etching at the same time and an upper layer 112 made of aluminum or an aluminum alloy having low resistance. The insulating film 12 covering the wiring 11 has a wiring hole 11, in particular, a contact hole 13 exposed by a part of the lower film 111 exposed out of at least the upper film 112 of the wiring 11. The conductive layer 14 made of IZO is formed on the upper portion of the 12 through the contact hole 13 in contact with the wiring 11, in particular, the lower film 111 of the wiring 11.

At this time, the conductive layer 14 of the lower layer 111 exposed from the contact hole 13 can be prevented from being disconnected due to the step of the contact hole 13 or the under-cut under the wiring 11. It is preferable to form the contact hole 13 so that the distance between the boundary line and the boundary line of the contact hole 13 adjacent thereto does not deviate from the range of 2 占 퐉. In the manufacturing method of the contact structure of the wiring according to the embodiment of the present invention, as shown in FIG. 2, first, the lower layer 111 of chromium or molybdenum or molybdenum alloy and the upper portion of aluminum or aluminum alloy on the substrate 10. The film 112 is sequentially stacked, and the photosensitive film pattern 200 for wiring is formed on the upper film 112. Subsequently, the upper layer 112 is etched by wet etching using an etchant using the photoresist pattern 200 as an etch mask, and the upper layer 112 is patterned under the photoresist pattern 200 to be undercut. Subsequently, the lower layer 111 is etched by dry etching using the photoresist pattern 200 as an etching mask. Then, the edge portion of the lower layer 111 is exposed out of the upper layer 112. At this time, in order to apply dry etching when the lower layer 111 is chromium, it is preferable to have a thickness of about 500 kV or less, more preferably about 300 kPa. Here, when the lower layer 111 of the wiring 11 is formed of a conductive material capable of dry etching, another layer is added to the lower portion of the lower layer 111 and patterned by dry etching, for example, a semiconductor layer made of silicon. In addition, when the semiconductor layer is patterned by dry etching by applying the same etching conditions as those of the lower layer 111, the manufacturing process may be simplified, and a method of manufacturing the thin film transistor substrate according to the second embodiment will be described later. Let's explain.

Subsequently, the insulating film 12 covering the wiring 11 is stacked, and the contact hole 13 is formed by patterning the insulating film 12 by a photolithography process using a mask. In this case, the contact hole 13 is formed so that the lower layer 111 is exposed. Subsequently, the IZO is laminated and patterned to form a conductive layer 14 in contact with the wiring 11, particularly the exposed lower layer 111, through the contact hole 13.

Such a contact portion of the wiring and the manufacturing method thereof can be applied to the thin film transistor for a liquid crystal display device and the manufacturing method thereof.

Next, a thin film transistor array substrate and a manufacturing method for a liquid crystal display including the contact portion of the wiring according to the present invention will be described in detail with reference to the drawings.

First, the structure of the thin film transistor array substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor array substrate shown in FIG. 3 taken along the line IV-IV '.

A gate wiring is formed on the insulating substrate 110 including a lower layer 201 made of a conductive material having good contact properties with IZO and dry etching and an upper layer 202 of aluminum or an aluminum alloy having low resistance. The gate wiring is connected to the gate line 121 and the gate line 121 extending in the horizontal direction and connected to the gate pad 125 and the gate line 121 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 123 of the thin film transistor. In this case, the lower layer 201 is exposed outside the upper layer 202.

Here, the gate wirings 121, 123, and 125 may be formed of a single layer of silver or silver alloy or aluminum or aluminum alloy.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate lines 121, 125, and 123.

A semiconductor layer 150 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 140 of the gate electrode 125, and n + is heavily doped with silicide or n-type impurities on the semiconductor layer 150. Resistive contact layers 163.165 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the ohmic contact layers 163 and 165 or the gate insulating layer 140, aluminum or aluminum having a low resistance and a lower layer 701 made of a conductive material having good contact properties with IZO, such as chromium, molybdenum or molybdenum alloy, and having dry etching. The data wiring including the upper film 702 of the alloy is formed. The data line is formed in a vertical direction and is connected to the data line 171 and the data line 171 defining the pixel by crossing the gate line 121 and extending to an upper portion of the ohmic contact layer 163. 173, the data pad 179 connected to one end of the data line 171 and separated from the source electrode 173 and receiving the image signal from the outside, and the source electrode 173 with respect to the gate electrode 123. And a drain electrode 175 formed on the opposite ohmic contact layer 165. At this time, like the gate lines 123, 121, and 125, the lower layer 701 of the data lines 171, 173, 175, and 179 is exposed outside the upper layer 702.

The data wires 171, 173, 175, and 179 are preferably formed of a single film of aluminum or aluminum alloy, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having a low contact resistance with other materials, especially IZO. Examples include Al (or Al alloys) / Cr or Al (or Al alloys) / Mo (or Mo alloys), and the like. In an embodiment of the present invention, the data wires 171, 173, 175, and 179 are made of chromium. It consists of a double film of the lower film 701 of and the upper film 702 of aluminum-neodymium alloy.

The data lines 171, 177, 173, 175, and 179 and the semiconductor layer 150 that do not cover them are formed by an organic material having excellent planarization characteristics, a photosensitive property, or a plasma enhanced chemical vapor deposition (PECVD) method, and a-Si. A protective film 180 made of silicon nitride as an inorganic material or a low dielectric constant CVD film including a: C: O film or an a-Si: O: F film or the like is formed.

In the passivation layer 180, contact holes 185 and 189 respectively exposing the drain electrode 175 and the data pad 179 are formed, and the contact holes 182 exposing the gate pad 125 together with the gate insulating layer 140. Is formed. In this case, the contact holes 182, 185, and 189 are formed to expose at least some of the boundary lines of the gate pad 125, the drain electrode 175, and the lower layers 201 and 701 of the data pad 179.

A pixel electrode 190 made of IZO is formed on the passivation layer 180 through the contact hole 185 and electrically connected to the drain electrode 175 and positioned in the pixel. In this case, the pixel electrode 190 is in contact with the lower layer 701 of the drain electrode 175 exposed from the contact hole 185 with a sufficiently large area, thereby minimizing contact resistance of the contact portion. In addition, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 are formed on the passivation layer 180 through the contact holes 187 and 189, respectively. In this case, the gate pad 125 and the data pad 179 and the lower layers 201 and 701 are exposed to the outside of the upper layers 202 and 702 so that the auxiliary gate pad 92 and the auxiliary data pad 97 have a lower area. Contacts with membranes 201 and 701. Therefore, the contact resistance of the contact portion can be minimized.

3 and 4, the pixel electrode 190 overlaps the gate line 121 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 190 is disposed on the same layer as the gate lines 121, 125, and 123. It is also possible to add a storage capacitor wiring.

Next, a method of manufacturing the TFT array substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4 and FIGS. 5A to 8B.

First, as shown in FIGS. 5A and 5B, the lower layer 201 of a conductive material having excellent contact properties with IZO, such as chromium, molybdenum or molybdenum alloy, etc., on the substrate 110 and the upper portion of aluminum or an aluminum alloy having low resistance. The films are stacked and patterned by sputtering to a thickness of about 500 mW and 2,500 m, respectively, to form a gate line including the gate line 121, the gate electrode 123, and the gate pad 125. Here, in the patterning of the gate wirings 121, 123, and 125, as described above, the photoresist film pattern 220 for the gate wiring is formed on the upper layer 702, and then aluminum or an aluminum alloy is first used as an etching mask. An aluminum etchant used for etching, using the top layer 202 using CH ₃ COOH (8-15%) / HNO ₃ (5-8%) / H ₃ PO ₄ (50-60%) / H ₂ O (rest). Wet). At this time, the wet etching proceeds isotropically, and undercut occurs in the lower portion of the photoresist pattern 220. Subsequently, the lower layer 201 is patterned by dry etching using the gate wiring photoresist pattern 220 as an etching mask. Then, the dry etching proceeds anisotropically so that the edge portion of the lower layer 201 is exposed out of the upper layer 202.

Next, as shown in FIGS. 6A and 6B, three layers of the gate insulating layer 140 made of silicon nitride, the semiconductor layer 150 made of amorphous silicon, and the doped amorphous silicon layer 160 are successively stacked, and a mask is formed. The semiconductor layer 150 and the ohmic contact layer 160 are formed on the gate insulating layer 140 facing the gate electrode 125 by patterning the semiconductor layer 150 and the doped amorphous silicon layer 160 by the patterning process. do. Here, the gate insulating film 140 is preferably formed by laminating silicon nitride in a thickness of about 2,000 to 5,000 Pa at a temperature range of 250 to 500 ° C.

Next, as shown in FIGS. 7A to 7B, the lower film 701 of chromium has a thickness of about 500 GPa and Al-Nd containing 2 at% of Nd in the aluminum or aluminum alloy metal having low resistance. The upper layer 602 was sequentially stacked by sputtering at a temperature of about 150 ° C. to about 2,500 μm using an alloy target, and then patterned by a photolithography process using a photosensitive film pattern 200 for data wiring to form a gate line. The data line 171 crossing the 121 and the source electrode 173 connected to the data line 171 and extending to the upper portion of the gate electrode 123, and the data line 171 are connected to one end of the data pad ( 179, a conductive pattern 177 for the storage capacitor that is separated from the source electrode 177 and overlaps the drain electrode 175 facing the source electrode 173 and the gate line 121 around the gate electrode 123. ) And data with tapered structure Form the wiring. The etching condition is the same as the etching condition for forming the gate wiring.

Subsequently, the doped amorphous silicon layer pattern 160, which is not covered by the data wires 171, 173, 175, and 179, is etched and separated from both sides of the gate electrode 123, while the doped amorphous silicon layers ( The semiconductor layer pattern 150 between 163 and 165 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 150, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 8A and 8B, a low dielectric constant including an a-Si: C: O film or an a-Si: O: F film or the like coated with an organic material having excellent planarization properties and photosensitivity Insulating material is deposited by plasma enhanced chemical vapor deposition (PECVD) or silicon nitride, which is an inorganic material, to form a passivation layer 180 and patterned by dry etching together with the gate insulating layer 140 by a photolithography process using a mask. In addition, contact holes 182, 185, and 189 are formed to expose the gate pad 125, the drain electrode 175, and the data pad 179, respectively. The contact holes 182, 185, and 189 are formed to expose the drain electrodes 175, the gate pads 125, and the lower layers 201 and 701 of the data pads 179. In this case, a portion of the gate insulating layer 140 may be etched in the contact holes 182, 185, and 189 to expose the substrate 110. In this way, the pixel electrode 190, the auxiliary gate pad 92 and the auxiliary data pad 97 and the drain electrode 175, the gate pad 125 and the data formed later in the contact holes 182, 185 and 189 are formed. When the pads 179 are in contact with each other, the contact resistance between the lower layer 701 and the IZO layers 190, 97, and 92 of those having excellent contact properties with other materials can be minimized. At the same time, the contact area can be maximized.

Next, as shown in FIGS. 3 and 4, the IZO film is laminated by sputtering and patterned using a mask to contact the pixel electrode 190 and the contact hole connected to the drain electrode 175 through the contact hole 185. An auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179, respectively, are formed through 182 and 189. In this case, the pixel electrode 190, the auxiliary gate pad 92, and the auxiliary data pad 97 are not disconnected because the under cut does not occur under the drain electrode 175, the gate pad 125, and the data pad 179. In addition, since the IZO film and the lower layer 701 of molybdenum or molybdenum alloy having a low contact resistance are sufficiently in contact with each other, the contact resistance of the contact portion can be minimized. In the exemplary embodiment of the present invention, a target for forming the IZO films 190, 92, and 97 was a product called indium x-metaloxide (IDIXO) manufactured by idemitsu, and the targets were In ₂ O ₃ and ZnO. It is preferable that the content of Zn in In + Zn is in the range of 15-20 at%. In addition, in order to minimize contact resistance, the IZO film is preferably laminated in the range of 250 ° C or lower.

The structure of the thin film transistor array substrate according to the embodiment of the present invention includes a conductive film of aluminum or aluminum alloy in which the gate wirings 121, 125, and 123 and the data wirings 171, 177, 175, and 179 have low resistance. At the same time, it is possible to minimize the contact resistance between the contact portion, especially the wiring and the IZO film, so that it can be applied to a liquid crystal display device having a large screen, and the characteristics of the display device can be improved.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor array substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 9 to 11.

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 10 and 11 are along the XX 'line and the XI-XI' line of the thin film transistor substrate shown in FIG. 9, respectively. It is sectional drawing cut out.

First, the gate line 121 and the gate pad including the lower layer 201 of chromium or molybdenum or molybdenum alloy and the upper layer 202 of aluminum or aluminum alloy on the insulating substrate 110 as in the first embodiment. A gate wiring including the 125 and the gate electrode 123 is formed. The gate wiring includes a storage electrode 131 that is parallel to the gate line 121 on the substrate 110 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 131 overlaps with the conductive capacitor conductor 177 connected to the pixel electrode 190 to be described later to form a storage capacitor to improve charge retention of the pixel, and the pixel electrode 190 and the gate line to be described later. If the holding capacity generated by the overlap of 121 is sufficient, it may not be formed.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate lines 121, 125, 123, and 131 to cover the gate lines 121, 125, 123, and 131.

Semiconductor layer patterns 152 and 157 formed of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 140, and n-type impurities such as phosphorus (P) are formed on the semiconductor layer patterns 152 and 157. An ohmic contact layer pattern or an intermediate layer pattern 163, 165, and 167 formed of an amorphous silicon doped with a high concentration is formed.

On the ohmic contact layer patterns 163, 165, and 167, the data including the lower layer 701 of chromium, molybdenum or molybdenum alloy, and the upper layer 702 of aluminum or aluminum alloy having low resistance as in the first embodiment. Wiring is formed. The data line is connected to the data line 171 formed in the vertical direction, the data pad 179 connected to one end of the data line 171 to receive an image signal from the outside, and the thin film connected to the data line 171. A data line portion formed of the source electrode 173 of the transistor, and is separated from the data line portions 171, 179, and 173, and the source electrode 173 with respect to the gate electrode 123 or the channel portion C of the thin film transistor. Also, a conductive capacitor pattern 177 for the storage capacitor is disposed on the drain electrode 175 and the storage electrode 131 of the thin film transistor positioned opposite to each other. When the storage electrode 131 is not formed, the conductor pattern 177 for the storage capacitor is also not formed. Here, as in the first embodiment, the edge portion of the lower layer 701 is exposed out of the upper layer 702.

The contact layer patterns 163, 165, and 167 lower the contact resistance between the semiconductor layer patterns 152 and 157 below and the data wires 171, 177, 173, 175, and 179 above the data. It has the same shape as the wirings 171, 177, 173, 175, and 179. That is, the data line part intermediate layer pattern 163 is the same as the data line parts 171, 179, and 173, the drain electrode intermediate layer pattern 165 is the same as the drain electrode 175, and the storage capacitor intermediate layer pattern 167 is formed. It is the same as the conductor pattern 177 for holding capacitors.

The semiconductor layer patterns 152 and 157 have the same shape as the data lines 171, 177, 173, 175 and 179 and the ohmic contact layer patterns 163, 165 and 167 except for the channel portion C of the thin film transistor. Doing Specifically, the semiconductor capacitor pattern 157 for the storage capacitor, the conductor pattern 177 for the storage capacitor, and the contact layer pattern 167 for the storage capacitor have the same shape, but the semiconductor layer pattern 152 for the thin film transistor has a data wiring. And slightly different from the rest of the contact layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 171, 179, and 173, in particular, the source electrode 173 and the drain electrode 175 are separated, and the data layer intermediate layer 163 and the contact layer pattern for the drain electrode. Although 165 is also separated, the semiconductor layer pattern 152 for thin film transistors is connected to each other without disconnection to generate a channel of the thin film transistor.

A passivation layer 180 made of an organic insulating material or an inorganic silicon nitride is formed on the data wires 171, 177, 173, 175, and 179 as in the first embodiment.

The passivation layer 180 has contact holes 185, 189, and 187 exposing the drain electrode 175, the data pad 179, and the conductive pattern 177 for the storage capacitor, and the gate together with the gate insulating layer 140. It has a contact hole 182 that exposes the pad 125. In this case, as in the first embodiment, all of the contact holes 182, 187, 185, and 189 have a conductive pattern 177 for the storage capacitor, a gate pad 125, a drain electrode 175, and a data pad 179, in particular. The lower layers 201 and 701 having low contact resistance with the IZO are formed to be exposed.

A pixel electrode 190 is formed on the passivation layer 180 to receive an image signal from the thin film transistor and generate an electric field together with the electrode of the upper plate. The pixel electrode 190 is made of a transparent conductive material such as indium tin oxide (ITO) or indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive an image signal. I receive it. The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 190 is also connected to the storage capacitor conductor pattern 177 through the contact hole 187 to transmit an image signal to the conductor pattern 177. On the other hand, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 through the contact holes 182 and 189, respectively, are formed. 179) and supplementing the adhesion between the external circuit device and protecting the pad, are not essential, and their application is optional. Here too, the IZO films 190, 92, and 97 at the contact portion have a lower contact resistance with the conductive pattern 177 for the storage capacitor, the gate pad 125, the drain electrode 175, and the data pad 179, in particular, the IZO. Membranes 201 and 701 are in contact.

Although the transparent IZO is mentioned as an example of the material of the pixel electrode 190, it may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.

Next, a method of manufacturing a thin film transistor array substrate for a liquid crystal display device having the structure of FIGS. 9 to 11 using four masks will be described in detail with reference to FIGS. 9 to 11 and FIGS. 12A to 18C. do.

First, as shown in Figs. 12A to 12C, 2 at% of Nd among the lower layer 201 made of chromium, molybdenum or molybdenum alloy having a lower contact resistance with IZO than aluminum and the aluminum or aluminum alloy having low resistance After sequentially stacking the upper layer 202 by sputtering using a target of Al-Nd alloy including a gate line 121 and a gate on the substrate 110 by a photolithography process using a first mask. The gate wiring including the pad 125, the gate electrode 123, and the storage electrode 131 is formed in a tapered structure. Here, the lower layer 201 is patterned in the same manner as in the first embodiment so that the lower layer 201 comes out of the upper layer 202 so that the later formed IZO layer and the lower layer 201 are sufficiently in contact.

Next, as shown in FIGS. 13A and 13B, the gate insulating layer 140, the semiconductor layer 150, and the intermediate layer 1690 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 상부, 1400 Å to 600 연속 of continuous deposition, followed by lamination of the lower layer 701 of chromium to a thickness of 500 Å or less to enable dry etching, and an upper layer made of aluminum or aluminum alloy having low resistance thereon 702 is laminated to deposit a conductor layer 170 in a thickness of 1,500 kPa to 3,000 kPa, and then a photosensitive film 210 is applied thereon in a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 210 is irradiated with light through a second mask and then developed to form photoresist patterns 212 and 214 as shown in FIGS. 14B and 14C. At this time, the channel portion C of the photoresist patterns 112 and 114, that is, the first portion 214 positioned between the source electrode 173 and the drain electrode 175, is the data wiring portion A, that is, the data. The thickness of the wirings 171, 177, 173, 175, and 179 is smaller than that of the second part 212 positioned at the portion where the wirings 171, 177, 173, 175, and 179 are to be formed. At this time, the ratio of the thickness of the photoresist film 214 remaining in the channel portion C and the thickness of the photoresist film 212 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable that the thickness of the first portion 214 be 1/2 or less of the thickness of the second portion 212, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist 214 may be exposed to light using a photoresist film made of a reflowable material, and then exposed and exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 214 and the underlying layers, that is, the conductor layer 170, the intermediate layer 160, and the semiconductor layer 150. In this case, the data line and the layers under the data line remain in the data wiring portion A, only the semiconductor layer should remain in the channel portion C, and the three layers 170, 160, 150 is removed to expose the gate insulating layer 140.

First, as shown in FIGS. 15A and 15B, the upper layer 701 is etched by wet etching in the same manner as in the first embodiment by exposing the exposed conductor layer 170 of the other portion B to the photoresist pattern 214. Patterned so that undercut occurs at the bottom of 212, and the lower layer 702 is patterned by anisotropic dry etching to form the edge portion of the lower layer 701 to be exposed out of the upper layer 702 and the lower intermediate layer ( 50). In this process, the conductor layer 170 is etched and the photoresist patterns 212 and 214 are preferably etched under a condition that is hardly etched.

In this way, as shown in Figs. 15A and 15B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 178 for the source / drain and the conductor pattern 177 for the storage capacitor, are present. All of the conductor layer 170 of the remaining portion B is removed, revealing the underlying intermediate layer 160. The remaining conductor patterns 178 and 177 are the same as the data wires 171, 177, 173, 175 and 179 except that the source and drain electrodes 173 and 175 are connected without being separated. Here, when dry etching is used, the photoresist patterns 212 and 214 are also etched to a certain thickness.

Then, as shown in FIGS. 16A and 16B, the exposed intermediate layer 160 of the other portion B and the semiconductor layer 150 thereunder are simultaneously removed by the dry etching method together with the first portion 214 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 212 and 214 and the intermediate layer 160 and the semiconductor layer 150 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched and the gate insulating layer 140 is not etched. In particular, it is preferable to etch under conditions in which the etching ratios of the photoresist patterns 212 and 214 and the semiconductor layer 150 are almost the same.

Here, the lower layer 701 of the conductor layer 170, the intermediate layer 160 and the semiconductor layer 150 thereunder can be continuously patterned by dry etching to simplify the manufacturing process, in this case in the same etching chamber It may or may not be performed in-situ which performs a dry etching process.

In addition, when the upper layer 702 is wet-etched and the lower layer 701 is wet-etched, and the wet etching is performed twice in succession, the photoresist patterns 212 and 214 may be lifted to accurately perform the subsequent patterning process. However, as in the exemplary embodiment of the present invention, the upper layer 702 proceeds by wet etching and the lower layer 701 proceeds by dry etching, thereby preventing the photoresist from being lifted up, thereby accurately proceeding the subsequent patterning process.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 178, as shown in FIGS. 16A and 16B, and the intermediate layer 16 of the other portion B. The semiconductor layer 150 is removed to expose the gate insulating layer 140 under the semiconductor layer 150. On the other hand, since the second portion 212 of the data line portion A is also etched, the thickness becomes thin. In this step, the semiconductor layer patterns 152 and 157 are completed. Reference numerals 168 and 167 denote intermediate layer patterns under the source / drain conductor patterns 178 and intermediate layer patterns under the storage capacitor conductor patterns 177, respectively.

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain conductor pattern 178 of the channel part C is removed.

Next, as illustrated in FIGS. 17A and 17B, the source / drain conductor pattern 178 of the channel portion C and the source / drain interlayer pattern 168 under the channel portion C are etched and removed. In this case, unlike the above, both the upper layer 702 and the lower layer 701 of the source / drain conductor pattern 178 are patterned by wet etching, and the source / drain interlayer pattern 168 is patterned by dry etching. At this time, the etching must be performed under the condition that the gate insulating layer 140 is not etched, and the second photosensitive layer 212 is etched so that the data lines 171, 177, 173, 175, and 179 below the photoresist are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 173 and the drain electrode 175 are separated, thereby completing the data lines 171, 177, 173, 175, and 179 and the contact layer patterns 163, 165, and 167 thereunder.

At this time, the removal of the second portion 212 is because the photoresist film may be raised when the wet etching is continuously performed, as described above, the upper layer 702 in the conductor pattern 178 for the channel portion C source / drain. ) Is removed after the wet etching, and before the lower layer 701 is removed. In this case, when the lower layer 701 is dry etched, the lower layer 701 is dried to etch the lower layer to prevent deterioration of the characteristics of the thin film transistor. 701 is removed by wet etching.

After forming the data wirings 171, 177, 173, 175, and 179 in this manner, as shown in FIGS. 18A and 18B, silicon nitride is deposited in the range of 250 to 1500 ° C. by CVD or has excellent planarization characteristics. A protective film 180 is formed by coating an organic insulating material or by stacking a low dielectric constant insulating material including an a-Si: C: O film or an a-Si: O: F film by PECVD. Subsequently, the passivation layer 180 is etched together with the gate insulating layer 140 by using a third mask to form the drain electrode 175, the gate pad 125, the data pad 179, and the conductive pattern 177 for the storage capacitor. Contact holes 185, 187, 189, and 182 exposing the lower layers 201 and 701, respectively, are formed. Also in this case, the contact holes 185, 187, 189, and 182 of the drain electrode 175, the gate pad 125, the data pad 179, and the conductive capacitor 177 for the storage capacitor are the same as in the first embodiment. A portion of the lower layers 201 and 701 is exposed. This is to maximize the contact area having a low contact resistance at the contact as described in the first embodiment and to minimize the contact resistance with the driving integrated circuit.

Finally, as shown in FIGS. 9 to 11, in the same manner as in the first embodiment, a IZO layer having a thickness of 1500 mW to 500 mW is deposited by a sputtering method, and patterned by a photolithography process using a fourth mask to drain. The pixel electrode 190 connected to the electrode 175 and the conductive pattern 177 for the storage capacitor, the auxiliary gate pad 92 connected to the gate pad 125, and the auxiliary data pad 97 connected to the data pad 179 are disposed. The etchant for patterning IZO uses a chromium etchant that is used to etch a metal film of chromium (Cr), which does not corrode aluminum and thus prevents the data or gate wiring from corroding. HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O), and the like.

In the second embodiment of the present invention, the data wirings 171, 177, 173, 175, and 179, the contact layer patterns 163, 165, 167, and the semiconductor layer patterns (below) of the data wirings 171, 177, 173, 175, and 179 are provided. 152 and 157 may be formed using one mask, and the source electrode 173 and the drain electrode 175 may be separated in this process to simplify the manufacturing process.

As described above, according to the present invention, the wiring can be exposed to the IZO film and the conductive film having a low contact resistance, thereby securing a contact portion having a low contact resistance, thereby ensuring the reliability of the contact portion. In addition, by forming a wiring including a conductive film containing low resistance aluminum or an aluminum alloy, the characteristics of a large screen high definition product can be improved. In addition, the manufacturing process can be simplified by patterning the wiring conductive film and the semiconductor layer by dry etching in the manufacturing process of the four masks.

Claims (17)

A wiring formed on an upper substrate, a lower layer formed of a conductive material capable of dry etching, and an upper layer formed on an upper portion of the lower layer, the upper layer formed of aluminum or an aluminum alloy, and having a boundary line positioned on the lower layer; A portion of the boundary line exposing the wiring line includes an insulating film having a contact hole located outside the boundary line of the wiring line, A conductive layer formed of IZO on the insulating film and in contact with the lower film of the wiring through the contact hole. Contact portion of the wiring comprising a. In claim 1, The lower layer is a contact portion of the wiring made of chromium. A gate line formed on an insulating substrate, a gate line including a gate electrode connected to the gate line, A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed on the semiconductor layer or the gate insulating layer, the data line including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode separated from and facing the source electrode; A protective film covering the data line and the semiconductor layer, A conductive layer formed of IZO on the passivation layer and connected to the gate line or the data line through a contact hole of the passivation layer. In the thin film transistor array substrate comprising: The gate wiring or the data wiring includes a lower layer formed of a conductive material capable of dry etching, and an upper layer formed on an upper portion of the lower layer and made of aluminum or an aluminum alloy, and having a boundary line positioned on the lower layer. And the layer is in contact with the lower layer exposed out of the upper layer through at least the contact hole. In claim 3, The lower layer is a thin film transistor array substrate made of chromium. In claim 4, The thin film transistor array substrate of which the thickness of the lower layer has a thickness of 500 Å or less. In claim 4, The gate line may include a gate pad configured to receive a scan signal from an external device and deliver the scan signal to the gate line. The data line may include a data pad configured to transfer an image signal from the outside to the data line. The contact hole includes first to third contact holes exposing the drain electrode, the gate pad or the data pad, The conductive layer may include a pixel electrode, an auxiliary gate pad, or an auxiliary data pad connected to the drain electrode, the gate pad, or the data pad through the first to third contact holes, respectively. In claim 3, The semiconductor layer except for the channel portion between the source and drain electrodes, the data line is formed in the same shape thin film transistor array substrate. Forming a gate line including a gate line formed on the insulating substrate, a gate electrode connected to the gate line, and a gate pad connected to the gate line; Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer pattern on the gate insulating layer; Forming a data line including a data line crossing the gate line in a vertical direction, a source electrode connected to the data line, a drain electrode facing and separated from the source electrode, and a data pad connected to the data line; step, Forming a passivation layer covering the semiconductor layer pattern and having a contact hole exposing the gate wiring or the data wiring; Stacking and patterning IZO on the passivation layer to form a conductive layer connected to the gate wiring or the data wiring through the contact hole; In the manufacturing method of a thin film transistor array substrate comprising: The gate line or the data line may be formed by sequentially stacking and patterning a lower layer made of a conductive material capable of dry etching and an upper layer made of aluminum or an aluminum alloy. In claim 8, The gate line and the data line forming step may be performed by a photolithography process using a photoresist pattern, wherein the upper layer is etched by wet etching, and the lower layer is etched by dry etching. In claim 9, And the lower layer is formed of chromium. In claim 10, And a thickness of the lower layer is 500 Å or less. In claim 8, And forming a contact layer pattern between the semiconductor layer pattern and the data line. In claim 12, The data line and the semiconductor layer pattern are formed through a photolithography process using a single photoresist pattern, wherein the photoresist pattern is positioned on a channel portion between the source electrode and the drain electrode and has a first thickness and a first thickness. And a second portion having a thickness thicker than the first thickness and a third portion having a thickness thinner than the first portion. In claim 13, The photosensitive film pattern is a manufacturing method of a thin film transistor substrate for a liquid crystal display device using a mask. The method of claim 14, The forming of the gate insulating film, the semiconductor layer pattern, the contact layer pattern, and the data line may include Stacking the gate insulating layer, the semiconductor layer, the contact layer, and the lower layer and the upper layer in order; Applying a photoresist film on top of the upper film, Exposing the photosensitive film through the mask; Developing the photoresist to form the photoresist pattern such that the second portion is located above the data line; A portion of the upper layer and the lower layer below the third portion and a contact layer and semiconductor layer below the first portion and the upper layer and the lower layer and the contact layer below the first portion and the second portion Etching the thickness to form the data line, the contact layer pattern, and the semiconductor layer pattern each of the lower layer, the upper layer, the contact layer, and the semiconductor layer; Removing the photoresist pattern Method of manufacturing a thin film transistor substrate comprising a. The method of claim 15, The forming of the data line, the contact layer pattern, and the semiconductor layer pattern may include: Wet etching the upper layer below the third portion; Dry etching the lower layer to expose the contact layer; The contact layer under the third portion and the semiconductor layer thereunder are dry-etched together with the first portion to expose the gate insulating film under the third portion and the upper layer under the first portion, and constitute the semiconductor layer. Completing the semiconductor layer pattern; Wet etching the upper layer and the lower layer below the first portion to complete the data line; Etching the contact layer under the first portion to complete the contact layer pattern Method of manufacturing a thin film transistor substrate comprising a. The method of claim 16, And removing the second portion between the etching of the top layer and the etching of the bottom layer.