KR20040008921A - A thin film transistor array panel and a method for manufacturing the same - Google Patents

Abstract

PURPOSE: A thin film transistor array panel is provided to simplify a fabricating process while preventing a contact part from corroding by eliminating aluminum from the contact part while using a photoresist layer pattern for a semiconductor layer pattern. CONSTITUTION: A gate line and a gate interconnection connected to the gate line are formed on an insulated substrate. The gate interconnection is covered with a gate insulation layer. The semiconductor layer pattern is formed on the gate insulation layer. A data interconnection is formed on the semiconductor layer pattern, including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode confronting the source electrode with respect to the gate electrode. The data interconnection includes a lower layer and an upper layer. The lower layer is made of a barrier metal. The upper layer is exposed by the lower layer in at least a part of the drain electrode, made of aluminum or aluminum alloy, wherein the interface of the upper layer is located on the lower layer.

Description

A thin film transistor array substrate and a method of manufacturing the same {A THIN FILM TRANSISTOR ARRAY PANEL AND A METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate and a method for manufacturing the same, and more particularly, to a thin film transistor substrate for use as a substrate of a liquid crystal display device and a method for manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In such a liquid crystal display, in order to prevent signal delay, a data line for transmitting an image signal generally uses a low resistance material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of forming a pixel electrode using indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, aluminum or aluminum in a contact portion where a drain electrode of aluminum or an aluminum alloy and a pixel electrode of ITO or IZO are in contact with each other. The wiring of the aluminum alloy is corroded or the contact resistance of the contact portion is problematic. In addition, in the case where the data wiring connected to the semiconductor layer made of silicon is formed of aluminum or an aluminum alloy, aluminum may be diffused into the semiconductor layer to damage the wiring. Therefore, it is preferable that the data wiring be interposed with ITO or IZO or another metal having excellent contact characteristics with the semiconductor layer, and the aluminum or aluminum alloy is removed from the contact portion.

However, when aluminum front etching is performed to remove aluminum or aluminum alloy, an undercut structure is formed at the contact portion, so that another formed film is disconnected at the contact portion or weakly induces the profile of the other film to increase the contact resistance of the contact portion. Increase. In order to prevent this, there is a method of adding a photolithography process to remove the undercut structure from the contact portion, but the manufacturing process is complicated and the manufacturing cost increases.

An object of the present invention is to provide a thin film transistor array substrate including a contact portion having excellent contact characteristics.

Another object of the present invention is to simplify the manufacturing process of a thin film transistor array substrate including a contact portion having excellent contact characteristics.

1 is a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II-II. FIG.

3A, 4A, 5A, and 7A are layout views of a thin film transistor array substrate in which an intermediate process of manufacturing a thin film transistor array substrate for a liquid crystal display device according to a first embodiment of the present invention is performed according to a process sequence thereof;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6 is a cross-sectional view taken along the line Vb-Vb 'of FIG. 5A and illustrating the next step of FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A and illustrating the next step of FIG. 6;

8 is a thin film transistor array substrate for a liquid crystal display according to a second embodiment of the present invention;

FIG. 9 is a cross-sectional view of the thin film transistor array substrate of FIG. 8 taken along the line IX-IX.

10A, 11A, 12A, and 14A are layout views of a thin film transistor array substrate illustrating an intermediate process of manufacturing a thin film transistor array substrate for a liquid crystal display device according to a second embodiment of the present invention, according to a process sequence thereof.

FIG. 10B is a cross-sectional view taken along the line Xb-Xb ′ in FIG. 10A.

FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 11A, and is a cross-sectional view showing the next step of FIG. 10B;

12B is a cross-sectional view taken along the line XIIb-XIIb ′ in FIG. 12A, and is a cross-sectional view illustrating the next step in FIG. 11B.

FIG. 13 is a cross-sectional view taken along the line XIIb-XIIb ′ in FIG. 12A and illustrates the next step of FIG. 12B;

FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb ′ of FIG. 14A, and is a cross-sectional view illustrating the next step of FIG. 13.

In order to solve this problem, in the present invention, the data wiring is formed by including a conductive film of a conductive material which has good contact characteristics with other materials or prevents aluminum or aluminum alloy from diffusing into another layer, and the data wiring is low. In the case of including a conductive film of aluminum or aluminum alloy having resistance, the conductive film of aluminum or aluminum alloy is removed from the contact portion during the photolithography process of patterning another film in the manufacturing process.

At this time, the lower layer is preferably formed of a barrier metal such as chromium or molybdenum or molybdenum alloy or titanium or tantalum.

More specifically, in the thin film transistor array substrate according to the present invention, a gate line connected to the gate line and the gate line is formed on the insulating substrate. A semiconductor layer pattern is formed on an upper portion of the gate insulating layer covering the gate line, and the upper portion includes a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode centered on the gate electrode. In the lower layer and the drain electrode of the barrier metal, the exposed boundary line is positioned on the upper portion of the lower layer, and a data line is formed including the upper layer of aluminum or aluminum alloy. In addition, a passivation layer is formed on the semiconductor layer pattern, and a pixel electrode connected to the drain electrode is formed in contact with the upper layer on the exposed lower layer of the drain electrode.

An impurity is doped between the semiconductor layer pattern and the data line, and an ohmic contact layer having the same pattern as that of the data line is further formed.

In this case, it is preferable that the semiconductor layer has a larger area than the data wiring, and the pixel electrode is made of ITO or IZO.

The gate line includes a gate pad that receives a scan signal from an external source and transfers the scan signal to a gate line, and the data wire includes a data pad that transmits an image signal from an external source to a data line, and the protective layer is a lower layer of the exposed drain electrode. Auxiliary gate pads and auxiliary data pads having a first contact hole for connecting the subpixel electrode and second and third contact holes for exposing the gate pad and the data pad, and connected to the gate pad and the data pad on the same layer as the pixel electrode, respectively. May be formed.

At this time, it is preferable that the protective film is in contact with the lower film around the first and third contact holes.

In the method for manufacturing a thin film transistor array substrate according to the present invention, first, a gate wiring including a gate line and a gate electrode is formed on an insulating substrate, and a gate insulating film is formed thereon. Subsequently, a semiconductor layer pattern is formed on the gate insulating layer, and a data line including a data line, a source electrode, and a drain electrode is formed on the semiconductor layer pattern, and a data line is formed on the lower layer and the upper layer on the lower layer. Next, the upper layer is removed from the drain electrode, and a pixel electrode connected to the lower layer of the exposed drain electrode is formed. In this case, in order to remove the upper layer, a photoresist pattern for patterning the semiconductor layer pattern is used as an etching mask.

In this case, the lower layer is preferably formed of a barrier metal, and the upper layer is preferably formed of aluminum or an aluminum alloy, and an ohmic contact layer doped with impurities is preferably formed between the semiconductor layer pattern and the data line.

The semiconductor layer pattern, the data wiring forming step, and the upper layer removing step may include sequentially stacking a semiconductor layer, a lower layer, and an upper layer on the gate insulating layer, patterning the upper layer and the lower layer, and applying a photoresist pattern on the upper layer and the semiconductor layer. And forming an upper layer that is not covered by the photoresist pattern, and removing the semiconductor layer by the photoresist pattern and the data wiring.

In this case, the photoresist pattern may expose at least a part of the drain electrode and cover the channel portion between the source electrode and the drain electrode.

After removing the photoresist pattern, it is preferable to remove the ohmic contact layer that is not covered by the data wiring.

Next, a thin film transistor array substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a thin film transistor array substrate for wiring according to an embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

Next, a thin film transistor array substrate and a manufacturing method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a structure of a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate shown in FIG. 1 taken along the line II-II '.

A gate wiring holding wiring including a conductive film made of silver or a silver alloy having a low resistance or a metal material of aluminum or an aluminum alloy is formed on the insulating substrate 110. The gate wire is connected to the gate line 121 and the gate line 121 extending in the horizontal direction and connected to the gate pad 125 and the gate line 121 which receive a gate signal from the outside and transfer the gate signal to the gate line. A gate electrode 123 of the thin film transistor. The storage wiring is connected to the storage electrode line 131 and the storage electrode 133 connected to the storage electrode line 131 which is parallel to the gate line 121 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. Include. The storage electrode 133 overlaps the conductor pattern 177 for the storage capacitor connected to the pixel electrode 190, which will be described later, to form a storage capacitor that improves the charge storage capability of the pixel. The sustain electrode may be used by providing a protrusion on the gate line 121. At this time, the gate wirings 121, 123, 125 and the sustain wirings 131, 133 have a tapered structure.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate wirings 121, 125, and 123 and the storage wiring.

Semiconductor layer patterns 152 and 157 made of a semiconductor such as amorphous silicon are formed on the gate insulating layer 140 of the gate electrode 125, and silicide or n-type impurities are formed on the semiconductor layer patterns 152 and 157. Resistive contact layers 163, 165 and 167 made of a material such as highly doped n + hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 163, 165, and 167, a bottom layer made of a barrier metal such as molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), titanium (Ti), or the like A data line is formed that includes 701 and an upper film 702 made of low resistance aluminum (Al) or aluminum alloy (Al alloy). The data line is formed in the vertical direction and crosses the gate line 121 to define a pixel, which is a branch of the data line 171 and the data line 171 and extends to the upper portion of the ohmic contact layer 163. ), Which is connected to one end of the data line 171 and is separated from the data pad 179 and the source electrode 173 for receiving an image signal from the outside, and is opposite to the source electrode 173 with respect to the gate electrode 123. The drain electrode 175 is formed on the ohmic contact layer 165. The data line also includes a conductor pattern 177 for a storage capacitor that overlaps the storage electrode 131. In this case, the conductive capacitor pattern 177 for the storage capacitor may extend from the drain electrode 175 and be connected to the drain electrode 175.

At this time, the upper layer 702 of aluminum or aluminum alloy among the data wires 171, 173, 175, 177, and 179 may have a contact portion, that is, a conductive pattern 177 for a storage capacitor, a drain electrode 175, and a data pad ( 179 is partially removed, and the contact portion from which the top layer 702 is removed has excellent contact properties with other materials, and prevents aluminum or aluminum alloy from diffusing into the silicon layers 150, 157, 163, 165, and 167. The lower layer 701 made of a barrier metal is exposed, and the boundary line of the upper layer 702 is positioned above the lower layer 701, so that the data lines 171, 173, 175, 177, and 179 have different shapes. A lower layer 701 and an upper layer 702 having a pattern are included.

The contact layer patterns 163, 165, and 167 lower the contact resistance between the semiconductor layer patterns 152 and 157 below and the data lines 171, 177, 173, 175, and 179 above the data. It has the same shape as the wirings 171, 177, 173, 175, and 179. That is, the data line part intermediate layer pattern 163 is the same as the data line parts 171, 179, and 173, the drain electrode intermediate layer pattern 165 is the same as the drain electrode 175, and the storage capacitor intermediate layer pattern 167 is formed. It is the same as the conductor pattern 177 for holding capacitors.

The semiconductor layer patterns 152 and 157 may include the data wires 171, 177, 173, 175, and 179 except for the thin film transistor unit in which the gate electrode 123, the drain electrode 175, and the source electrode 173 are located. It has the same shape as the ohmic contact layer patterns 163, 165, and 167. Specifically, the semiconductor capacitor pattern 157 for the storage capacitor, the conductor pattern 177 for the storage capacitor, and the contact layer pattern 167 for the storage capacitor have the same shape, but the semiconductor layer pattern 152 for the thin film transistor has a data wiring. And slightly different from the rest of the contact layer pattern. That is, in the thin film transistor unit, the data line units 171, 179, and 173, in particular, the source electrode 173 and the drain electrode 175 are separated, and the data layer intermediate layer 163 and the contact layer pattern 165 for the drain electrode are also separated. However, the semiconductor layer pattern 152 for thin film transistors is connected here without being disconnected.

The data lines 171, 173, 177, 175, and 179 and the semiconductor layers 152 and 157 that are not covered by the semiconductor substrates 171, 173, 177, 175, and 179 are formed by an organic material having excellent planarization characteristics and a photosensitive or plasma enhanced chemical vapor deposition (PECVD) method. A protective film 180 made of silicon nitride which is a low dielectric constant insulating material or an inorganic material including a -Si: C: O film or an a-Si: O: F film or the like is formed.

In the passivation layer 180, contact holes 185, 187, and 189 are formed to expose the drain electrode 175, the conductive capacitor pattern 177 for the storage capacitor, and the lower layer 701 of the data pad 179, respectively. The contact hole 182 exposing the gate pad 125 is formed together with the gate insulating layer 140. In this case, the protective layer 180 is in contact with the lower layer 701 around the contact holes 185, 187, and 189 without the undercut structure and covers the lower layer 701.

A pixel electrode 190 is formed on the passivation layer 180 to receive an image signal from the thin film transistor and generate an electric field together with the electrode of the upper plate. The pixel electrode 190 is made of a transparent conductive material such as IZO or ITO, and is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive an image signal. The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 190 is also connected to the storage capacitor conductor pattern 177 through the contact hole 187 to transmit an image signal to the storage capacitor conductor pattern 177. On the other hand, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 through the contact holes 182 and 189, respectively, are formed. 179) and supplementing the adhesion between the external circuit device and protecting the pad, are not essential, and their application is optional.

In the thin film transistor array substrate according to the exemplary embodiment of the present invention, the ITO film or the IZO films 190, 92, and 97 may have a conductive pattern 177, a drain electrode 175, and a data pad 179 for a storage capacitor at a contact portion. Since only the lower layer 701 is in contact with the lower layer 701, the contact resistance of the contact portion may be low, thereby improving characteristics of the display device.

Herein, although the transparent IZO or ITO is mentioned as an example of the material of the pixel electrode 190, the transparent electrode may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.

Next, a method of manufacturing the TFT array substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, a single film of aluminum or an aluminum alloy, which is a low resistance conductive material, or a multilayer film including the same, is stacked on the glass substrate 110, and patterned by a photolithography process using a mask. As a result, the gate wiring including the gate line 121, the gate electrode 123, and the gate pad 125, and the storage wiring including the storage electrode line 131 and the storage electrode 133 are formed in a tapered structure.

Next, as shown in FIGS. 4A and 4B, three layers of the gate insulating layer 140 made of silicon nitride, the semiconductor layer 150 made of amorphous silicon, and the doped amorphous silicon layer 160 are sequentially stacked. Here, the gate insulating film 140 is preferably formed by laminating silicon nitride to a thickness of about 2,000 to 5,000 Pa, in a temperature range of 250 to 400 ° C. Next, a molybdenum or molybdenum alloy or chromium among the Bayer metals having excellent contact properties with other materials such as ITO or IZO, while preventing other materials from diffusing into the semiconductor layer 150 or the doped amorphous silicon layer 160 thereon. The lower layer 701 having a thickness of about 500 GPa, and the upper layer 702 by using a target of Al-Nd alloy including Nd of 2 at% of aluminum or aluminum alloy having low resistance. Laminate through sputtering in order to a thickness of about 2,500Å. Subsequently, the upper layer 702 and the lower layer 701 are patterned by a photolithography process using a data wiring mask to be connected to the data line 171 and the data line 171 crossing the gate line 121 to form a gate electrode ( The source electrode 173 and the data line 171 extending to the upper portion of the upper part 123 are separated from the data pad 179 and the source electrode 179 connected to one end thereof, and the source electrode 1 is formed around the gate electrode 123. A data line including a drain electrode 175 facing the 173 and a conductor pattern 177 for a storage capacitor positioned on the storage electrode 133 is formed. Here, both the upper layer 702 and the lower layer 701 may be etched by wet etching, the upper layer 702 may be etched by wet etching, and the lower layer 701 may be etched by dry etching, and the lower layer 701 may be etched. ) Is a molybdenum or molybdenum alloy film, the lower film 701 and the upper film 702 may be patterned under one etching condition.

Subsequently, as shown in FIGS. 5A and 5B, the photosensitive film pattern 210 for a semiconductor pattern is formed by exposure and development by a photolithography process using a mask for a semiconductor pattern. In this case, the photoresist pattern 210 is formed so as not to cover at least the data pad 179, the drain electrode 175, and the conductive capacitor conductor 177 that are part of the data line, and the photoresist pattern 210 is formed. The upper layer 702 including aluminum is etched using the etching mask to expose the data pad 179, the drain electrode 175, and the lower layer 701 of the conductive pattern 177 for the storage capacitor at the contact portion. Subsequently, the doped amorphous silicon layer 160 and the semiconductor layer 150 exposed by using the data wires 171, 173, 177, 175, and 179 and the photoresist pattern 210 as an etching mask are etched to form a semiconductor layer pattern 152. 157) and leaves the doped amorphous silicon layer 160 thereon. Here, the semiconductor layer pattern 152 remains only at the lower portion of the data lines 171, 173, 175, 177, and 179 and not covered by the photoresist pattern 210, and thus, at least the data lines 171, 173, 175, 177, and 179. It will have a larger area than). In this case, since the upper layer 702 including aluminum is removed from the contact portion by using the photoresist pattern 210 as an etching mask, the photoresist pattern 210 may include at least a portion of the data pad 179 and the drain electrode. 175 and a part of the conductive pattern 177 for the storage capacitor are not covered and at least the channel portion must be covered in the channel portion between the source electrode 173 and the drain electrode 175 to prevent the semiconductor layer from being etched.

The data lines 171, 173, 175, 177, and 179 may be formed as a double layer, but may be formed as a single layer, and the photoresist pattern 210 may be formed to completely cover the data line 171.

Subsequently, the photoresist layer pattern 210 is removed, and the doped amorphous silicon layer pattern 160 is not etched by the data lines 171, 173, 175, 177, and 179 as shown in FIG. 6 to etch the gate electrode 123. The semiconductor layer pattern 152 between the two doped amorphous silicon layers 163 and 165 is exposed while being separated from both sides. Subsequently, in order to stabilize the surface of the exposed semiconductor layer pattern 152, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 7A and 7B, an organic material having excellent planarization characteristics and photosensitivity may be coated on top of the substrate 110 or a-Si may be formed by a plasma enhanced chemical vapor deposition (PECVD) method. A low dielectric constant CVD film, such as a C: O film or an a-Si: O: F film, is deposited to form a passivation layer 180, and patterned by dry etching together with the gate insulating layer 140 by a photolithography process using a mask. Contact holes 182, 185, 187 and 189 are formed to expose the pad 125 and the drain electrode 175, the conductive pattern 177 for the organic capacitor, and the lower layer 701 of the data pad 179, respectively.

Next, as shown in FIGS. 1 and 2, the IZO or ITO film is laminated by sputtering and patterned using a mask to conduct the drain electrode 175 and the conductor pattern for the storage capacitor through the contact holes 185 and 187. An auxiliary gate connected to the gate pad 125 and the lower layer 701 of the data pad 179 through the pixel electrode 190 connected to the lower layer 701 of 177 and the contact holes 182 and 189, respectively. Pads 92 and auxiliary data pads 97 are formed, respectively. At this time, the pixel electrode 190 is not disconnected because no undercut occurs in the contact holes 185 and 187 exposing the drain electrode 175 as the contact portion and the lower layer 701 of the conductive pattern 177 for the storage capacitor. The IZO film or the ITO films 190 and 97 are sufficiently in contact with the lower film 701 having low contact resistance with them, so that the contact resistance of the contact portion can be minimized. In the exemplary embodiment of the present invention, a target for forming the IZO films 190, 92, and 97 was a product called indium x-metal oxide (IDIXO) manufactured by idemitsu, and the target was In ₂ O ₃ and ZnO, and the content of Zn in In + Zn is preferably in the range of 15-20 at%. In addition, in order to minimize contact resistance, the IZO film is preferably laminated in the range of 250 ° C or lower.

The structure of the thin film transistor array substrate according to the exemplary embodiment of the present invention may include a conductive film of aluminum or aluminum alloy in which the gate lines 121, 125, 123 and the data lines 171, 173, 175, 177, and 179 have low resistance. At the same time, the contact resistance between the contact portion, in particular, the data line and the pixel electrode 190 of the IZO or ITO can be minimized, and thus it can be applied to a liquid crystal display device having a large screen. In addition, in order to remove the undercut from the contact portion during the manufacturing process, by removing the conductive film of aluminum or aluminum alloy remaining on the contact portion with the photosensitive film pattern for the semiconductor pattern without a separate photo etching process, to prevent the corrosion occurring in the contact portion while simplifying the manufacturing process The reliability of the contact portion can be secured.

Next, a structure of a thin film transistor array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9.

8 is a thin film transistor array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 8 taken along the line IX-IX '.

As shown in Figs. 8 and 9, most of the structure is the same as that of the first embodiment. At this time, the conductive film constituting the gate wirings 121, 123, and 125 preferably has a taper angle of 20-70 °, and at least one of the conductive films in the case where the gate wirings 121, 123, and 125 is formed of a multilayer film It is desirable to have a tapered structure to favorably form a profile of another film formed in the film.

However, unlike the first embodiment, the sustain wiring is not formed to independently form the storage capacitor, and the conductive capacitor conductor 177 connected to the pixel electrode 190 through the contact hole 187 is formed. The storage capacitor overlaps with the gate line 121 applying the gate signal to the adjacent pixel row.

In addition, the semiconductor layer pattern 152 formed on the gate insulating layer 140 may have a data pad 179 having a contact portion, a drain electrode 175, or a lower portion of the conductive pattern 177 for a storage capacitor. , 177, 175, and the other part is exposed outside the data lines 171, 175, and 173.

In addition, the upper layer 701 of the low-resistance aluminum or aluminum alloy is formed as a whole of the data lines 171, 173, 175, and 179 to have the same shape as the lower layer 701, and has a contact portion with a data pad 179. Only part of the drain electrode 175 or the conductive pattern 177 for the storage capacitor is removed.

In addition, an edge portion of the pixel electrode 190 formed on the passivation layer 180 formed of an organic insulating material, an inorganic insulating material, or a low dielectric constant CVD film overlaps with the semiconductor layer 152 extending out of the data line 171 to obtain an aperture ratio. It is raising. Of course, it may overlap with the gate lines 121 and 171 as in the first embodiment, and may not overlap, but it is preferable to overlap at least the semiconductor layer pattern 152 in order to secure the aperture ratio as in the second embodiment. .

Also in the thin film transistor array substrate according to the second embodiment of the present invention, the ITO film or the IZO films 190, 92, and 97 may be formed at the contact portion of the conductive capacitor conductor 177, the drain electrode 175, and the data pad ( Since only the lower layer 701 is in contact with the lower layer 701 of the upper portion 179, the contact resistance of the contact portion can be ensured low, thereby improving the characteristics of the display device.

Next, a method of manufacturing the TFT array substrate for a liquid crystal display according to the second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9 and FIGS. 10A to 14B.

First, as shown in FIGS. 10A and 10B, as in the first embodiment, the gate wirings 121, 123, and 125 include a conductive film of aluminum or an aluminum alloy, which is a conductive material of low resistance, on the glass substrate 110. To form. At this time, it is preferable that the gate wirings 121, 123, and 125 have a taper angle of 20-70 degrees.

Next, as shown in FIGS. 11A and 11B, as in the first embodiment, the gate insulating layer 140 of silicon nitride, the semiconductor layer 150 made of amorphous silicon, and the three layer films of the doped amorphous silicon layer 160 are successively formed. By laminating. Subsequently, the lower layer 701 made of molybdenum, molybdenum alloy, chromium, or the like of the metal of the bayer, which is excellent in contact with other materials such as ITO or IZO, while preventing the material from being diffused, has 2d% of Nd in the aluminum alloy. After stacking the upper layer 702 of Al-Nd alloy including, and then patterning the upper layer 702 and the lower layer 701 by a photolithography process using a data wiring mask to form the data line (171, 173, 179, 175, 177).

Next, as shown in FIGS. 12A and 12B, the photosensitive film pattern 210 for a semiconductor pattern is formed by exposure and development by a photolithography process using a mask for a semiconductor pattern. 179, and developed so as to completely cover most of the data wirings 171, 173, 175, and 179 except for a part of the drain electrode 175 or the conductor pattern 177 for the storage capacitor. Subsequently, the upper layer 702 of the data line 171, 173, 175, 177, and 179 that is not covered by the photoresist pattern is removed, and the contact portion of the data pad 179, the drain electrode 175, or the storage capacitor ( A portion of the 177 is exposed and the doped amorphous silicon layer 150 and the doped amorphous silicon are exposed by using the photoresist pattern 210 and the data lines 171, 173, 175, 177, and 179 as an etching mask. The layer 160 is etched to complete the semiconductor layer patterns 152 and 157.

13, the photoresist layer pattern 210 is removed, and the doped amorphous silicon layer pattern 160 is not etched by the data lines 171, 173, 175, 177, and 179 to etch the gate electrode 123. The semiconductor layer pattern 152 between the two doped amorphous silicon layers 163 and 165 is exposed while being separated from both sides.

Next, as shown in FIGS. 14A and 14B, the passivation layer 180 is stacked and patterned using an organic insulating material, an inorganic insulating material, or a low dielectric constant CVD film to form the gate pad 125, the drain electrode 175, and the organic storage. Contact holes 182, 185, 187, and 189 exposing the conductive conductor pattern 177 and the lower layer 701 of the data pad 179, respectively, are formed.

Next, as shown in FIGS. 8 and 9, the transparent conductive material patterns 190, 92, and 97 are formed by stacking and patterning the transparent conductive material as in the first embodiment. In this case, it is preferable that at least the pixel electrode 190 overlaps the semiconductor layer pattern 152 whose edge portion is exposed to the outside of the data line 171.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, by removing the aluminum from the contact portion by using the photoresist pattern for the semiconductor layer pattern, the manufacturing process can be simplified and the corrosion generated at the contact portion can be prevented, thereby ensuring the reliability of the contact portion. Can be minimized. In addition, by forming a wiring including a conductive film containing low resistance aluminum or an aluminum alloy, the characteristics of a large screen high definition product can be improved.

Claims (28)

A gate line formed on the insulating substrate and connected to the gate line and the gate line, A gate insulating film covering the gate wiring, A semiconductor layer pattern formed on the gate insulating layer; A data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode centered on the gate electrode, the barrier layer being formed on the semiconductor layer pattern; A data line including a lower layer and an upper layer exposed by the lower layer in at least a portion of the drain electrode and having a boundary line positioned on the lower layer, the upper layer being made of aluminum or an aluminum alloy; A protective film covering the semiconductor layer pattern, A pixel electrode connected to the drain electrode in contact with the lower layer on the exposed lower layer of the drain electrode; Thin film transistor array substrate comprising a. In claim 1, The lower layer includes a chromium or molybdenum or molybdenum alloy. In claim 1, And a resistive contact layer doped with impurities between the semiconductor layer pattern and the data line. In claim 3, And the ohmic contact layer is formed in the same pattern as the data line. In claim 1, The semiconductor layer has a larger area than the data line. In claim 1, The pixel electrode is a thin film transistor array substrate made of ITO or IZO. In claim 1, The gate line may include a gate pad configured to receive a scan signal from the outside and transmit the scan signal to the gate line, and the data line may include a data pad configured to transfer the image signal from the outside to the data line. The passivation layer has a first contact hole connecting the lower layer of the exposed drain electrode and the pixel electrode, and second and third contact holes exposing the gate pad and the data pad. And an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad, respectively, on the same layer as the pixel electrode. In claim 7, The passivation layer is in contact with the lower layer around the first and third contact holes. Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer pattern on the gate insulating layer; Forming a data line including a data line, a source electrode, and a drain electrode on the semiconductor layer pattern, the data line including a lower layer and an upper layer on the lower layer; Removing the upper layer from the drain electrode, A method of manufacturing a thin film transistor array substrate, the method comprising: forming a pixel electrode connected to the lower layer of the exposed drain electrode; In the removing of the upper layer, a method of manufacturing a thin film transistor array substrate using a photoresist pattern as an etching mask for patterning the semiconductor layer pattern. In claim 9, And the lower layer is formed of a barrier metal and the upper layer is formed of aluminum or an aluminum alloy. In claim 9, And forming an ohmic contact layer doped with impurities between the semiconductor layer pattern and the data line. In claim 11, The semiconductor layer pattern, the data line forming step and the upper layer removing step may include Sequentially stacking a semiconductor layer, the lower layer, and the upper layer on the gate insulating layer; Patterning the upper layer and the lower layer to form the data line; Forming the photoresist pattern on the upper layer and the semiconductor layer; Removing the upper layer not covered by the photoresist pattern; Removing the semiconductor layer not having the photoresist pattern and the data line. In claim 12, And the photoresist pattern exposes at least a portion of the drain electrode and covers a channel portion between the source electrode and the drain electrode. In claim 13, After removing the semiconductor layer, Removing the photoresist pattern; Removing the ohmic contact layer that is not covered by the data line. Method of manufacturing a thin film transistor array substrate further comprising. A gate line formed on the insulating substrate and connected to the gate line and the gate line, A gate insulating film covering the gate wiring, A semiconductor layer pattern formed on the gate insulating layer; A data line intersecting the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode around the gate electrode, and one end portion of the data line formed on the semiconductor layer pattern; A data wiring comprising a connected data pad, A protective film covering the semiconductor layer pattern, A thin film transistor array substrate comprising: a pixel electrode connected to the drain electrode in contact with the bottom layer on the exposed bottom layer of the drain electrode; A portion of the semiconductor layer pattern except at least a portion of the drain electrode or the data pad is exposed outside the data line. The method of claim 15, And the data line is formed of a single layer or a lower layer and a multi-layered layer including an upper layer formed on the lower layer and having a different shape from that of the lower layer. The method of claim 16, The lower layer may be formed of a barrier metal, and the upper layer may be formed of aluminum or an aluminum alloy. The method of claim 15, And the semiconductor layer pattern is exposed outside the data line. The method of claim 18, An edge portion of the pixel electrode overlaps the gate line or the data line or overlaps the semiconductor layer pattern exposed out of the data line. The method of claim 15, And a resistive contact layer doped with an impurity between the semiconductor layer pattern and the data line, wherein the resistive contact layer has the same pattern as the data line. The method of claim 15, The gate wiring has a tapered structure. The method of claim 15, The gate line may include a gate pad configured to receive a scan signal from the outside and transmit the scan signal to the gate line. The passivation layer has a first contact hole connecting the lower layer of the exposed drain electrode and the pixel electrode, and second and third contact holes exposing the gate pad and the data pad. And an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad, respectively, on the same layer as the pixel electrode. The method of claim 22, The passivation layer is in contact with the lower layer around the first and third contact holes. Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer pattern on the gate insulating layer; Forming a data line including a data line, a source electrode, a drain electrode, and a data pad on the semiconductor layer pattern; A method of manufacturing a thin film transistor array substrate comprising forming a pixel electrode connected to the drain electrode. The forming of the semiconductor layer pattern may include using at least a portion of the data line as an etching mask. The method of claim 24, And the data line is formed of a lower layer and an upper layer. The method of claim 25, And removing the upper layer that is not covered by the photoresist pattern for forming the semiconductor layer pattern. The method of claim 24, The semiconductor layer pattern and the data line forming step, Sequentially stacking a semiconductor layer, the lower layer, and the upper layer on the gate insulating layer; Patterning the upper layer and the lower layer to form the data line; Forming the photoresist pattern on the upper layer and the semiconductor layer; Removing the upper layer not covered by the photoresist pattern; Removing the semiconductor layer not having the photoresist pattern and the data line. The method of claim 27, And the photoresist pattern exposes at least a portion of the drain electrode or the data pad and covers a channel portion between the source electrode and the drain electrode.