KR20080045961A - Thin film transistor substrate and metod of fabricating the same - Google Patents

Abstract

A TFT(Thin Film Transistor) substrate and a method for fabricating the same are provided to prevent corrosion of gate ends, prevent a pixel defect, and reduce processing time. A TFT substrate(100) includes gate wiring formed on an insulating substrate(10), including gate lines, gate electrodes(26), and gate ends(24). A gate insulating pattern(32), an active layer pattern(44), and ohmic contact layer patterns(55,56) are sequentially arranged at a part of the gate wiring except the gate ends. Data wiring includes a capping pattern(61) directly contacting with the gate ends for covering the gate ends, data lines(62) crossing the gate lines, and source and drain electrodes(65,66) formed on the ohmic contact layer patterns, separated from each other. Auxiliary gate ends(84) are electrically connected with the gate ends.

Description

Thin film transistor substrate and manufacturing method therefor {Thin film transistor substrate and metod of fabricating the same}

1A is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 1B is a cross-sectional view of the thin film transistor substrate of FIG. 1A taken along line AA ′.

2 to 6 are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: insulating substrate 22: gate line

24: gate end 26: gate electrode

28 sustain electrode 30 gate insulating film

32: gate insulating film pattern 40: active layer

44 active layer pattern 50 doped amorphous silicon layer

55, 56: ohmic contact layer 61: capping pattern

62: data line 65: source electrode

66: drain electrode 67: drain electrode extension

68: end of data 70: shield

74: first contact hole 77: second contact hole

78: third contact hole 82: pixel electrode

84: end of auxiliary gate 88: end of auxiliary data

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate and a method of manufacturing the same, in which pixel defects and wiring defects are reduced and process time is shortened.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed between them. The display device is applied to rearrange the liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted.

Among the liquid crystal display devices, a field generating electrode is provided on two substrates. Among them, a plurality of pixel electrodes are arranged in a matrix form on one substrate (thin film transistor substrate), and one common electrode covers the entire surface of the substrate on another substrate (common electrode substrate). In such a liquid crystal display, an image is displayed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor substrate has a gate line and a pixel that connect a thin film transistor, which is a three-terminal element for switching a voltage applied to the pixel electrode, to each pixel electrode, and transmit a signal for controlling the thin film transistor. A plurality of wirings and insulating films are formed, such as a data line for transferring a voltage to be applied to an electrode, and an electrical signal is directly applied to an end and connected to the ends to directly apply an electrical signal to the plurality of wirings. The receiving secondary end is formed.

In general, the end and the auxiliary end are made of different materials having a large standard reduction potential difference, so that corrosion may occur at the connection site.

In order to prevent this, a structure of capping the end with another material has been studied, but this also increases the processing time and causes a problem of pixel defects caused by the photoresist used during the process.

Therefore, it is necessary to prevent corrosion and pixel defects between the end and the auxiliary end connecting portions and to shorten the process time.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate having reduced pixel defects and wiring defects and a short process time.

Another technical problem to be achieved by the present invention is to provide a method of manufacturing such a thin film transistor substrate.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A thin film transistor substrate according to an embodiment of the present invention for achieving the technical problem, a gate wiring formed on an insulating substrate, including a gate line, a gate electrode and a gate end, and the gate wiring except for the gate end A gate insulating layer pattern, an active layer pattern, and an ohmic contact layer pattern disposed in order over at least a portion of the substrate; a capping pattern in direct contact with the gate end to cover the gate end; a data line crossing the gate line; and the ohmic contact layer. And a data line including a source electrode and a drain electrode spaced apart from each other on the pattern, and an auxiliary gate end electrically connected to the gate end.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, the method including: forming a gate line including a gate line, a gate electrode, and a gate end on an insulating substrate; Forming a gate insulating layer pattern, an active layer pattern, and an unseparated ohmic contact layer pattern so as to be disposed in order on at least a portion of the gate wiring except an end; a capping pattern that directly contacts the gate end to cover the gate end; Forming a data line including a data line intersecting a gate line and a source electrode and a drain electrode spaced apart from each other on the unseparated ohmic contact layer pattern, and forming an auxiliary gate end electrically connected to the gate end; It includes.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

The spatially relative terms " below ", " beneath ", " lower ", " above ", " upper " It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below or beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be oriented in other directions as well, in which case spatially relative terms may be interpreted according to orientation.

Hereinafter, a thin film transistor substrate according to an exemplary embodiment will be described with reference to the accompanying drawings.

First, a structure of a thin film transistor substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1A and 1B. 1A is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention. FIG. 1B is a cross-sectional view of the thin film transistor substrate of FIG. 1A taken along line AA ′.

The thin film transistor substrate 100 is formed of a plurality of wires formed on the insulating substrate 10.

A plurality of gate wires 22, 24, 26, and 28 for transmitting a gate signal are formed on the insulating substrate 10. Gate wires 22, 24, 26, and 28 are connected to gate lines 22 and gate lines 22 that extend in the horizontal direction, and receive gate signals from the outside and transfer them to gate lines 22. A sustain electrode connected to the end 24 and the gate line 22 and having a width of the gate electrode 26 and the gate line 22 of the thin film transistor formed in the shape of a protrusion extending in parallel to the gate line 22 ( 28).

The gate end 24 is not covered by the gate insulating film pattern 32 described later, but directly by the capping pattern 61. The material constituting the capping pattern 61 and the gate end 24 has a small standard reduction potential difference so that the risk of corrosion is small. This will be described in detail later. The storage electrode 28 overlaps with the pixel electrode 82, which will be described later, to form a storage capacitor that improves the charge storage capability of the pixel. The shape and arrangement of the sustain electrode 28 may be modified in various forms.

The gate wirings 22, 24, 26, and 28 are made of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, and copper-based metals such as copper (Cu) and copper alloys. And molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), tantalum (Ta), and neodymium (Nd). In addition, the gate lines 22, 24, 26, and 28 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive films may be formed of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce the signal delay or voltage drop of the gate wirings 22, 24, 26, and 28. Is done. In contrast, the other conductive film is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum, neodymium, and the like. Good examples of such a combination include a chromium lower layer and an aluminum upper layer, an aluminum lower layer and a molybdenum upper layer, and an aluminum lower layer and a neodymium upper layer. However, the present invention is not limited thereto, and the gate wires 22, 24, 26, and 28 may be made of various metals and conductors.

A gate insulating layer pattern 32 made of silicon nitride (SiNx) or the like is formed on the insulating substrate 10 or the portion of the gate line 22 overlapping with the data line 62 described later, and on the gate electrode 26. It is. The gate insulation layer pattern 32 is not formed in the gate end 24 and the pixel region, and the gate end 24 is entirely covered by the capping pattern 61 described later.

An active layer pattern 44 made of a semiconductor such as hydrogenated amorphous silicon or polycrystalline silicon is formed in an island shape with the same pattern as the gate insulating layer pattern 32 on the gate insulating layer pattern 32. Resistive contact layer patterns 55 and 56 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the upper side, respectively.

Data lines 61, 62, 65, 66, 67, and 68 are formed on the ohmic contact layer patterns 55 and 56. The data wires 61, 62, 65, 66, 67, and 68 are formed to overlap the gate ends 24 to be in direct contact with the gate ends 24 to cover the gate ends 24, and vertically. The source line 65 and the data line formed in the direction to cross the gate line 22 to define the pixel, and the branch of the data line 62 and extending to the upper portion of the ohmic contact layer 55. The data end 68, which is extended from one end of the 62, receives the image signal from the outside, is spaced apart from the source electrode 65, and the source electrode 65 of the gate electrode 26 or the channel portion of the thin film transistor. A drain electrode 66 formed on the opposite ohmic contact layer 56 and a drain electrode extension 67 having a large area extending from the drain electrode 66 and contacting the pixel electrode 82 are included.

The data lines 61, 62, 65, 66, 67, and 68 are preferably made of refractory metals such as chromium, molybdenum-based metals, tantalum, and titanium, and are disposed on a lower layer (not shown) such as refractory metals and It may have a multilayer structure consisting of an upper layer (not shown) of a low resistance material. Examples of the multilayer film structure may include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the double film of the chromium lower film and the aluminum upper film or the aluminum lower film and the molybdenum upper film.

The capping pattern 61 may be made of, for example, molybdenum like the other data wires 62, 65, 66, 67, and 68. Since it is not large, corrosion by the galvanic effect can be prevented. This will be described in detail later.

The source electrode 65 overlaps at least a portion of the active layer pattern 44, and the drain electrode 66 faces the source electrode 65 around the gate electrode 26 and at least a portion of the active layer pattern 44. This overlaps. In this case, the ohmic contact layer patterns 55 and 56 are interposed between the active layer pattern 44 at the lower side and the source electrode 65 and the drain electrode 66 thereon, and serve to lower the contact resistance.

The passivation layer 70 is formed on the data wires 61, 62, 65, 66, 67, and 68, the active layer pattern 44 not covered by the active layer pattern 44, and the exposed insulating substrate 10. The protective film 70 is formed of, for example, a-Si: C: O or a-Si: It may be formed of a low dielectric constant insulating material such as O: F, or silicon nitride (SiNx), which is an inorganic material. In addition, when the protective film 70 is formed of an organic material, the organic material of the protective film 70 is prevented from contacting a portion where the active layer pattern 44 between the source electrode 65 and the drain electrode 66 is exposed. For this purpose, an insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) may be further formed below the organic film.

In the passivation layer 70, the first contact hole 74 exposing the capping pattern 61, the drain electrode 66, and specifically, the second contact hole 77 exposing the drain electrode extension 67 and the data end 68. ), A third contact hole 78 exposing each of The drain electrode 66 or the drain electrode extension portion is formed on the passivation layer 70 through the auxiliary gate end 84 electrically connected to the capping pattern 61 through the first contact hole 74 and the second contact hole 77. A pixel electrode 82 positioned in the pixel electrically connected to the 67 and an auxiliary data end 88 electrically connected to the data end 68 through the third contact hole 78 are formed. The pixel electrode 82 to which the data voltage is applied generates an electric field together with the common electrode of the upper substrate (not shown) to determine the arrangement of the liquid crystal molecules of the liquid crystal layer between the pixel electrode 82 and the common electrode. Here, the pixel electrode 82, the auxiliary gates, and the data ends 84 and 88 are made of ITO.

The pixel electrode 82 may be formed directly on the insulating substrate 10 except for a portion connected to the drain electrode 66 or the drain electrode extension 67 and a portion overlapping with the storage electrode 28. Since the pixel electrode 82 is formed directly on the insulating substrate 10 without interposing the gate insulating layer 30, the transmittance of light emitted from the backlight assembly (not shown) may be improved.

The auxiliary gate end 84 is electrically connected to the capping pattern 61 to transmit a gate signal to the gate end 24. While the auxiliary gate end 84 is electrically connected to the direct capping pattern 61, the auxiliary gate end 84 is not directly in contact with the gate end 24, so that corrosion due to a galvanic effect may be prevented. . Specifically, the standard reduction potential difference between an aluminum / neodymium alloy and ITO when the auxiliary gate end 84, typically made of ITO, is directly and electrically connected, for example, to the gate end 24 made of an alloy of aluminum and neodymium. Corrosion may occur due to the galvanic effect at the connection site, but in this embodiment, the auxiliary gate end 84 made of ITO contacts the capping pattern 61 made of molybdenum, for example, to prevent corrosion. This is because the standard reduction potential difference between ITO and molybdenum is not large.

Hereinafter, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6 and FIGS. 1A and 1B.

First, referring to FIGS. 2 and 1A, gate wirings 22, 24, including a gate line 22, a gate end 24, a gate electrode 26, and a storage electrode 28 on an insulating substrate 10 may be used. 26, 28).

3 and 1A, the gate insulating film 30, the active layer 40, and the doped amorphous silicon layer 50 made of silicon nitride are respectively 1,500 on the resultant, for example, using chemical vapor deposition. Continuous deposition is carried out in a thickness of from 5 kPa to 5,000 kPa, from 500 kPa to 2,000 kPa, from 300 kPa to 600 kPa.

4 and 1A, a photoresist material is coated on the resultant, and the photoresist material is patterned through an etching mask to form a photoresist pattern 110.

In this case, the photoresist pattern 110 is formed to cover the top of the gate electrode 26 and the top of the doped amorphous silicon layer 50 on which the source electrode 65 and the drain electrode 66 to be described later are formed. The photoresist pattern 110 is formed to have a uniform thickness without any difference in thickness at these sites. Accordingly, since the process of etching back the photoresist pattern 110 is not included in the subsequent process, pixel defects due to particles of the photoresist material or contamination of the chamber may be prevented. In addition, since the halftone mask or the slit mask may not be used to separately form a thin photoresist pattern (not shown), it may be economical. In addition, since the etch back process is not used, not only the reactive ion etching (RIE) facility but also the PE (Plasma Etch) facility may be used, thereby diversifying the process.

4, 5, and 1A, the doped amorphous silicon layer 50, the active layer 40, and the gate insulating layer 30 are simultaneously etched using the photoresist pattern 110 as an etching mask. The gate insulating film pattern 32, the active layer pattern 44, and the unseparated ohmic contact layer pattern 51 are formed. In this case, the etching gas may be, for example, a mixed gas of SF ₆ and HCl, or a mixed gas of SF ₆ and O ₂ . As a result, the gate end 24 is exposed to the outside, and the insulating substrate 10 is exposed in the pixel region or the like. As such, the process of exposing the gate end 24 by forming the gate insulating film pattern 32, the active layer pattern 44, and the unseparated ohmic contact layer pattern 51 by one etching, the photoresist pattern By using the 110 as an etching mask, the above-mentioned patterns are simply formed without performing a multi-step process such as forming an active layer pattern 44 and the like by etching back and removing a thin photoresist pattern, Since the gate end 24 can be exposed, the process time can be shortened. In addition, since the exposure time of the gate end 24 is minimized, the gate end 24 may be prevented from being damaged in the etching process for forming the active layer pattern 44.

5, 6 and 1A, a conductive material for data wiring is deposited on the resultant, for example, by the method of sputtering. Subsequently, by etching the conductive material for data wiring using an etching mask, the capping pattern 61 and the data line 62 crossing the gate line 22 are directly contacted with the gate end 24 to cover the gate end 24. And data lines 61, 62, 65, 66, 67, and 68 including a source electrode 65 and a drain electrode 66 spaced apart from each other on the unseparated ohmic contact layer pattern 51. All other portions of the conductive material for data wiring are removed, and the lower insulating substrate 10 is exposed. Subsequently, the unseparated ohmic contact layer pattern 51 exposed between the spaced source electrode 65 and the drain electrode 66 is etched to form the ohmic contact layer patterns 55 and 56. For forming the ohmic contact layer patterns 55 and 56, the same etching mask as that used to form the source electrode 65 and the drain electrode 66 is used.

Subsequently, referring to FIGS. 6, 1A, and 1B, an organic material having excellent planarization characteristics and photosensitivity on the resultant, a-Si: C formed by plasma enhanced chemical vapor deposition (PECVD) A low dielectric constant insulating material such as: O, a-Si: O: F, or silicon nitride (SiNx), which is an inorganic material, or the like is formed in a single layer or in a plurality of layers to form a passivation layer 70.

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process to expose the gate end 24, the drain electrode extension 67, and the data end 68, respectively. , A second contact hole 77, and a third contact hole 78 are formed. Subsequently, the ITO film is deposited and photo-etched to extend the drain electrode 66 or the drain electrode through the auxiliary gate end 84 and the second contact hole, which are electrically connected to the capping pattern 61 through the first contact hole 74. A pixel electrode 82 electrically connected to the portion 67 and an auxiliary data end 88 electrically connected to the data end 68 are formed through the third contact hole 78. In particular, the auxiliary gate end 84 made of ITO and the capping pattern 61 made of, for example, molybdenum are directly and electrically connected, and are not directly connected to the gate end 24 made of aluminum and neodymium alloy. The gate signal may be transmitted to the gate end 24 through the auxiliary gate end 84 and the capping pattern 61 while preventing corrosion due to the standard reduction potential difference of.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments but may be manufactured in various forms, and having ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the thin film transistor substrate and the manufacturing method thereof according to the present invention, corrosion is prevented at the gate end, the pixel defect is prevented, and the process time can be shortened.

Claims (11)

A gate wiring formed on the insulating substrate and including a gate line, a gate electrode, and a gate end; A gate insulating pattern, an active layer pattern, and an ohmic contact layer pattern sequentially disposed on at least a portion of the gate line except for the gate end; A data line including a capping pattern directly contacting the gate end to cover the gate end, a data line crossing the gate line, and a source electrode and a drain electrode formed on the ohmic contact layer pattern and spaced apart from each other; And And a second gate end electrically connected to the gate end. According to claim 1, A protective film formed on the data line and the insulating substrate; And a first contact hole exposing the capping pattern in the passivation layer. The method of claim 2, And the auxiliary gate end is electrically connected to the capping pattern through the first contact hole. The method of claim 2, A second contact hole formed in the passivation layer to expose the drain electrode; And And a pixel electrode electrically connected to the drain electrode through the second contact hole, at least a portion of which is formed directly on the insulating substrate. According to claim 1, The gate insulating layer pattern and the active layer pattern may be formed on the gate electrode and on a portion where the gate line and the data line overlap. Forming a gate wiring on the insulating substrate, the gate wiring including a gate line, a gate electrode, and a gate end; Forming a gate insulating layer pattern, an active layer pattern, and an unseparated ohmic contact layer pattern so as to be disposed on at least a portion of the gate line except for the gate end; Forming a data line including a capping pattern directly contacting the gate end to cover the gate end, a data line crossing the gate line, and a source electrode and a drain electrode spaced apart from each other on the unseparated ohmic contact layer pattern; And Forming an auxiliary gate end electrically connected to the gate end. The method of claim 6, Forming the gate insulating layer pattern, the active layer pattern, and the unseparated ohmic contact layer pattern may include: Forming a gate insulating film, an active layer, a doped amorphous silicon layer, and a photoresist pattern sequentially disposed on the gate wiring and the insulating substrate; And Etching the doped amorphous silicon layer, the active layer, and the gate insulating layer using the photoresist pattern as an etching mask to form the gate insulating layer pattern, the active layer pattern, and the unseparated ohmic contact layer pattern A method of manufacturing a thin film transistor substrate comprising the step. The method of claim 6, The photoresist pattern is a method of manufacturing a thin film transistor substrate having a uniform thickness. The method of claim 6, The step of forming the data line, Depositing a conductive material for data wiring on the gate insulating layer pattern, the active layer pattern, and the unseparated ohmic contact layer pattern; Etching the conductive material for data wiring to form the data wiring including the capping pattern, the source electrode and the drain electrode spaced apart from each other; And Forming an ohmic contact layer pattern by etching the unseparated ohmic contact layer pattern exposed in the spaced space by using the same etching mask as the etching mask used to form the source electrode and the drain electrode. Method of preparation. The method of claim 6, Forming a passivation layer on the data line and the insulating substrate; And Forming a first contact hole exposing the capping pattern and a second contact hole exposing the drain electrode in the passivation layer. The method of claim 10, The forming of the auxiliary gate end electrically connected to the gate end may include forming an auxiliary gate end electrically connected to the drain electrode through the auxiliary gate end and the second contact hole electrically connected to the capping pattern through the first contact hole. A method of manufacturing a thin film transistor substrate comprising the step of forming a pixel electrode to be connected.

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