KR20030094606A - A contact portion of a wires, and thin film transistor substrate including the contact portion - Google Patents

Abstract

PURPOSE: Contact parts of lines and a thin film transistor substrate including the same are provided to secure the reliability of contact parts by minimizing contact resistance of wiring and an IZO film. CONSTITUTION: A gate wiring(11) is formed on an insulating substrate. A gate insulating film(12) is formed on the gate wiring. A semiconductor layer is formed on the gate insulating film. A data wiring is formed on the gate insulating film. The semiconductor layer is covered with a passivation film. A transparent conductive pattern(14) formed of an IZO(Indium Zinc Oxide) film is connected with the gate wiring exposed through contact holes(13) of the gate insulating film. Contact parts of the gate wiring exposed through the contact holes have side walls in step shape. The transparent conductive pattern contacts with the contact parts following the side walls.

Description

A contact portion of a wiring and a thin film transistor substrate including the same {A CONTACT PORTION OF A WIRES, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT PORTION}

The present invention relates to a contact portion of a wiring and a thin film transistor array substrate including the same.

In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.

In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since the wiring of aluminum or aluminum alloy has a weak physical or chemical property, corrosion occurs when the contact portion is connected to another conductive material, thereby deteriorating the characteristics of the semiconductor device. In particular, when the pixel electrode is formed using indium tin oxide (ITO), which is a transparent conductive material, as in a liquid crystal display device, the wiring of aluminum or an aluminum alloy is corroded at the contact portion that contacts the wiring of the ITO and aluminum or an aluminum alloy. This happens. In order to solve this problem, a technique of forming a pixel electrode using IZO, which does not cause corrosion even when contacted with aluminum-based wiring instead of ITO, has been developed.However, in the case of using IZO, there is a problem of increasing contact resistance at the contact portion. have.

An object of the present invention is to provide a contact portion of a wiring made of a low resistance material and having a low resistance contact characteristic.

Another object of the present invention is to provide a thin film transistor array substrate including a contact structure of a wiring having excellent contact characteristics.

1A and 2B are diagrams illustrating a contact portion of a wiring and a method of manufacturing the same according to an embodiment of the present invention;

3 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 4 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 3 taken along the line IV-IV.

5A, 6A, 7A, and 8A are layout views of a thin film transistor substrate, illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof;

5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A, and is a cross-sectional view showing the next step in FIG. 7B;

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

10 and 11 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 9 taken along lines X-X 'and XI-XI',

12 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 12 taken along the line XIII-XIII ′.

In order to solve this problem, in the present invention, the wiring includes a lower film made of a conductive material of aluminum or an aluminum alloy having low resistance, and a conductive material having good contact properties with other materials. The lower layer is formed outside the upper layer so that the conductive layer in contact with the wiring is in contact with the upper surface of the lower layer.

At this time, the lower film preferably includes a conductive film of chromium, molybdenum or molybdenum alloy.

The contact portion of the wiring can be similarly applied to the thin film transistor array substrate for a liquid crystal display device.

In the thin film transistor array substrate according to the present invention, a gate wiring is formed on an insulating substrate, and a gate insulating film covering the gate wiring is formed. A semiconductor layer is formed on the gate insulating film facing the gate wiring, a data wiring is formed on the gate insulating film or the semiconductor layer, and the semiconductor layer is covered with a protective film. In addition, the transparent conductive film pattern is connected to the gate wiring or the data wiring exposed through the contact hole of the gate insulating film or the protective film. At this time, the contact portion exposed through the contact hole in the gate wiring or the data wiring has a stepped sidewall, and the transparent conductive film pattern is in contact with the contact along the stepped sidewall.

Here, the gate wiring or the data wiring may be formed of a lower layer of chromium or molybdenum or molybdenum alloy and an upper layer of aluminum or aluminum alloy, and the lower layer is exposed out of the upper layer so that the transparent conductive layer pattern is in contact with the upper surface of the lower layer. .

At this time, the transparent conductive film pattern is preferably made of IZO.

The gate wiring includes a gate line extending in a horizontal direction, a gate electrode connected to the gate line, and a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line. The data wiring includes a data line and a data line extending in a vertical direction. And a source pad connected to the source electrode, the drain electrode facing the source electrode centered on the gate electrode, and a data pad transferring the image signal from the outside to a data line.

The transparent conductive layer pattern includes a pixel electrode contacting the drain electrode through the first contact hole, and an auxiliary data pad or auxiliary data pad connected to the data pad and the gate pad through the second and third contact holes, respectively.

Then, a person having ordinary knowledge in the technical field to which the present invention belongs with respect to the contact portion of the wiring according to the embodiment of the present invention, the manufacturing method thereof, the thin film transistor array substrate including the same, and the manufacturing method thereof with reference to the accompanying drawings. It demonstrates in detail so that implementation may be carried out easily.

1A to 2B are diagrams showing contact portions of a wire according to an exemplary embodiment of the present invention. FIG. 1A is a layout view showing a contact portion structure of a wire, and FIG. 1B is cut along the line Ib-Ib 'of FIG. 1A. 2A and 2B are cross-sectional views illustrating a method for manufacturing a contact portion in accordance with the process sequence thereof.

In order to minimize the delay of the signal, it is suitable to include a conductive film of aluminum or an aluminum alloy having a low resistivity of 15 μΩcm or less in order to minimize signal delay. In this case, the wiring should be connected to another conductive layer in order to receive a signal from the outside or to transmit a signal to the outside, and the contact resistance at the contact portion should be small when contacting the other conductive material in the manufacturing process. In particular, when IZO is used as a transparent conductive layer as in a liquid crystal display device, since IZO has a very high contact resistance with aluminum or an aluminum alloy, the contact resistance can be minimized at the contact portion where the wire including IZO and aluminum is connected. It is necessary to design the structure of the contact so that it is. To this end, as shown in FIGS. 1A and 1B according to an embodiment of the present invention, the wiring 11 is formed on the substrate 10 and has a low contact resistance with IZO such as molybdenum or molybdenum alloy or chromium. The lower layer 111 and the upper layer 112 made of a conductive material having low resistance, such as aluminum or an aluminum alloy, are included. At this time, as shown in FIG. 1B, the lower layer 111 is formed on the upper layer (the upper layer) at the contact portion of the wiring 11 exposed through the contact hole 13 of the insulating film 12 formed so that the boundary line of the wiring 11 is exposed. The side wall of the wiring 11 extends out of the boundary line of 112 and has a step shape. The conductive film 14 of IZO formed on the insulating film 12 has a sidewall of the wiring 11 at the contact hole 13. And the upper surface of the lower layer 111 at the same time. Here, the conductive layer 14, which is connected to the wiring 11 through the contact hole 13, of the wiring 11 exposed from the contact hole 13 may be prevented from being disconnected due to the step in the contact hole 13. It is preferable to design the contact hole 13 so that the distance between the boundary line and the boundary line of the adjacent contact hole 13 does not deviate from the range of 2 占 퐉.

In the method of manufacturing the contact portion of the wiring according to the embodiment of the present invention, first, as shown in FIG. 2A, the lower layer 111 and the upper layer 112 are sequentially stacked on the substrate 10, and the upper layer 112 is formed. The photoresist patterns 212 and 214 formed of two parts having different thicknesses are formed on the upper side of the top surface), and the upper layer 112 and the lower layer 111 are sequentially etched using the photoresist patterns 212 and 214 as masks.

In this case, there may be various ways of varying the thickness of the photoresist film according to the position in the photolithography process using a single mask, mainly slit to adjust the light transmission amount of the portion corresponding to the second portion 214. Form a lattice pattern or use a translucent film.

Here, the line width of the pattern located between the slits or the spacing between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, a different transmittance for controlling the transmittance when fabricating a mask is used. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photoresist film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, the first portion 212 where the polymer molecules are not decomposed remains almost intact, and the second portion having a thickness thinner than the first portion 212 that is not irradiated with light at all is irradiated with less light. 214). In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin second portion 214 is exposed to light using a photosensitive film made of a reflowable material, and exposed using a conventional mask that is divided into a portion that can completely transmit light and a portion that can not completely transmit light. And a portion of the photoresist film flows down to a portion where the photoresist film does not remain.

Subsequently, the ashing process is performed to remove the second portion 214 of the photoresist pattern, as shown in FIG. 2B, and then only the top layer 112 is patterned using the photoresist pattern of the first portion 212 as shown in FIG. 1B. As described above, the upper surface of the lower layer 111 is exposed out of the upper layer 112, so that the side surface of the wiring 11 may have a stepped shape.

Such a contact portion of a wiring and a method of manufacturing the same can be applied to a thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the same.

Next, a thin film transistor array substrate and a manufacturing method for a liquid crystal display device including a contact portion of a wiring according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor substrate shown in FIG. 3 taken along the line IV-IV '.

A gate wiring made of a metal material of aluminum or aluminum alloy having low resistance is formed on the insulating substrate 110. The gate wire is connected to the gate line 121 and the gate line 121 extending in the horizontal direction and connected to the gate pad 125 and the gate line 121 which receive a gate signal from the outside and transfer the gate signal to the gate line. A gate electrode 123 of the thin film transistor.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate lines 121, 125, and 123.

A semiconductor layer 150 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 140 of the gate electrode 125, and n + is heavily doped with silicide or n-type impurities on the semiconductor layer 150. Resistive contact layers 163 and 165 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the ohmic contacts 163 and 165 and the gate insulating layer 140, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), Data lines 171, 173, 175, and 179 made of a metal or a conductor such as titanium (Ti) are formed. The data line is formed in the vertical direction and crosses the gate line 121 to define a pixel, which is a branch of the data line 171 and the data line 171 and extends to the upper portion of the ohmic contact layer 163. ), Which is connected to one end of the data line 171 and is separated from the data pad 179 and the source electrode 173 for receiving an image signal from the outside, and is opposite to the source electrode 173 with respect to the gate electrode 123. The drain electrode 175 is formed on the ohmic contact layer 165.

The data wires 171, 173, 175, and 179 are preferably formed of a single film of aluminum or aluminum alloy, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having a low contact resistance with other materials, especially IZO. Examples include Al (or Al alloys) / Cr or Al (or Al alloys) / Mo (or Mo alloys), and the like. In an embodiment of the present invention, the data wires 171, 173, 175, and 179 are made of chromium. It consists of a double film of the lower film 701 of and the upper film 702 of aluminum-neodymium alloy.

At this time, in the drain electrode 175, which is a contact portion connected to the pixel electrode 190, the lower layer 701 is exposed out of the upper layer 702, so that the sidewall has a step shape.

A passivation film 801 made of silicon nitride is formed on the data wires 171, 173, 175, and 179 and the semiconductor layer 150 that is not covered.

In the passivation layer 801, contact holes 185 and 189 respectively exposing the drain electrode 175 and the data pad 179 are formed, and the contact holes 182 exposing the gate pad 125 together with the gate insulating layer 140. Is formed. Here, the contact hole 185 is formed so that the boundary line of the lower layer 701 of the drain electrode 175 is exposed, so that the sidewalls and lower layers of the lower layer 701 and the upper layer 702 of the drain electrode 179 are exposed. The top surface of 701 is all exposed through contact hole 185.

A pixel electrode 190 is formed on the passivation layer 801 and is electrically connected to the drain electrode 175 through the contact hole 185. In this case, the pixel electrode 190 is sufficiently in contact with the sidewall of the drain electrode 175 exposed from the contact hole 185, in particular, the sidewall and the top surface of the lower layer 701 of the drain electrode 175. It can be minimized.

In addition, the auxiliary gate pad 92 and the auxiliary data pad 97, which are connected to the gate pad 125 and the data pad 179, respectively, are formed on the passivation layer 801 through the contact holes 182 and 189. The pixel electrode 190, the auxiliary gates, and the auxiliary data pads 92 and 97 are made of indium zinc oxide (IZO).

3 and 4, the pixel electrode 190 overlaps the gate line 121 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 190 is disposed on the same layer as the gate lines 121, 125, and 123. The storage capacitor wiring may be added, or the width of the gate line 121 overlapping the pixel electrode 190 may be formed wide.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4 and FIGS. 5A to 8B.

First, as shown in FIGS. 5A and 5B, about 2,500 mW using a target including Al-Nd containing 2 at% of Nd among aluminum or aluminum alloy metals having low resistance on the substrate 110. Stacking and patterning by sputtering at a temperature of about 150 ° C. to form a horizontal gate line including a gate line 121, a gate electrode 123, and a gate pad 125 and having a tapered structure.

Next, as shown in FIGS. 6A and 6B, a three-layer film of a gate insulating film 140 made of silicon nitride, a semiconductor layer 150 made of amorphous silicon, and a doped amorphous silicon layer 16 is successively stacked and a mask is formed. The semiconductor layer 150 and the ohmic contact layer 160 are formed on the gate insulating layer 140 facing the gate electrode 125 by patterning the semiconductor layer 150 and the doped amorphous silicon layer 160 by the patterning process. do. Here, the gate insulating film 140 is preferably formed by laminating silicon nitride to a thickness of about 2,000 to 5,000 Pa, in a temperature range of 250 to 400 ° C.

Next, as shown in FIGS. 7A to 7B, the lower film 701 made of molybdenum, molybdenum alloy, chromium, or the like is about 500 kPa, and has a thickness of about 2 at% of the aluminum or aluminum alloy metal having low resistance. The upper layer 702 was sequentially laminated by sputtering to a thickness of about 2,500 에서 at a temperature of about 150 ° C. using an Al-Nd alloy target including Nd, and then patterned by a photo process using a mask to form a gate line. The data line 171 crossing the 121 and the source electrode 173 connected to the data line 171 and extending to the upper portion of the gate electrode 123, and the data line 171 are connected to one end of the data pad ( 179 and a drain electrode 175 which are separated from the source electrode 179 and face the source electrode 173 with respect to the gate electrode 123, and have a tapered structure. Here, both the upper layer 702 and the lower layer 701 may be etched by wet etching, the upper layer 702 may be etched by wet etching, and the lower layer 701 may be etched by dry etching, and the lower layer 701 may be etched. ) Is a molybdenum or molybdenum alloy film may be patterned with the upper film 702 in one etching condition.

In addition, the lower layer 701 of the drain electrode 175 in one photolithography process using a photosensitive layer pattern having a different thickness as shown in FIG. 2A in order to sufficiently contact the later formed IZO layer and the lower layer 701. It is formed so as to be exposed out of the upper film 702.

Subsequently, the doped amorphous silicon layer pattern 106 which is not covered by the data wires 171, 173, 175, and 179 is etched and separated from both sides around the gate electrode 123, while the doped amorphous silicon layers ( The semiconductor layer pattern 150 between 163 and 165 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 150, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 8A and 8B, an inorganic insulating film such as silicon nitride is stacked in a range of 250 ° C. to 400 ° C. to form a protective film 801, and together with the gate insulating film 140 in a photolithography process using a mask. Patterning by dry etching forms contact holes 182, 185, and 189 exposing the gate pad 125, the drain electrode 175, and the data pad 179, respectively. In this case, the contact hole 185 is formed such that the boundary line of the drain electrode 175 and the sidewalls of the upper layer 701 and the lower layer 701 are exposed. In this case, the distance between the boundary line of the contact hole 185 located outside the drain electrode 175 and the boundary line of the drain electrode 175 adjacent thereto is preferably formed to be within 2 μm. This is to minimize contact resistance between the pixel electrode 190 and the drain electrode 175 formed later, and to prevent the undercut from occurring under the drain electrode 175 when forming the contact hole 185. to be.

Next, as shown in FIGS. 3 and 4, the IZO film is stacked by sputtering and patterned using a mask to contact the pixel electrode 190 and the contact hole connected to the drain electrode 175 through the contact hole 185. An auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179, respectively, are formed through 182 and 189. In this case, the pixel electrode 190 is not disconnected because an undercut does not occur under the drain electrode 175, and the pixel electrode 190 is in close contact with the lower layer 701 having a low contact resistance with the IZO layer, thereby minimizing contact resistance of the contact portion. have. In the exemplary embodiment of the present invention, a target for forming the IZO films 190, 92, and 97 was a product called indium x-metal oxide (IDIXO) manufactured by idemitsu, and the target was In ₂ O ₃ and ZnO, and the content of Zn in In + Zn is preferably in the range of 15-20 at%. In addition, in order to minimize contact resistance, the IZO film is preferably laminated in the range of 250 ° C or lower.

The structure of the thin film transistor array substrate according to the embodiment of the present invention includes a conductive film of aluminum or aluminum alloy in which the gate wirings 121, 125, and 123 and the data wirings 171, 173, 175, and 179 have low resistance. At the same time, the contact resistance between the contact portion, particularly the data line and the pixel electrode 190 of the IZO film can be minimized, and thus it can be applied to a large screen high-definition liquid crystal display device.

As described above, the contact portion of the wiring can be applied to a substrate completed by a manufacturing method using five masks, but can be similarly applied to a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

9 to 11, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail.

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 10 and 11 are along the XX 'line and the XI-XI' line of the thin film transistor substrate shown in FIG. 9, respectively. It is sectional drawing cut out.

First, an upper layer made of a low resistance conductive material such as aluminum or an aluminum alloy and a lower layer 201 made of a conductive material having excellent contact properties with other materials such as molybdenum, molybdenum alloy, chromium, etc., on the insulating substrate 110. A gate wiring including a film 202 and including a gate line 121, a gate pad 125, and a gate electrode 123 is formed as in the first embodiment. The gate wiring includes a storage electrode 131 that is parallel to the gate line 121 on the substrate 110 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 131 overlaps the conductive capacitor conductor 179 connected to the pixel electrode 82, which will be described later, to form a storage capacitor that improves the charge storage capability of the pixel. The pixel electrode 131 and the gate line, which will be described later, If the holding capacity generated by the overlap of 121 is sufficient, it may not be formed. At this time, the lower layer 201 of the gate pad 125 is exposed out of the upper layer 202, and the sidewalls of the gate pad 125 have a step shape.

Semiconductor patterns 152 and 158 formed of a semiconductor such as hydrogenated amorphous silicon on the gate insulating layer 140 formed of silicon nitride (SiN _x ) and covering the gate wirings 121, 125, 123, and 131. Is formed on the semiconductor patterns 152 and 157, and an ohmic contact layer pattern or an intermediate layer pattern 163, 165, or the like formed of amorphous silicon doped with high concentration of n-type impurities such as 167 is formed.

On the ohmic contact layer patterns 163, 165, and 58, a data line including a conductive film made of a conductive material of aluminum or an aluminum alloy having low resistance is formed. The data line is a thin film transistor which is a branch of the data line 171 formed in the vertical direction, the data pad 179 connected to one end of the data line 171 to receive an image signal from the outside, and the data line 171. And a data line portion of the source electrode 173 of the source electrode 173, and separated from the data line portions 171, 179, and 173 of the source electrode 173. Also included is a conductive capacitor pattern 177 for the storage capacitor located on the drain electrode 175 and the storage electrode 131 of the thin film transistor positioned on the opposite side. When the storage electrode 131 is not formed, the conductor pattern 177 for the storage capacitor is also not formed.

The data wirings 171, 177, 173, 175, and 179 are the same as the first embodiment, and the lower layer 701 made of chromium or molybdenum or molybdenum alloy or tantalum or titanium and the upper layer 702 made of aluminum or aluminum alloy. It is formed into a double film containing. At this time, each of the drain electrode 175 having the contact portion, the data pad 179, and the conductive pattern 179 for the storage capacitor among the data wires 171, 177, 173, 175, and 179 is formed around the edge of the lower layer 701. A portion of the drain layer 175, the data pad 179, and the conductive pattern 179 for the storage capacitor have a step shape.

The contact layer patterns 163, 165, and 167 lower the contact resistance between the semiconductor patterns 152 and 157 below and the data wires 171, 177, 173, 175, and 179 above the data layer. (171, 177, 173, 175, 179) is exactly the same form. That is, the data line part intermediate layer pattern 163 is the same as the data line parts 171, 179, and 173, the drain electrode intermediate layer pattern 165 is the same as the drain electrode 175, and the storage capacitor intermediate layer pattern 167 is formed. It is the same as the conductor pattern 177 for holding capacitors.

The semiconductor patterns 152 and 157 have the same shape as the data lines 171, 177, 173, 175 and 179 and the ohmic contact layer patterns 163, 165 and 167 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor pattern 157 for the storage capacitor, the conductor pattern 177 for the storage capacitor, and the contact layer pattern 167 for the storage capacitor have the same shape, but the semiconductor pattern 152 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 171, 179, and 173, in particular, the source electrode 173 and the drain electrode 175 are separated, and the data layer intermediate layer 163 and the contact layer pattern for the drain electrode. Although 165 is also separated, the semiconductor pattern 152 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 801 covering the data lines 171, 177, 173, 175, and 179 has contact holes 185, 189, which expose the drain electrode 175, the data pad 179, and the conductive pattern 177 for the storage capacitor. 187 and a contact hole 182 that exposes the gate pad 125 together with the gate insulating layer 140. In this case, all of the contact holes 182, 185, 187, and 189 are formed of the conductive pattern 177 for the storage capacitor, the gate pad 125, the drain electrode 175, and the sidewalls of the data pad 179, in particular, each of the IZOs. The lower layers 201 and 701 having low contact resistance are formed to be exposed.

A pixel electrode 190 is formed on the passivation layer 801 to receive an image signal from the thin film transistor and generate an electric field together with the electrodes of the upper plate. The pixel electrode 190 is made of a transparent conductive material such as indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 175, particularly the lower layer 701 of the drain electrode 175 through the contact hole 185. Connected to receive an image signal. The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 190 is also connected to the conductive pattern 177 for the storage capacitor, particularly the lower layer 701, through the contact hole 187 to transmit the image signal to the conductive pattern 177. On the other hand, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 through the contact holes 182 and 189, respectively, are formed. 179) and supplementing the adhesion between the external circuit device and protecting the pad, are not essential, and their application is optional. Here too, the IZO films 190, 92, and 97 at the contact portion have low contact resistance with the sidewalls of the conductive pattern 177 for the storage capacitor, the gate pad 125, the drain electrode 175, and the data pad 179, in particular the IZO. The branches are in contact with the underlayers 201 and 701.

Although the transparent IZO is mentioned as an example of the material of the pixel electrode 190, it may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.

The structure of the contact unit according to the exemplary embodiment of the present invention may be similarly applied to a thin film transistor array substrate having a color filter on array (COA) structure that forms a color filter on the thin film transistor.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention will be described in detail with reference to FIGS. 12 and 13.

12 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 13 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 12 taken along the line XIII-XIII ′.

Most of the structure is the same as in the first embodiment.

However, the conductive capacitor pattern 177 for the storage capacitor overlaps with the gate line 121 to secure the storage capacitance, and a part of the gate line 121 overlapping with the conductive capacitor pattern 177 for the storage capacitor is for the storage capacitance. It is formed wider than other parts to secure enough.

In addition, red, green, and blue color filters (R) having openings exposing the contact portions of the drain electrode 173 and the conductive capacitor conductor pattern 177 in the pixel region above the gate insulating layer 140 and below the pixel electrode 190. , G, B) are sequentially formed in the longitudinal direction. Here, the boundaries of the color filters R, G, and B of red, green, and blue are shown to coincide with each other on the upper part of the data line 171, but overlapped with each other on the upper part of the data line 171 to leak light between the pixel areas. It may have a function of blocking and is not formed in the pad portion in which the gate and data pads 125 and 179 are formed. Although not illustrated, an interlayer insulating layer made of an insulating material such as silicon oxide or silicon nitride may be formed on the data lines 171, 173, 175, 177, and 179 and the semiconductor pattern 150 not covered by the data lines.

As described above, according to the present invention, the contact portion of the contact portion is formed by contacting the IZO film with aluminum or an aluminum alloy by forming a sidewall of the wiring in a contact shape to expose a conductive film having excellent contact properties with other materials and contacting the IZO film. Can minimize the reliability of the contact portion. In addition, by forming a wiring including a conductive film containing low resistance aluminum or an aluminum alloy, the characteristics of a large screen high definition product can be improved.

Claims (14)

A double layer wiring formed on the substrate and having a stepped sidewall, An insulating film covering the wiring and having at least a part of a boundary line formed outside the wiring to expose the stepped sidewall; A conductive film pattern formed of IZO on the insulating film and in contact with the sidewalls of the wirings having a step shape through the contact holes. Thin film transistor array substrate having a contact portion of the wiring comprising a. In claim 1, The double layer wiring has a contact portion of a wiring made of a lower film of chromium or molybdenum or molybdenum alloy and an upper film of aluminum or aluminum alloy. In claim 1, The lower layer is exposed out of the upper layer, but the conductive layer has a contact portion of a wiring contacting the upper surface of the lower layer. A gate wiring formed on an insulating substrate, A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed over the gate insulating film or the semiconductor layer; A protective film covering the semiconductor layer, A thin film transistor array substrate comprising: a transparent conductive layer pattern connected to the gate line or the data line exposed through a contact hole of the gate insulating layer or the protective layer; The contact portion exposed through the contact hole in the gate wiring or the data wiring has a stepped sidewall, and the transparent conductive layer pattern is in contact with the contact along the stepped sidewall. In claim 4, The gate wiring or the data wiring is a thin film transistor array substrate comprising a lower film of chromium or molybdenum or molybdenum alloy and an upper film of aluminum or aluminum alloy. In claim 5, And the lower layer is exposed out of the upper layer, and the transparent conductive layer pattern is in contact with the upper surface of the lower layer at the contact portion. In claim 4, The transparent conductive film pattern is a thin film transistor array substrate made of IZO. In claim 4, The gate line includes a gate line extending in a horizontal direction, a gate electrode connected to the gate line, and a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line may include a data line extending in a vertical direction, a source electrode connected to the data line, a drain electrode separated from the source electrode and facing the source electrode around the gate electrode, and receiving image signals from the outside. A thin film transistor array substrate comprising a data pad transferring a data line. In claim 8, And the contact hole has first, second, and third contact holes exposing the gate pad together with the drain electrode, the data pad, and the gate insulating layer. In claim 9, The transparent conductive layer pattern may include a pixel electrode contacting the drain electrode through the first contact hole, and an auxiliary data pad or auxiliary data connected to the data pad and the gate pad through the second and third contact holes, respectively. A thin film transistor array substrate comprising a pad. In claim 4, The semiconductor layer except for the channel portion between the source electrode and the drain electrode has the same pattern as the data line. In claim 11, And a resistive contact layer formed between the data line and the semiconductor layer. In claim 9, And the ohmic contact layer has the same pattern as the data line. In claim 4, And a red, green, and blue color filter formed between the data line and the passivation layer.