KR20040008706A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of improving the degree of integration. CONSTITUTION: The first fuses(12) are formed at the upper portion of a substrate(10). An interlayer dielectric(13) is formed at the upper portion of the resultant structure. The second fuses(14) are formed at the upper portion of the interlayer dielectric. At this time, the second fuses are between the first fuses. Preferably, the first fuse is corresponding to a predetermined cell address and the second fuse is corresponding to a lower cell address in comparison with the cell address. Preferably, the first and second fuse are formed by using one selected from a group consisting of a metal line, a word line, a bit line.

Description

Method for fabricating semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory technology, and more particularly, to a manufacturing process of a repair fuse in a semiconductor device manufacturing process.

If any one of a number of microcells is defective in memory device manufacturing, it can not function as a memory and is therefore treated as defective. However, even though only a few cells in the memory have failed, discarding the entire device as a defective product is an inefficient process in terms of yield.

Therefore, the current yield is improved by replacing the defective cells by using spare memory cells (hereinafter, referred to as redundancy cells) previously installed in the memory.

In the repair operation using redundancy cells, spare rows and spare columns are pre-installed in each cell array to repair defective memory cells in row / column units as spare memory cells. It proceeds in such a way that it is described in detail as follows.

In other words, when a defective memory cell is selected through a test after wafer processing is completed, a program is executed in the internal circuit to replace the corresponding address with the address signal of the spare cell. Therefore, when an address signal corresponding to a bad line is input in actual use, the selection is switched to a spare line instead. One of the programming methods is a method of burning a fuse with a laser beam, and the wiring broken by the laser irradiation is called a fuse line, and the broken portion and the area surrounding the fuse box are called a fuse box.

On the other hand, the fuse is not formed separately by an additional process, but is formed using a conductive layer (for example, polysilicon) forming a bit line or a word line. In general, a portion of the insulating film on the repair fuse box region is etched along with the pad etching of the semiconductor device, so it is called a pad / repair etching. Also, in recent years, as the degree of integration and speed of semiconductor memory devices have increased, fuse layers have used metal series.

After the manufacturing process is completed on the wafer, the test is performed. If a defective cell occurs during the test, the fuse is cut by using a laser to repair the redundant cell.

However, as semiconductor devices become more integrated, the gap between fuses can be formed as narrow as other structures. When irradiating and cutting fuses with a laser lamp, damage is caused to neighboring fuses. In other words, the laser irradiated to the fuse causes short circuits with surrounding fuses and cracks in the fuse undercarriage.

In addition, the remaining fuses, which are left at the time of fuse cutting, are frequently generated until they are adsorbed by neighboring fuses to cause electrical shorts, which causes problems in reliability and yield of semiconductor devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device, which is more advantageous for high integration by forming a stack of fuses for replacing defective cells with redundancy circuits.

1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* Explanation of symbols on the main parts of the drawing

10: substrate

11: device isolation film

12: first fuse layer

13: first interlayer insulating film

14: second fuse layer

15: second interlayer insulating film

14: antifuse contact plug

16: third interlayer insulating film

In order to achieve the above object, the present invention comprises the steps of forming a first fuse on the substrate; Forming an interlayer insulating film on the first fuse; And forming a second fuse on the interlayer insulating film in a region where the first fuse is not formed.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

1 through 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

As shown in FIG. 1, the isolation layer 11 is formed on the substrate 10 in the form of a shallow trench isolation. The device isolation layer 11 plays a role when the fuse is irradiated with a laser in a subsequent process.

Subsequently, as shown in FIG. 2, a first fuse layer 12 is formed on the device isolation layer 11. The fuse layer 12 may be formed as a word line or a bit line of the memory device, or may be formed using one of the multilayer metal wires.

Next, as shown in FIG. 3, the first interlayer insulating layer 13 is formed of a silicon oxide film on the first fuse layer 12. Silicon oxide films include HDP (High Density Plasma), Spin On Glass (SOG), undoped silicate glass (USG), Tetra Ethyl Ortho Silicate (TEOS), phosphoro silicate glass (PSG), low pressure TEOS (LP-TEOS), PE- It can be formed using TEOS (Plasma Enhanced TEOS).

Subsequently, as shown in FIG. 4, a second fuse layer 14 is formed on the first interlayer insulating layer 13. At this time, the interval between the second fuse layer 14 is formed on the region where the first fuse layer is not formed in the lower portion, and a predetermined number of fuses are grouped to form an 'a' interval, and the interval between the groups is 'b'. To make it wider than 'a'. At this time, the interval between the first fuselays is 'c'.

In this case, the second fuse layer 14 may be formed of a word line or a bit line of the memory device, or may be formed using one of the multilayer metal wires.

Subsequently, as shown in FIG. 5, a second interlayer insulating film 15 is formed on the second fuse layer 14 as a silicon oxide film. The second interlayer insulating film 15 may be formed using HDP, SOG, USG, TEOS, PSG, LP-TEOS, PE-TEOS, or the like.

Next, as shown in FIG. 6, a third interlayer insulating film is formed on the second fuse layer 15. The third interlayer insulating film may be formed using HDP, SOG, USG, TEOS, PSG, LP-TEOS, PE-TEOS, or the like.

As described above, when the fuses are arranged in a multi-layer, the gap between the fuses is increased to prevent short circuits occurring between neighboring fuses due to residual fuses due to laser irradiation.

Further, by forming the fuses in multiple layers in the same area, more fuses can be formed with less area.

In addition, when the parts repaired by the first and second fuse layers are appropriately combined, the repair process can be performed more efficiently. For example, the first fuse 12 is configured to be connected to the upper address among the addresses to be repaired, and the second fuse 14 is to be connected to the lower address. Subsequently, when the lower address needs to be repaired during the laser repair process, the laser irradiation energy is adjusted so that only the second fuse 14 is insulated, and when the upper address needs to be repaired, the laser irradiation so that the first fuse 12 can be insulated. When the repair process is carried out with energy, the repair process can be effectively performed.

At this time, since the first fuse 113 is connected to the upper address, even if the second fuse 115 on the first fuse 113 is insulated together, there is no problem in the repair process.

In addition, a plurality of lower fuses may be formed as a group for the upper fuse, and the upper fuse may correspond to one upper address, and the lower fuse may be formed to correspond to the lower address of one upper fuse.

In addition, the lower fuse may correspond to a number of low addresses as a repair address, and the upper address may correspond to a column address having a smaller repair address.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, more fuses can be formed in a limited area, and thus a highly integrated semiconductor device can be manufactured in a more limited area.

Claims (5)

Forming a first fuse on the substrate; Forming an interlayer insulating film on the first fuse; And Forming a second fuse on the interlayer insulating film in a region where the first fuse is not formed; Semiconductor device manufacturing method comprising a. The method of claim 1, And the first fuse corresponds to a predetermined cell address, and the second fuse corresponds to a lower cell address than the cell address. The method of claim 1, And the first and second fuses are formed using one selected from metal lines, word lines, and bit lines. The method of claim 1, The interlayer dielectric layer is formed using one selected from among HDP, SOG, USG, TEOS, PSG, LP-TEOS, PE-TEOS. The method of claim 1 And forming a shallow trench type isolation layer, which acts as a buffer in the repair process, between the substrate and the first fuse.