KR20040003974A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20040003974A
KR20040003974A KR1020020039007A KR20020039007A KR20040003974A KR 20040003974 A KR20040003974 A KR 20040003974A KR 1020020039007 A KR1020020039007 A KR 1020020039007A KR 20020039007 A KR20020039007 A KR 20020039007A KR 20040003974 A KR20040003974 A KR 20040003974A
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KR
South Korea
Prior art keywords
tungsten
film
semiconductor device
contact plug
contact
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KR1020020039007A
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Korean (ko)
Inventor
하승철
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주식회사 하이닉스반도체
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Priority to KR1020020039007A priority Critical patent/KR20040003974A/en
Publication of KR20040003974A publication Critical patent/KR20040003974A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of easily obtaining a stable tungsten contact plug by using simplified processes. CONSTITUTION: An interlayer dielectric is formed on a semiconductor substrate(30) having a lower conductive pattern(31). A contact hole is formed to expose the lower conductive pattern by selectively etching the interlayer dielectric. A tungsten contact plug(42a,42b) is formed by filling a tungsten film in the contact hole using ALD(Atomic Layer Deposition). Then, a metal interconnection is formed to connect the tungsten contact plug.

Description

반도체 장치의 제조방법{Method for fabricating semiconductor device}Method for fabricating semiconductor device

본 발명은 반도체 장치의 제조기술에 관한 것으로, 특히 반도체 장치의 콘택플러그에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly to a contact plug of a semiconductor device.

반도체 소자, 특히 디램(DRAM)이 고집적화 되어 감에 따라 워드 라인, 비트 라인등과 같은 도전성 패턴들은 그 간격이 점점 줄어들고 있고 있으며, 콘택 영역 또한 그 크기가 줄어들고 있다. 콘택 영역의 마진이 충분할 경우에는 포토레지스트 패턴을 마스크로 한 일반적인 식각 공정으로 콘택홀을 형성하고, 이 콘택홀과 배선 영역에 도전성 물질을 매립하여 하부 도전층과 전기적으로 연결하였다.As semiconductor devices, especially DRAMs, have become highly integrated, conductive patterns such as word lines, bit lines, and the like are becoming smaller, and contact areas are also decreasing in size. When the contact region had sufficient margin, a contact hole was formed by a general etching process using a photoresist pattern as a mask, and a conductive material was buried in the contact hole and the wiring region to be electrically connected to the lower conductive layer.

그러나, 소자가 점점 고집적화 되어감에 따라 콘택영역의 마진이 부족하여 자기정렬 콘택 공정을 통해 콘택홀을 형성하는 방식이 도입되었다. 또한, 콘택홀의 크기가 작아짐에 따라 배선에 사용되는 도전성 물질로 콘택홀을 양호하게 매립하기 어려워 매립 특성이 우수한 도전성 물질을 사용하여 콘택홀만을 매립시키는 콘택 플러그 방식이 널리 채택되고 있다.However, as devices are becoming more and more integrated, a method of forming contact holes through self-aligned contact processes has been introduced due to a lack of margin of contact regions. In addition, as the size of the contact hole decreases, it is difficult to fill the contact hole with a conductive material used for wiring, and a contact plug method for filling only the contact hole using a conductive material having excellent embedding characteristics has been widely adopted.

주로, 도핑된(Doping) 폴리 실리콘을 이용하여 콘택플러그를 형성하나, 최근에는 도핑된 폴리 실리콘보다 상대적으로 저항이 낮은 텅스텐 플러그를 주로 사용하고 있다.In general, contact plugs are formed using doped polysilicon, but recently, tungsten plugs having lower resistance than doped polysilicon are mainly used.

도1a에 내지 도1d는 종래기술에 의한 반도체 장치의 콘택플러그 제조방법을 보여주는 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a contact plug of a semiconductor device according to the prior art.

도1a에 도시된 바와 같이, 먼저 활성영역(11') 및 게이트 패턴(11)이 형성된 기판(10)에 제1 층간절연막(12)을 형성하고 활성영역(11')이 노출되도록 층간절연막(12)을 선택적으로 식각하여 콘택홀을 형성한다. 콘택홀에 도전성물질을 매립하여 스토리지노드 콘택플러그(13)를 형성한다. 이어서 하부전극(15) 유전체 박막(16), 상부전극(17)으로 구성되는 캐패시터를 형성하고 제2 층간절연막(14)을 형성한다.As shown in FIG. 1A, a first interlayer insulating film 12 is first formed on a substrate 10 on which an active region 11 ′ and a gate pattern 11 are formed, and an interlayer insulating film is formed so that the active region 11 ′ is exposed. 12) is selectively etched to form contact holes. The storage node contact plug 13 is formed by filling a conductive material in the contact hole. Subsequently, a capacitor including the lower electrode 15 dielectric thin film 16 and the upper electrode 17 is formed, and a second interlayer insulating film 14 is formed.

이어서 캐패시터의 상부전극(17)과 연결되는 금속배선(18)을 형성하고, 제3 층간절연막(19)를 형성한다.Subsequently, a metal wiring 18 connected to the upper electrode 17 of the capacitor is formed, and a third interlayer insulating film 19 is formed.

이어서 도1b에 도시된 바와 같이, 제1 내지 제3 층간절연막(12,14,19)을 선택적으로 식각하여 금속배선(18)이 노출되는 콘택홀(20a)과, 게이트패턴(11)이 노출되는 콘택홀(20b)을 형성한다.Subsequently, as illustrated in FIG. 1B, the first to third interlayer insulating films 12, 14, and 19 are selectively etched to expose the contact holes 20a exposing the metal lines 18 and the gate patterns 11. A contact hole 20b is formed.

이어서 도1c에 도시된 바와 같이, 콘택홀(20a,20b)의 바닥및 측벽을 포함하는 기판전면에 TiN/Ti막(21)을 형성한다. 여기서 형서된 TiN/Ti막(21)은 후속공정에서 형성될 텅스텐과 층간절연막과의 접착막으로 사용된다.Subsequently, as shown in FIG. 1C, a TiN / Ti film 21 is formed on the front surface of the substrate including the bottom and sidewalls of the contact holes 20a and 20b. The TiN / Ti film 21 formed here is used as an adhesive film between tungsten and an interlayer insulating film to be formed in a subsequent step.

이어서 도1d에 도시된 바와 같이, 텅스텐으로 콘택홀(20a,20b)을 매립하여 텅스텐 콘택플러그(23a,23b)를 형성한다. 여기서 텅스텐을 콘택플러그는 WF6소스가스와 H2반응가스를 사용하여 화학적기상증착법(Chemical vapor deposition)으로 콘택홀(20a,20b)이 매립되도록 텅스텐막을 증착한 다음, 에치백 공정이나 화학적기계적연마공정을 이용하여 콘택홀 내부만 남기기도록 텅스텐막을 제거하여 형성한다.1D, the contact holes 20a and 20b are filled with tungsten to form the tungsten contact plugs 23a and 23b. Here, the tungsten contact plug is deposited using a WF 6 source gas and a H 2 reaction gas to deposit the tungsten film to fill the contact holes 20a and 20b by chemical vapor deposition, followed by an etch back process or chemical mechanical polishing. The tungsten film is removed to leave only the inside of the contact hole by using the process.

상기와 같이 콘택플러그를 형성할 때에 전도성이 좋은 텅스텐을 주로 사용하고 있으나 화학기상증착법으로 텅스텐플러그를 형성할 때에 텅스텐과 산화막계열의 층간절연막과의 접착에 문제가 있기 때문에, 이를 보완하기 위해 접착막으로 TiN/Ti막(21)을 사용하고 있다.Tungsten with good conductivity is mainly used to form the contact plug as described above. However, when the tungsten plug is formed by chemical vapor deposition, there is a problem in the adhesion between the tungsten and the interlayer insulating film of the oxide film series. TiN / Ti film 21 is used.

따라서 TiN/Ti막(21)을 형성함으로서 추가적인 공정스텝이 증가하게 되고, 또한 반도체 장치가 고집적화 되면서 콘택홀의 어스펙트 비(aspect ratio)가 커지면서 접착막으로 사용되는 TiN/Ti막의 스텝커버리지(step coverage) 문제가 생기게 된다.Therefore, by forming the TiN / Ti film 21, an additional process step is increased, and as the semiconductor device becomes highly integrated, the aspect ratio of the contact hole increases, and step coverage of the TiN / Ti film used as the adhesive film is increased. ) Will cause problems.

본 발명은 고집적 반도체 장치에서 보다 단순화된 공정으로 안정적인 텅스텐 콘택플러그를 형성하는 반도체 장치의 제조방법을 제공함을 목적으로 한다.It is an object of the present invention to provide a method for manufacturing a semiconductor device which forms a stable tungsten contact plug in a more simplified process in a highly integrated semiconductor device.

도1a에 내지 도1d는 종래기술에 의한 반도체 장치의 제조방법을 보여주는 공정단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도2a 내지 도2d는 본 발명의 바람직한 실시예에 따른 반도체 장치의 콘택플러그 제조방법을 보여주는 공정단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a contact plug in a semiconductor device according to a preferred embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

30 : 기판30: substrate

31 : 게이트패턴31: gate pattern

32 : 제1 층간절연막32: first interlayer insulating film

33 : 스토리지노드 콘택플러그33: Storage Node Contact Plug

34 : 제2 층간절연막34: second interlayer insulating film

35,36,37 : 캐패시터35,36,37: Capacitor

38 : 금속배선38: metal wiring

39 : 제3 층간절연막39: third interlayer insulating film

40a,40b : 콘택플러그40a, 40b: Contact Plug

41 : 텅스텐막41: tungsten film

42 : 텅스텐 콘택플러그42: Tungsten Contact Plug

상기의 목적을 달성하기 위한 본 발명은 하부 전도막 패턴이 형성된 기판상에 층간절연막을 형성하는 단계; 상기 전도막 패턴이 노출되도록 상기 층간절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계; 단원자증착법을 이용하여 상기 콘택홀내에 텅스텐막을 채워 텅스텐 콘택플러그를 형성하는 단계; 및 상기 텅스텐 콘택플러그와 연결되는 금속배선을 형성하는 단계를 포함하는 반도체 장치의 제조방법을 제공한다.The present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a substrate on which the lower conductive film pattern is formed; Selectively removing the interlayer insulating layer to expose the conductive layer pattern to form a contact hole; Forming a tungsten contact plug by filling a tungsten film in the contact hole by using monoatomic deposition; And forming a metal wiring connected to the tungsten contact plug.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도2a 내지 도2d는 본 발명의 바람직한 실시예에 따른 반도체 장치의 콘택플러그 제조방법을 보여주는 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a contact plug in a semiconductor device according to an embodiment of the present invention.

도2a에 도시된 바와 같이, 먼저 활성영역(31') 및 게이트 패턴(31)이 형성된 기판(30)에 제1 층간절연막(32)을 형성하고 활성영역(31')이 노출되도록 층간절연막(32)을 선택적으로 식각하여 콘택홀을 형성한다. 콘택홀에 도전성물질을 매립하여 스토리지노드 콘택플러그(33)를 형성한다. 이어서 하부전극(35) 유전체 박막(36), 상부전극(37)으로 구성되는 캐패시터를 형성하고 제2 층간절연막(34)을 형성한다.As shown in FIG. 2A, first, an interlayer insulating layer 32 is formed on a substrate 30 on which an active region 31 ′ and a gate pattern 31 are formed, and the active region 31 ′ is exposed. 32) is selectively etched to form contact holes. The storage node contact plug 33 is formed by filling a conductive material in the contact hole. Subsequently, a capacitor including the lower electrode 35 dielectric thin film 36 and the upper electrode 37 is formed, and a second interlayer insulating film 34 is formed.

이어서 캐패시터의 상부전극(37)과 연결되는 금속배선(38)을 형성하고, 제3 층간절연막(39)를 형성한다.Subsequently, a metal wiring 38 connected to the upper electrode 37 of the capacitor is formed, and a third interlayer insulating film 39 is formed.

이어서 도2b에 도시된 바와 같이, 제1 내지 제3 층간절연막(32,34,39)을 선택적으로 식각하여 금속배선(38)이 노출되는 콘택홀(40a)과, 게이트패턴(31)이 노출되는 콘택홀(40b)을 형성한다.Subsequently, as illustrated in FIG. 2B, the first to third interlayer insulating layers 32, 34, and 39 are selectively etched to expose the contact holes 40a exposing the metal wiring 38 and the gate patterns 31. A contact hole 40b is formed.

이어서 도2c에 도시된 바와 같이, 텅스텐막(41)을 단원자층증착법을 이용하여 콘택홀(40a,40b)이 매립되도록 형성한다. 이전에는 반응식1과 같은 반응을 이용하여 텅스텐막을 화학적기상증착법으로 형성하였다.Next, as shown in FIG. 2C, the tungsten film 41 is formed so as to fill the contact holes 40a and 40b by using monoatomic layer deposition. Previously, the tungsten film was formed by chemical vapor deposition using the same reaction as in Scheme 1.

WF6(g) + 3/2SiO2↔ W(c)+3/2 SiF4(g) + 3/2O2(g)의WF 6 (g) + 3 / 2SiO 2 ↔ W (c) +3/2 SiF4 (g) + 3 / 2O2 (g)

그러나 반응식1은 역반응만이 가능하여 텅스텐막을 산화막계열의 층간절연막상에 증착이 잘되지 않았었다.However, the reaction formula 1 was only capable of reverse reaction, so that the tungsten film was not deposited well on the interlayer insulating film of the oxide film series.

(1) WFx + Si2H6(g) → W - SiHyFz + 2H2(g) + SiHaFb(g)(1) WFx + Si 2 H 6 (g) → W-SiHyFz + 2H 2 (g) + SiHaFb (g)

(2) W - SiHyFz + WF6(g) → W - WFx + SiHaFb(g)(2) W-SiHyFz + WF 6 (g) → W-WFx + SiHaFb (g)

이에 본 발명은 반응식2와 같은 반응을 유도하는 단원자증착법을 이용하여 2스텝으로 텅스텐을 형성한다. 즉, WH6을 소스가스로 사용하고 SiH4또는 Si2H6을 반응가스로 하여 단원자증착법을 이용하면 산화막계열의 층간절연막에도 텅스텐막이 잘 형성되는 것이다.Therefore, the present invention forms tungsten in two steps by using monoatomic deposition to induce a reaction as in Scheme 2. In other words, if the single gas deposition method is used using WH 6 as the source gas and SiH 4 or Si 2 H 6 as the reaction gas, the tungsten film is well formed in the interlayer insulating film of the oxide film series.

이 때 단원자증착 공정시 증착온도는 200 ~ 500℃범위에서 공정을 진행한다.At this time, the deposition temperature during the monoatomic deposition process proceeds in the range of 200 ~ 500 ℃.

이어서 도2d에 도시된 바와 같이, 콘택홀(40a,40b)내부에만 텅스텐막이 남도록 에치백 공정이나 또는 화학적기계적연막 공정을 진행하여 텅스텐 콘택플러그(42a,42b)를 형성한다. 이어서 텅스텐 콘택플러그(42a,42b)와 연결되는 알루미늄 금속배선을 형성한다.Next, as shown in FIG. 2D, the tungsten contact plugs 42a and 42b are formed by performing an etch back process or a chemical mechanical smoke deposition process so that the tungsten film remains only in the contact holes 40a and 40b. Subsequently, aluminum metal wires connected to the tungsten contact plugs 42a and 42b are formed.

상기에서 설명한 텅스텐 콘택플러그는 게이트와 금속배선을 연결하는 콘택플러그 제조시에 사용가능할 뿐만 아니라, 비트라인과 금속배선을 형성하는 콘택플러그에도 사용가능하며, 또한 다른 부분에 제조되는 콘택플러그에도 사용가능하다.The tungsten contact plug described above can be used not only in the manufacture of a contact plug connecting the gate and the metal wiring, but also in the contact plug forming the bit line and the metal wiring, and also in the contact plug manufactured in other parts. Do.

본 발명에 의해 Ti와 TiN막 고정을 생략함으로써 콘택홀 공정을 단순화할 수 있으며, 단원자증착법을 이용하기 때문에 어스펙트 비가 큰 콘택홀에도 안정적으로 사용가능하다. 또한 비트라인 또는 게이트패턴등에 Ti와 TiN막 없이 바로 텅스텐이 연결되기 때문에 콘택저항 또한 최소화 할 수 있다.According to the present invention, the contact hole process can be simplified by omitting the Ti and TiN film fixing, and since the single-electron deposition method is used, it can be stably used even in contact holes having a high aspect ratio. In addition, since tungsten is directly connected to the bit line or gate pattern without the Ti and TiN layers, contact resistance can be minimized.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명에 의해 단순화된 공정으로 텅스테 콘택플러그를 안정적으로 형성할 수 있어 저렴한 비용으로 신뢰성 높은 반도체 장치를 제조할 수 있다.According to the present invention, a tungsten contact plug can be stably formed by a simplified process, thereby manufacturing a highly reliable semiconductor device at low cost.

Claims (3)

하부 전도막 패턴이 형성된 기판상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the substrate on which the lower conductive film pattern is formed; 상기 전도막 패턴이 노출되도록 상기 층간절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계;Selectively removing the interlayer insulating layer to expose the conductive layer pattern to form a contact hole; 단원자증착법을 이용하여 상기 콘택홀내에 텅스텐막을 채워 텅스텐 콘택플러그를 형성하는 단계; 및Forming a tungsten contact plug by filling a tungsten film in the contact hole by using monoatomic deposition; And 상기 텅스텐 콘택플러그와 연결되는 금속배선을 형성하는 단계Forming a metal wire connected to the tungsten contact plug; 를 포함하는 반도체 장치의 제조방법.Method for manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 단원자증착법은 WH6을 소스가스로, SiH4또는 Si2H6을 반응가스로 하여 텅스텐막을 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method for producing a semiconductor device according to the above method, wherein the monoatomic deposition method forms a tungsten film using WH 6 as a source gas and SiH 4 or Si 2 H 6 as a reaction gas. 제 2 항에 있어서,The method of claim 2, 상기 단원자증착법은 200 ~ 500 ℃ 범위의 온도에서 형성하는 것을 것을 특징으로 하는 반도체 장치의 제조방법.The monoatomic deposition method is a method of manufacturing a semiconductor device, characterized in that formed at a temperature in the range of 200 ~ 500 ℃.
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