KR19990032597A - Wiring Formation Method of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method for forming a wiring of a semiconductor device, comprising the steps of: forming a first wiring on a predetermined portion on a substrate and forming an interlayer insulating layer covering the first wiring; and the first wiring of the first interlayer insulating layer; Forming a trench by etching a corresponding portion and a predetermined portion by a predetermined depth; forming a sidewall on a side surface of the trench; and etching the bottom surface of the trench corresponding to the first wiring to form the first wiring. Forming a contact hole for exposing and depositing a conductive metal in contact with the first wiring through the trench and the contact hole on the interlayer insulating layer, and removing the remaining portions except for the portion corresponding to the trench; It comprises a step of forming a. Therefore, since the second wiring is thinly formed on the interlayer insulating layer, the topography of the surface can be improved to facilitate subsequent processes, and the second wiring can be formed to fill the trench, so that the resistance can be reduced.

Description

Wiring Formation Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method of a semiconductor device, and more particularly, to a wiring forming method of a semiconductor device capable of improving surface flatness and reducing specific resistance.

1A to 1C are process drawings showing a wiring forming method of a semiconductor device according to the prior art.

Referring to FIG. 1A, a first wiring 13 may be formed by depositing polysilicon or a conductive metal doped with impurities on a substrate 11 and patterning the photolithography method. The substrate 11 may be a semiconductor substrate or an interlayer insulating layer. In addition, an insulating material such as silicon oxide, BSG (Boro Silicate Glass), PSG (Phospho Silicate Glass), or BPSG (Boro Phospho Silicate Glass) on the substrate 11 is referred to as chemical vapor deposition (hereinafter, referred to as CVD). The interlayer insulating layer 15 is formed by depositing to cover the first wiring 13 by the method.

Referring to FIG. 1B, the photoresist 16 is deposited, exposed, and developed on the interlayer insulating layer 15 to be patterned to expose a portion corresponding to the first wiring 13 of the interlayer insulating layer 15. Then, using the photoresist 16 as a mask, the exposed portion of the interlayer insulating layer 15 is etched to form a contact hole 17 exposing the first wiring 13.

At this time, the contact hole 17 is formed by isotropically etching the interlayer insulating layer 15 to a predetermined depth and then anisotropically etching until the first wiring 13 is continuously exposed. Therefore, the upper side of the contact hole 17 is inclined.

Referring to FIG. 1C, the photoresist 16 remaining on the interlayer insulating layer 15 is removed. Then, a conductive metal is deposited on the interlayer insulating layer 15 to be in contact with the first wiring 13 through the contact hole 17. At this time, since the side surface of the upper portion of the contact hole 17 is inclined, the coating property of the conductive metal is improved. The conductive metal is patterned by the photolithography method so that the portion in contact with the first wiring 13 and the predetermined portion remain, thereby forming the second wiring 19.

However, the above-described wiring forming method according to the related art has a problem in that since the second wiring is thickly formed on the interlayer insulating layer, the topography of the surface is lowered, which makes the subsequent process difficult. In addition, in order to prevent the topography of the surface from being lowered, there is a problem in that the resistance is increased when the second wiring is thinly formed.

Accordingly, it is an object of the present invention to provide a method for forming a wiring in a semiconductor device which can improve the topography of the surface and facilitate the subsequent steps.

Another object of the present invention is to provide a wiring forming method of a semiconductor device capable of reducing resistance.

A wiring forming method of a semiconductor device according to the present invention for achieving the above objects is a step of forming a first wiring on a predetermined portion on a substrate and forming an interlayer insulating layer covering the first wiring, and the first interlayer insulating layer of Forming a trench by etching a portion and a predetermined portion corresponding to the first wiring by a predetermined depth, forming a sidewall on a side surface of the trench, and etching a bottom surface of the trench corresponding to the first wiring Forming a contact hole for exposing the first wiring, and depositing a conductive metal in contact with the first wiring through the trench and the contact hole on the interlayer insulating layer, and leaving the remaining portions except the portion corresponding to the trench. It removes and forms a 2nd wiring.

1A to 1C are process diagrams showing a wiring forming method of a semiconductor device according to the prior art.

2A to 2D are process diagrams showing a wiring forming method of a semiconductor device according to the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are process diagrams showing a wiring formation method of a semiconductor device according to the present invention.

Referring to FIG. 2A, the first wiring 33 may be formed by depositing polycrystalline silicon or a conductive metal doped with impurities on the substrate 31 and patterning the photolithography method. The substrate 31 may be a semiconductor substrate or an interlayer insulating layer. Then, an insulating material such as silicon oxide, BSG, PSG, or BPSG is deposited on the substrate 31 to a thickness of about 12000 to 20000 kPa by CVD to form an interlayer insulating layer 35 covering the first wiring 33.

The first photoresist 26 is deposited, exposed to light, and developed on the interlayer insulating layer 35, and then patterned to expose portions and portions corresponding to the first wiring 23 of the interlayer insulating layer 25. Using the photoresist 26 as a mask, the exposed portion of the interlayer insulating layer 25 is etched to a predetermined depth, for example, a depth of about 7000 to 12000 kPa to form the trench 27.

Referring to FIG. 2B, the first photoresist 26 remaining on the interlayer insulating layer 25 is removed. The conductive side wall 29 is formed on the side surface of the trench 27 by depositing a conductive metal such as polycrystalline silicon or aluminum doped with impurities to fill the trench 27 on the interlayer insulating layer 25. do.

Referring to FIG. 2C, the second photoresist 31 is coated on the interlayer insulating layer 25, and then exposed and developed to form a trench 27 in a portion corresponding to the first wiring 23 of the interlayer insulating layer 25. ) To be exposed. Then, using the second photoresist 31 as a mask, the contact hole 33 is anisotropically etched so that the first wiring 23 is exposed to the exposed portion of the interlayer insulating layer 25 on the bottom of the trench 27. Form. At this time, the conductive side wall 29 serves as a mask so that the size of the contact hole 33 is smaller than the bottom surface of the trench 27.

Referring to FIG. 2D, the second photoresist 31 remaining on the interlayer insulating layer 25 is removed. Then, a conductive metal such as aluminum, gold, silver or copper is deposited on the interlayer insulating layer 25 so as to be in contact with the first wiring 23 through the contact hole 33 and the trench 27. At this time, since the conductive side wall 29 formed on the side surface of the trench 27 is inclined, the coating property of the conductive metal is improved. In addition, since the trench 27 is filled even when the conductive metal layer is thinly formed, the contact hole 33 is electrically connected to not only the first wiring 23 but also the conductive side wall 29 formed on the side of the trench 27. .

The second wiring 35 is formed by patterning the conductive metal by photolithography so that only the portion corresponding to the trench 27 remains. In the above, since the second wiring 35 is formed thin on the interlayer insulating layer 25, the topography of the surface is improved and also formed to fill the trench 27, so that the cross-sectional area is increased and the resistance is reduced.

As described above, in the wiring forming method according to the present invention, even if a thin conductive metal is formed on the interlayer insulating layer, the wiring is contacted and electrically connected to the first wiring through the contact hole, and fills the trench having the conductive side wall on the side surface.

Therefore, the present invention can thinly form the second wiring on the interlayer insulating layer, thereby improving the topography of the surface, thereby facilitating subsequent processes, and reducing the resistance by forming the second wiring to fill the trench. There is an advantage to this.

Claims (4)

Forming a first wiring on a predetermined portion on the substrate and forming an interlayer insulating layer covering the first wiring; Etching a portion and a predetermined portion of the first interlayer insulating layer corresponding to the first wiring to form a trench; Forming a sidewall on the side of the trench; Etching a bottom surface of the trench corresponding to the first wiring to form a contact hole for exposing the first wiring; And depositing a conductive metal in contact with the first wiring through the trench and the contact hole on the interlayer insulating layer, and removing a portion other than the portion corresponding to the trench to form a second wiring. Wiring formation method. The method for forming a wiring of a semiconductor device according to claim 1, wherein the interlayer insulating layer is deposited to a thickness of 12000 to 20000 GPa. The wiring forming method of claim 1, wherein the trench is formed by etching the interlayer insulating layer to a depth of 7000 to 12000 μs. The wiring forming method of claim 1, wherein the sidewall is formed of a conductive metal of polycrystalline silicon or aluminum doped with impurities.