KR20080074504A - Semiconductor device and method of manufacturing thereof - Google Patents

Semiconductor device and method of manufacturing thereof Download PDF

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KR20080074504A
KR20080074504A KR1020070013713A KR20070013713A KR20080074504A KR 20080074504 A KR20080074504 A KR 20080074504A KR 1020070013713 A KR1020070013713 A KR 1020070013713A KR 20070013713 A KR20070013713 A KR 20070013713A KR 20080074504 A KR20080074504 A KR 20080074504A
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forming
etch stop
insulating film
film
layer
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길민철
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A semiconductor device and a manufacturing method thereof are provided to minimize a change of contact resistance between an upper metal layer and a lower metal layer by preventing an etching effect of the lower metal layer. A first insulating layer(101) and a second insulating layer(103) are sequentially formed on a semiconductor substrate(100). A contact hole for exposing a contact region of the first insulating layer is formed by etching the second insulating layer. A metal line is formed within the contact hole. An etch stop conducting layer(105) is formed on an upper part of the metal line. A third insulating layer(107) is formed on the entire structure including the etch stop conducting layer. A via hole(108) is formed to expose the etch stop conducting layer.

Description

반도체 소자 및 그것의 제조 방법{Semiconductor device and Method of manufacturing thereof}Semiconductor device and method of manufacturing the same

도 1은 종래의 반도체 소자의 제조 방법을 설명하기 위한 반도체 기판 일부의 단면도이다.1 is a cross-sectional view of a portion of a semiconductor substrate for explaining a conventional method for manufacturing a semiconductor device.

도 2 내지 도 6은 본 발명의 일실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 반도체 기판 일부의 단면도들이다.2 to 6 are cross-sectional views of a part of a semiconductor substrate for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100 : 반도체 기판 101 : 제1 절연막100 semiconductor substrate 101 first insulating film

102 : 제1 식각 정지 절연막 103 : 제2 절연막102: first etch stop insulating film 103: second insulating film

104 : 상부 금속층 105 : 식각 정지 도전층104: upper metal layer 105: etch stop conductive layer

106 : 제2 식각 정지 절연막 107 : 제3 절연막106: second etching stop insulating film 107: third insulating film

108 : 비아홀108: via hole

본 발명은 반도체 소자 및 그것의 제조 방법에 관한 것으로, 특히 다층 금속 배선 패턴을 포함하는 반도체 소자 및 그것의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a multilayer metal wiring pattern and a method for manufacturing the same.

일반적으로, 반도체 소자 제조시 넓은 활성영역의 확보를 위하여 데이타 전송을 담당하는 금속 배선을 주로 다층으로 형성하게 되며, 비아홀을 이용하여 다층 금속 배선 사이를 연결하여 왔다.In general, in the manufacture of semiconductor devices, in order to secure a wide active area, metal wires for data transmission are mainly formed in multiple layers, and via holes are used to connect the multilayer metal wires.

종래의 반도체 소자의 제조방법은 다마신(Damascene) 공정을 이용한 금속배선 공정을 실시한다. 절연막을 식각하여 비아홀을 형성한 후, 비아홀을 포함한 전체 구조 상에 금속막을 증착 및 금속막의 화학적 기계적 연마(Chemical Mechanical Polishing)를 통해 금속 배선을 형성한다.The conventional method for manufacturing a semiconductor device performs a metal wiring process using a damascene process. After the insulating film is etched to form the via hole, a metal film is formed on the entire structure including the via hole, and the metal wiring is formed through chemical mechanical polishing of the metal film.

도 1은 종래의 반도체 소자의 제조 방법을 설명하기 위한 반도체 기판 일부의 단면도이다.1 is a cross-sectional view of a portion of a semiconductor substrate for explaining a conventional method for manufacturing a semiconductor device.

도 1을 참조하면, 상부에 복수의 단위 소자 패턴들(미도시)을 포함하는 반도체 기판(10) 상에 제1 절연막(11) 및 제2 절연막(12)을 순차적으로 형성한다. 이 후, 식각 공정을 실시하여 제 1 절연막(11)의 플러그가 연결될 부분이 노출되도록 콘택홀을 형성한 후, 콘택홀이 매립되도록 금속 물질을 증착한다. 이 후, CMP 공정을 실시하여 하부 금속층(13)을 형성한다. 이 후, 하부 금속층(13)을 포함하는 전체 구조 상에 식각 정지막(14) 및 제3 층간 절연막(15)을 순차적으로 증착한다. 이 후, 식각 공정을 실시하여 상기 하부 금속층(13)의 상부가 노출되는 비아홀(16)을 형성한다.Referring to FIG. 1, a first insulating layer 11 and a second insulating layer 12 are sequentially formed on a semiconductor substrate 10 including a plurality of unit device patterns (not shown) thereon. Thereafter, an etching process is performed to form a contact hole to expose a portion to which the plug of the first insulating layer 11 is to be connected, and then a metal material is deposited to fill the contact hole. Thereafter, the lower metal layer 13 is formed by performing a CMP process. Thereafter, the etch stop layer 14 and the third interlayer insulating layer 15 are sequentially deposited on the entire structure including the lower metal layer 13. Thereafter, an etching process is performed to form a via hole 16 through which the upper portion of the lower metal layer 13 is exposed.

상술한 바와 같이 종래 기술에 따른 반도체 소자의 제조 방법은 바람직하게 는 식각 정지막(14)만이 식각되어야 하지만, 도 1에 도시된 것과 같이, 상기 하부 금속층(13)의 일부도 식각되는 현상(즉, 펀치(punch) 현상)이 발생되는 문제점이 있다. 이렇게, 상기 하부 금속층(13)이 식각될 경우, 하부 금속층(13)과 후속 형성되는 상부 금속층을 연결하는 플러그의 접촉 저항 값이 변경되고, 결국 반도체 소자의 양산시 양품률(yield) 특성이 저하되는 문제점이 있다. 이를 방지하기 위해, 상기 하부 금속층(13)의 두께를 증가시킴으로써, 펀치 마진(punch margin)이 확보될 수도 있지만, 고집적 반도체 소자의 경우 상기 하부 금속층(13)의 두께를 증가시키는 데는 한계가 있다. 또한, 상기 하부 금속층(13)의 두께가 증가될 경우, 상기 하부 금속층(13)이 패터닝될 때, 식각되어야할 금속층의 두께가 증가된다.As described above, in the method of manufacturing a semiconductor device according to the related art, only the etch stop layer 14 should be etched. However, as shown in FIG. 1, a part of the lower metal layer 13 is also etched (ie, , A punch phenomenon occurs. As such, when the lower metal layer 13 is etched, the contact resistance value of the plug connecting the lower metal layer 13 and the upper metal layer subsequently formed is changed, resulting in a decrease in yield characteristics during mass production of the semiconductor device. There is a problem. In order to prevent this, by increasing the thickness of the lower metal layer 13, a punch margin may be secured, but in the case of highly integrated semiconductor devices, there is a limit in increasing the thickness of the lower metal layer 13. In addition, when the thickness of the lower metal layer 13 is increased, when the lower metal layer 13 is patterned, the thickness of the metal layer to be etched is increased.

따라서, 본 발명이 이루고자 하는 기술적 과제는 하부 금속층 상부에 식각 정지 도전층을 형성함으로써, 절연막에 하부 금속층과 상부 금속층간의 플러그용 비아홀 형성시 하부 금속층의 식각을 방지하여, 상부 금속층과 하부 금속층간의 접촉 저항 값의 변화를 최소화하고, 반도체 소자의 양산시 양품률 특성을 향상시킬 수 있는 반도체 소자 및 그것의 제조 방법을 제공하는 데 있다.Accordingly, the technical problem to be achieved by the present invention is to form an etch stop conductive layer on the lower metal layer, thereby preventing the etching of the lower metal layer when forming a via hole for the plug between the lower metal layer and the upper metal layer in the insulating film, thereby preventing the upper metal layer from the lower metal layer. It is to provide a semiconductor device and a method of manufacturing the same that can minimize the change in the value of the contact resistance of the semiconductor device, and improve the yield rate characteristics during mass production of the semiconductor device.

본 발명의 일실시 예에 따른 반도체 소자는 반도체 기판 상에 순차적으로 형성된 제1 절연막 및 제2 절연막과, 상기 제2 절연막을 관통하여 상기 제1 절연막과 연결되는 금속 배선과, 상기 금속 배선 상부에 형성된 식각 정지 도전막, 및 상기 식각 정지 도전막 상부의 일부 또는 전체를 포함하는 영역이 노출되도록 형성된 비아홀을 포함한다. According to an embodiment of the present invention, a semiconductor device may include a first insulating film and a second insulating film sequentially formed on a semiconductor substrate, a metal wiring penetrating the second insulating film and connected to the first insulating film, and an upper portion of the metal wiring. The formed etch stop conductive layer and a via hole formed to expose a region including a part or the whole of the upper portion of the etch stop conductive layer.

상기 비아홀 내에 형성된 플러그를 더 포함하며, 상기 식각 정지 도전막은 TiN막으로 형성된다.And a plug formed in the via hole, wherein the etch stop conductive layer is formed of a TiN layer.

본 발명의 일실시 예에 따른 반도체 소자의 제조 방법은 반도체 기판 상에 제1 절연막 및 제2 절연막을 순차적으로 형성하는 단계와, 상기 제2 절연막을 식각하여 상기 제1 절연막의 콘택 영역이 노출되는 콘택홀을 형성하는 단계와, 상기 콘택홀 내에 금속 배선을 형성하는 단계와, 상기 금속 배선 상부에 식각 정지 도전막을 형성하는 단계와, 상기 식각 정지 도전막을 포함한 전체 구조 상에 제3 절연막을 형성하는 단계, 및 상기 식각 정지 도전막이 노출되는 비아홀을 형성하는 단계를 포함한다.According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and etching the second insulating film to expose a contact region of the first insulating film. Forming a contact hole, forming a metal wiring in the contact hole, forming an etch stop conductive film on the metal wire, and forming a third insulating film on the entire structure including the etch stop conductive film. And forming a via hole through which the etch stop conductive layer is exposed.

상기 비아홀을 형성한 후, 상기 비아홀을 금속 물질로 채워 플러그를 형성하는 단계를 더 포함하며, 상기 식각 정지 도전막을 형성하는 단계는 상기 금속 배선을 포함하는 전체 구조 상에 도전막을 형성하는 단계, 및 패터닝 공정을 실시하여 상기 금속 배선 상부에 상기 도전막을 잔류시켜 상기 식각 정지 도전막을 형성하는 단계를 포함한다. 상기 식각 정지 도전막은 TiN막으로 형성한다. After the via hole is formed, the method may further include filling the via hole with a metal material to form a plug. The forming of the etch stop conductive film may include forming a conductive film on the entire structure including the metal wires, and Performing a patterning process to form the etch stop conductive film by remaining the conductive film on the metal wiring. The etch stop conductive film is formed of a TiN film.

상기 패터닝 공정은 주식각 가스로 Chlorine("cl" 함유한 Cl2)/Fluorine("F" 함유한 CxHyFz계열 )로 사용하고 보조 식각 가스로 Ar,O2를 사용하여 실시하며, 상기 패터닝 공정은 고선택비를 가지기 위하여 Cl2 : CHF3 의 프로우양(sccm)을 10:1 내지 1 : 1 의 비율로 제어하여 실시한다. The patterning process is performed using chlorine ("cl" -containing Cl2) / Fluorine ("C" -containing CxHyFz series) as the stock angle gas and Ar, O2 as the auxiliary etching gas, and the patterning process is highly selected. In order to have a ratio, the proyang (sccm) of Cl2: CHF3 is controlled by controlling the ratio of 10: 1 to 1: 1.

상기 제1 내지 제3 절연막은 산화막으로 형성하며, 상기 제1 절연막 형성 후, 상기 제2 절연막 형성 전에 식각 정지 절연막을 형성하는 단계를 더 포함한다. 상기 식각 정지 도전막을 형성한 후, 상기 제3 절연막 형성 전에 식각 정지 절연막을 형성하는 단계를 더 포함한다. 상기 식각 정지 절연막은 질화막으로 형성한다.The first to third insulating films may be formed of an oxide film, and after the first insulating film is formed, an etch stop insulating film may be formed before the second insulating film is formed. After forming the etch stop conductive film, and further comprising forming an etch stop insulating film before forming the third insulating film. The etch stop insulating film is formed of a nitride film.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

도 2 내지 도 6은 본 발명의 일실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다. 도 22 내지 도 6에서는 일례로서 플래시 메모리 소자의 제조 공정이 도시되어 있다. 도 2a 내지 도 2g에 도시된 참조부호들 중 서로 동일한 참조부호는 서로 동일한 기능을 하는 동일 구성요소를 가리킨다.2 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 22 to 6 illustrate a manufacturing process of a flash memory device as an example. The same reference numerals among the reference numerals shown in FIGS. 2A to 2G indicate the same components having the same function.

도 2를 참고하면, 복수의 단위 소자들(미도시)이 형성된 반도체 기판(100)이 제공된다. 이후, 반도체 기판(100)을 포함하는 전체 구조 상부에 제1 절연막(101)을 형성하고, 제1 절연막(101) 상에 제1 식각 정지 절연막(102)을 형성한다. 이 후, 금속 확산 방지막(102)을 포함한 전체 구조 상에 제2 층간 절연막(103)을 형성 한다. 제1 절연막(101) 및 제2 절연막(103)은 산화막으로 형성하는 것이 바람직하다. 제1 식각 정지 절연막(102)은 질화막으로 형성하는 것이 바람직하다.Referring to FIG. 2, a semiconductor substrate 100 in which a plurality of unit devices (not shown) is formed is provided. Thereafter, the first insulating film 101 is formed on the entire structure including the semiconductor substrate 100, and the first etch stop insulating film 102 is formed on the first insulating film 101. Thereafter, the second interlayer insulating film 103 is formed over the entire structure including the metal diffusion barrier film 102. The first insulating film 101 and the second insulating film 103 are preferably formed of an oxide film. The first etch stop insulating film 102 is preferably formed of a nitride film.

도 3을 참조하면, 식각 공정을 실시하여 제1 식각 정지 절연막(102)의 일부 영역이 노출되는 트렌치를 형성한 후, 노출되는 제1 식각 정지 절연막(102)을 식각하여 콘택홀을 형성한다. 이 후, 전체 구조 상에 금속 물질을 증착한 후, CMP 공정을 실시하여 금속 물질을 콘택홀에 잔류시켜 하부 금속층(104)을 형성한다. 하부 금속층(104)은 알루미늄으로 형성하는 것이 바람직하다.Referring to FIG. 3, an etching process is performed to form a trench in which a portion of the first etch stop insulating layer 102 is exposed, and then the exposed first etch stop insulating layer 102 is etched to form a contact hole. Thereafter, after depositing a metal material on the entire structure, a CMP process is performed to leave the metal material in the contact hole to form the lower metal layer 104. The lower metal layer 104 is preferably formed of aluminum.

도 4를 참조하면, 하부 금속층(104)을 포함하는 전체 구조 상에 도전층을 증착한 후, 패터닝 공정을 실시하여 하부 금속층(104)에 잔류시킨다. 즉, 도전층을 하부 금속층(104) 상부에 잔류시켜 식각 정지 도전층(105)을 형성한다. 식각 정지 도전층(105)은 TiN막으로 형성하는 것이 바람직하다. 패터닝 공정은 주식각 가스로 Chlorine("cl" 함유한 Cl2)/Fluorine("F" 함유한 CxHyFz계열 )로 사용하고 보조 식각 가스로 Ar,O2를 사용하여 실시하는 것이 바람직하다. 패터닝 공정은 고선택비를 가지기 위하여 Cl2 : CHF3 의 프로우양(sccm)을 10:1 내지 1 : 1 의 비율로 제어하는 것이 바람직하다. 이때, CHF3 대신에 CF4,C2F6 등의 CxHyFz 가스 사용시 동일 "F" 비율 유지하는 것이 바람직하다.Referring to FIG. 4, after depositing a conductive layer on the entire structure including the lower metal layer 104, a patterning process is performed to remain in the lower metal layer 104. That is, the etch stop conductive layer 105 is formed by leaving the conductive layer on the lower metal layer 104. The etch stop conductive layer 105 is preferably formed of a TiN film. The patterning process is preferably carried out using Chlorine ("cl" containing Cl2) / Fluorine ("C" containing CxHyFz) as the stock angle gas and Ar, O2 as the auxiliary etching gas. In the patterning process, in order to have a high selectivity, it is preferable to control the pro amount (sccm) of Cl2: CHF3 at a ratio of 10: 1 to 1: 1. At this time, it is preferable to maintain the same "F" ratio when using CxHyFz gas such as CF4, C2F6 instead of CHF3.

도 5를 참조하면, 식각 정지 도전층(105)을 포함한 전체 구조 상에 제2 식각 정지 절연막(106) 및 제3 절연막(107)을 순차적으로 적층하여 형성한다. 제2 식각 정지 절연막(106)은 질화막으로 형성하는 것이 바람직하다. 제3 절연막(107)은 산화막으로 형성하는 것이 바람직하다.Referring to FIG. 5, the second etch stop insulating layer 106 and the third insulating layer 107 are sequentially stacked on the entire structure including the etch stop conductive layer 105. The second etch stop insulating film 106 is preferably formed of a nitride film. The third insulating film 107 is preferably formed of an oxide film.

도 6을 참조하면, 식각 공정을 실시하여 식각 정지 도전층(105) 상부에 형성된 제2 식각 정지 절연막(106)이 노출되도록 제3 절연막(107)을 식각한다. 이 후, 노출된 제2 식각 정지 절연막(106)을 식각하여 비아홀(108)을 형성한다. 이때 식각 공정시 과도 식각되어도 식각 정지 도전층(105)에 의해 하부 금속층(104)이 손상되는 것을 방지할 수 있다.Referring to FIG. 6, the third insulating layer 107 is etched to expose the second etch stop insulating layer 106 formed on the etch stop conductive layer 105 by performing an etching process. Thereafter, the exposed second etch stop insulating layer 106 is etched to form a via hole 108. At this time, even if excessive etching is performed during the etching process, the lower metal layer 104 may be prevented from being damaged by the etch stop conductive layer 105.

이 후 도시되진 않았지만, 비아홀을 포함한 전체 구조 상에 금속 물질을 증착한 후, CMP 공정을 실시하여 금속 물질을 비아홀에 잔류시켜 플러그를 형성한 후, 상부 금속층을 형성한다.Thereafter, although not shown, the metal material is deposited on the entire structure including the via hole, and then a CMP process is performed to leave the metal material in the via hole to form a plug, and then form an upper metal layer.

상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예들에서 구체적으로 기술되었으나, 상기한 실시예들은 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

이상에서 설명한 바와 같이, 본 발명에 의하면 하부 금속층 상부에 비아홀 정지 도전층이 형성됨으로써, 절연막에 하부 금속층과 상부 금속층간의 플러그용 비아홀 형성시 하부 금속층의 식각을 방지하여, 상부 금속층과 하부 금속층간의 접촉 저항 값의 변화가 최소화될 수 있고, 반도체 소자의 양산시 양품률 특성이 향상 될 수 있다.As described above, according to the present invention, the via hole stop conductive layer is formed on the lower metal layer, thereby preventing the etching of the lower metal layer when the via hole for plug between the lower metal layer and the upper metal layer is formed in the insulating layer, thereby preventing the etching between the upper metal layer and the lower metal layer. The change of the contact resistance value of can be minimized, and the yield rate characteristics during the mass production of the semiconductor device can be improved.

Claims (13)

반도체 기판 상에 제1 절연막 및 제2 절연막을 순차적으로 형성하는 단계;Sequentially forming a first insulating film and a second insulating film on the semiconductor substrate; 상기 제2 절연막을 식각하여 상기 제1 절연막의 콘택 영역이 노출되는 콘택홀을 형성하는 단계;Etching the second insulating layer to form a contact hole exposing the contact region of the first insulating layer; 상기 콘택홀 내에 금속 배선을 형성하는 단계;Forming a metal line in the contact hole; 상기 금속 배선 상부에 식각 정지 도전막을 형성하는 단계;Forming an etch stop conductive layer on the metal wiring; 상기 식각 정지 도전막을 포함한 전체 구조 상에 제3 절연막을 형성하는 단계; 및Forming a third insulating film on the entire structure including the etch stop conductive film; And 상기 식각 정지 도전막이 노출되는 비아홀을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.And forming a via hole through which the etch stop conductive layer is exposed. 제 1 항에 있어서,The method of claim 1, 상기 비아홀을 형성한 후, 상기 비아홀을 금속 물질로 채워 플러그를 형성하는 단계를 더 포함하는 반도체 소자의 제조 방법.After forming the via hole, filling the via hole with a metal material to form a plug. 제 1 항에 있어서,The method of claim 1, 상기 식각 정지 도전막을 형성하는 단계는Forming the etch stop conductive layer is 상기 금속 배선을 포함하는 전체 구조 상에 도전막을 형성하는 단계; 및Forming a conductive film on the entire structure including the metal wiring; And 패터닝 공정을 실시하여 상기 금속 배선 상부에 상기 도전막을 잔류시켜 상기 식각 정지 도전막을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.And forming a etch stop conductive layer by remaining the conductive layer on the metal wiring by performing a patterning process. 제 1 항에 있어서,The method of claim 1, 상기 식각 정지 도전막은 TiN막으로 형성하는 반도체 소자의 제조 방법.The etching stop conductive film is a semiconductor device manufacturing method of forming a TiN film. 제 3 항에 있어서,The method of claim 3, wherein 상기 패터닝 공정은 주식각 가스로 Chlorine("cl" 함유한 Cl2)/Fluorine("F" 함유한 CxHyFz계열 )로 사용하고 보조 식각 가스로 Ar,O2를 사용하여 실시하는 반도체 소자의 제조 방법.The patterning process is a semiconductor device manufacturing method using a chlorine ("cl" containing Cl2) / Fluorine ("F" containing CxHyFz series) as a stock angle gas and using Ar, O2 as an auxiliary etching gas. 제 3 항에 있어서,The method of claim 3, wherein 상기 패터닝 공정은 고선택비를 가지기 위하여 Cl2 : CHF3 의 프로우양(sccm)을 10:1 내지 1 : 1 의 비율로 제어하여 실시하는 반도체 소자의 제조 방법.The patterning process is a semiconductor device manufacturing method performed by controlling the proyang (sccm) of Cl2: CHF3 in a ratio of 10: 1 to 1: 1 in order to have a high selectivity. 제 1 항에 있어서,The method of claim 1, 상기 제1 내지 제3 절연막은 산화막으로 형성하는 반도체 소자의 제조 방법.And the first to third insulating films are formed of an oxide film. 제 1 항에 있어서,The method of claim 1, 상기 제1 절연막 형성 후, 상기 제2 절연막 형성 전에 식각 정지 절연막을 형성하는 단계를 더 포함하는 반도체 소자의 제조 방법.And forming an etch stop insulating film after forming the first insulating film and before forming the second insulating film. 제 1 항에 있어서,The method of claim 1, 상기 식각 정지 도전막을 형성한 후, 상기 제3 절연막 형성 전에 식각 정지 절연막을 형성하는 단계를 더 포함하는 반도체 소자의 제조 방법.And forming an etch stop insulating film after forming the etch stop conductive film and before forming the third insulating film. 제 8 항 또는 제 9 항에 있어서,The method according to claim 8 or 9, 상기 식각 정지 절연막은 질화막으로 형성하는 반도체 소자의 제조 방법.The etching stop insulating film is a semiconductor device manufacturing method of forming a nitride film. 반도체 기판 상에 순차적으로 형성된 제1 절연막 및 제2 절연막;A first insulating film and a second insulating film sequentially formed on the semiconductor substrate; 상기 제2 절연막을 관통하여 상기 제1 절연막과 연결되는 금속 배선;A metal wire penetrating the second insulating film and connected to the first insulating film; 상기 금속 배선 상부에 형성된 식각 정지 도전막; 및An etch stop conductive layer formed on the metal wiring; And 상기 식각 정지 도전막 상부의 일부 또는 전체를 포함하는 영역이 노출되도록 형성된 비아홀을 포함하는 반도체 소자.And a via hole formed to expose a region including a portion or the entirety of an upper portion of the etch stop conductive layer. 제 11 항에 있어서,The method of claim 11, wherein 상기 비아홀 내에 형성된 플러그를 더 포함하는 반도체 소자.The semiconductor device further comprises a plug formed in the via hole. 제 11 항에 있어서, 상기 식각 정지 도전막은 TiN막으로 형성된 반도체 소자.The semiconductor device of claim 11, wherein the etch stop conductive layer is formed of a TiN layer.
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Publication number Priority date Publication date Assignee Title
CN115185129A (en) * 2022-06-07 2022-10-14 深圳技术大学 Etching method of dielectric film via hole, liquid crystal display panel and liquid crystal display

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115185129A (en) * 2022-06-07 2022-10-14 深圳技术大学 Etching method of dielectric film via hole, liquid crystal display panel and liquid crystal display
CN115185129B (en) * 2022-06-07 2024-02-09 深圳技术大学 Etching method of dielectric film via hole, liquid crystal display panel and liquid crystal display

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