KR20040002200A - Method for fabricating device isolation film of semiconductor device - Google Patents

Method for fabricating device isolation film of semiconductor device Download PDF

Info

Publication number
KR20040002200A
KR20040002200A KR1020020037646A KR20020037646A KR20040002200A KR 20040002200 A KR20040002200 A KR 20040002200A KR 1020020037646 A KR1020020037646 A KR 1020020037646A KR 20020037646 A KR20020037646 A KR 20020037646A KR 20040002200 A KR20040002200 A KR 20040002200A
Authority
KR
South Korea
Prior art keywords
oxide film
trench
pad
pad nitride
layer
Prior art date
Application number
KR1020020037646A
Other languages
Korean (ko)
Other versions
KR100461328B1 (en
Inventor
김우진
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR10-2002-0037646A priority Critical patent/KR100461328B1/en
Publication of KR20040002200A publication Critical patent/KR20040002200A/en
Application granted granted Critical
Publication of KR100461328B1 publication Critical patent/KR100461328B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE: A method for fabricating an isolation layer of a semiconductor device is provided to prevent a void in a process for forming a filling oxide layer by forming an oxide layer in a trench such that the oxide layer has a sufficient thickness for filling an undercut under a pad nitride layer. CONSTITUTION: A pad oxide layer(200) and a pad nitride layer are sequentially formed on a semiconductor substrate(100). A predetermined region of the pad nitride layer and the pad oxide layer is etched to expose the substrate in a region for the isolation layer(900). The exposed substrate is oxidized to form a sacrificial oxide layer of a bird's beak. The sacrificial oxide layer is eliminated. The exposed substrate is etched to form a trench by using the pad nitride layer as a mask. An oxide layer(700) is formed on the bottom and the sidewall of the trench so that the oxide layer formed on the sidewall of the trench is twice as thick as the pad oxide layer. The filling oxide layer for filling the trench is formed on the substrate. A planarization process is performed to expose the pad nitride layer. The pad nitride layer is eliminated.

Description

반도체 소자의 소자 분리막 제조 방법{METHOD FOR FABRICATING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE}METHODS FOR FABRICATING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 소자 분리막 제조 방법에 관한 것으로, 특히 트렌치 형성 전에 산화 공정을 수행함으로써, 패드 질화막 하부의 언더컷을 방지하고 트렌치 상부 코너를 라운딩하여 소자 특성의 열화를 방지하는 반도체 소자의 소자 분리막 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a device isolation film of a semiconductor device, and in particular, by performing an oxidation process prior to trench formation, to prevent undercut of the bottom of the pad nitride film and to round the top corner of the trench to prevent deterioration of device characteristics. It relates to a manufacturing method.

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 소자 분리막 형성 방법을 도시한 단면도들이다. 도 1a 내지 도 1e를 참조하면, 반도체 기판(10) 상부에 패드 산화막(20) 및 패드 질화막(30)을 순차적으로 형성한 후 패드 질화막(30), 패드 산화막(20) 및 반도체 기판(10)의 소정 영역을 식각하여 트렌치(40)를형성한다(도 1a 참조).1A to 1D are cross-sectional views illustrating a method of forming a device isolation layer of a semiconductor device according to the prior art. 1A to 1E, after the pad oxide film 20 and the pad nitride film 30 are sequentially formed on the semiconductor substrate 10, the pad nitride film 30, the pad oxide film 20, and the semiconductor substrate 10 are sequentially formed. The trench 40 is formed by etching a predetermined region of the trench (see FIG. 1A).

다음에는, 트렌치(50)의 바닥 및 측벽에 희생 산화막(미도시)을 형성하고 세정 공정으로 희생 산화막을 제거한 후 산화 공정으로 트렌치(50)의 바닥 및 측벽에산화막(50)을 형성한다(도 1b 참조). 상기 두 번의 산화 공정에 의하여 패드 질화막(30)의 하부에는 언더컷(60)이 형성된다. 언더컷(60)을 매립하기 위하여 추가적인 질화막(70)을 구조물의 전면에 소정 두께 형성한다(도 1c 참조).Next, a sacrificial oxide film (not shown) is formed on the bottom and sidewalls of the trench 50, the sacrificial oxide film is removed by a cleaning process, and an oxide film 50 is formed on the bottom and sidewalls of the trench 50 by an oxidation process (FIG. 1b). Undercuts 60 are formed under the pad nitride layer 30 by the two oxidation processes. In order to fill the undercut 60, an additional nitride film 70 is formed on the front surface of the structure by a predetermined thickness (see FIG. 1C).

트렌치(40)를 매립하는 충진 산화막(80)을 반도체 기판(10)의 전면에 형성하고(도 1d 참조), 평탄화 공정 및 패드 질화막(30) 제거 공정을 수행하여 소자 분리막(미도시)을 형성한다.A filling oxide film 80 filling the trench 40 is formed on the entire surface of the semiconductor substrate 10 (see FIG. 1D), and a device isolation film (not shown) is formed by performing a planarization process and a removal process of the pad nitride film 30. do.

상기 종래의 소자 분리막 형성 공정에서는 전계 감소를 위한 트렌치 상부 코너의 라운딩을 위하여 트렌치 형성 후에 측벽 희생 산화막 및 측벽 산화막 형성 공정을 이용하였다. 그러나 이러한 두 번의 산화 공정으로 인하여 활성 영역의 면적이 감소하는 문제점이 있었으며, 패드 질화막 하부의 언더컷으로 인하여 충진 산화막 형성 단계에서 보이드(void)가 발생하는 문제점이 있었다. 이러한 보이드의 발생을 방지하기 위하여 측벽 산화막 형성 공정 수행 후에 질화막 또는 산화막을 추가적으로 형성하는 공정을 이용하였으나, 추가적인 공정으로 인하여 공정이 복잡해지고 비용이 상승한다는 문제점이 있었다.In the conventional device isolation layer forming process, a sidewall sacrificial oxide film and a sidewall oxide film forming process are used after the trench formation to round the upper corners of the trench for electric field reduction. However, due to these two oxidation processes, there is a problem in that the area of the active region is reduced, and there is a problem in that voids are generated in the filling oxide film forming step due to the undercut under the pad nitride film. In order to prevent the generation of such voids, a process of additionally forming a nitride film or an oxide film after performing the sidewall oxide film forming process is used, but there is a problem that the process is complicated and the cost increases.

본 발명은 이러한 문제를 해결하기 위해 트렌치 형성 공정 후에 발생하는 패드 질화막 하부의 언더컷을 매립하는 충분한 두께의 산화막을 트렌치 내부에 형성함으로써, 충진 산화막 형성 단계에서 발생하는 보이드(void)를 방지하고, 산화 공정을 한번만 수행함으로써, 활성 영역의 감소를 억제하며, 공정을 간단히 하여 생산 비용을 줄일 수 있는 동시에 트렌치 상부 코너의 라운딩을 달성하는 반도체 소자의 소자 분리막 제조 방법을 제공하는데 그 목적이 있다.In order to solve this problem, the present invention forms an oxide film having a sufficient thickness to fill an undercut under the pad nitride film generated after the trench forming process in the trench, thereby preventing voids generated during the filling oxide film forming step, and oxidizing. It is an object of the present invention to provide a method for fabricating a device isolation layer of a semiconductor device in which the process is performed only once to suppress the reduction of the active area, simplify the process, reduce the production cost, and at the same time achieve rounding of the upper corner of the trench.

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 소자 분리막 형성 방법을 도시한 단면도들.1A to 1D are cross-sectional views illustrating a method of forming a device isolation layer of a semiconductor device according to the prior art.

도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 소자 분리막 제조 방법을 도시한 단면도들.2A to 2H are cross-sectional views illustrating a method of manufacturing a device isolation film of a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은 반도체 기판 상부에 패드 산화막 및 패드 질화막을 순차적으로 형성하는 단계와, 상기 패드 질화막 및 패드 산화막의 소정 영역을 식각하여 소자 분리막이 형성될 영역의 반도체 기판을 노출시키는 단계와, 노출된 반도체 기판을 산화시켜 새부리 형태의 희생 산화막을 형성하는 단계와, 상기 희생 산화막을 제거하는 단계와, 상기 패드 질화막을 마스크로 노출된 반도체 기판을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치의 측벽에 형성되는 산화막이 상기 패드 산화막 두께의 2배 이상이 되도록 상기 트렌치의 바닥 및 측벽에 산화막을 형성하는 단계와, 상기 트렌치를 매립하는 충진 산화막을 상기 반도체 기판의 전면에 형성하는 단계와, 상기 패드 질화막이 노출되도록 평탄화 공정을 수행하는 단계 및 상기 패드 질화막을 제거하는 단계를 포함하는 것을 특징으로 한다.A method of forming a device isolation layer of a semiconductor device according to the present invention includes sequentially forming a pad oxide film and a pad nitride film on an upper portion of a semiconductor substrate, and etching a predetermined region of the pad nitride film and the pad oxide film to form a device substrate. Exposing the sacrificial oxide film to form a sacrificial oxide film by oxidizing the exposed semiconductor substrate, removing the sacrificial oxide film, and etching the semiconductor substrate exposed by the pad nitride film as a mask to form a trench. Forming an oxide film on the bottom and sidewalls of the trench such that the oxide film formed on the sidewalls of the trench is at least twice the thickness of the pad oxide film, and filling the trench with a fill oxide film on the entire surface of the semiconductor substrate. And forming a planarization process to expose the pad nitride layer. Step and is characterized in that it comprises a step of removing the pad nitride film.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 소자 분리막 제조 방법을 도시한 단면도들이다. 도 2a 내지 도 2h를 참조하면, 반도체 기판(100) 상부에 패드 산화막(200) 및 패드 질화막(300)을 순차적으로 형성한 후(도 2a 참조) 패드 질화막(300) 및 패드 산화막(200)의 소정 영역을 식각하여 소자 분리막이 형성될 영역의 반도체 기판을 노출시킨다(도 2b 참조).2A to 2H are cross-sectional views illustrating a method of manufacturing a device isolation layer of a semiconductor device according to the present invention. 2A to 2H, after the pad oxide film 200 and the pad nitride film 300 are sequentially formed on the semiconductor substrate 100 (see FIG. 2A), the pad nitride film 300 and the pad oxide film 200 may be formed. The predetermined region is etched to expose the semiconductor substrate in the region where the device isolation layer is to be formed (see FIG. 2B).

다음에는 반도체 기판의 노출된 영역을 산화시켜 새부리(bird's beak) 형태의 희생 산화막(400)을 형성한다(도 2c 참조). 여기서 희생 산화막(400)은 1000℃ 이상의 온도에서 고온 건식 산화 공정을 수행하여 형성하는 것이 바람직하다. 고온 건식 산화 공정에 의하여 LOCOS 공정에서와 같은 새부리 형태의 산화막이 형성된다.Next, the exposed region of the semiconductor substrate is oxidized to form a sacrificial oxide film 400 in the form of a bird's beak (see FIG. 2C). Here, the sacrificial oxide film 400 is preferably formed by performing a high temperature dry oxidation process at a temperature of 1000 ° C. or higher. The high temperature dry oxidation process forms an oxide film in the form of a beak as in the LOCOS process.

그 다음에, 희생 산화막(400)을 제거하고 패드 질화막(300)을 마스크로 노출된 반도체 기판(100)을 식각하여 트렌치(500)를 형성한다(도 2d 참조). 여기서, 희생 산화막(400)을 제거하는 공정은 습식 제정 공정인 것이 바람직하며, 상기 공정에 의하여 패드 질화막(300)의 하부에 언더컷(600)이 형성된다.Next, the trench 500 is formed by removing the sacrificial oxide film 400 and etching the semiconductor substrate 100 with the pad nitride film 300 exposed as a mask (see FIG. 2D). Here, the process of removing the sacrificial oxide film 400 is preferably a wet-setting process, and the undercut 600 is formed under the pad nitride film 300 by the above process.

다음에는, 트렌치(500)의 바닥 및 측벽에 산화막(700)을 형성한다. 산화막(700)은 패드 산화막(200) 두께의 2배 이상이 되도록 형성하여 언더컷(600)을 충분히 매립하도록 한다. 산화막(700)이 충분히 두껍지 않은 경우에는, 언더컷(600)이 전부 매립되지 않으므로 후속 공정에서 보이드(void) 및 모트(moat)로 작용하여 소자의 특성이 열화되므로 주의하여야 한다. 또한 산화막(700)을 형성하는 산화 공정은 1000℃ 이상의 온도에서 수행되는 고온 건식 산화 공정인 것이 바람직하다.Next, an oxide film 700 is formed on the bottom and sidewalls of the trench 500. The oxide film 700 is formed to be at least twice the thickness of the pad oxide film 200 to sufficiently fill the undercut 600. When the oxide film 700 is not thick enough, the undercut 600 is not entirely embedded, and thus, the undercut 600 acts as a void and a moat to deteriorate the characteristics of the device. In addition, the oxidation process for forming the oxide film 700 is preferably a high temperature dry oxidation process performed at a temperature of 1000 ℃ or more.

다음에는, 트렌치(500)를 매립하는 충진 산화막(800)을 반도체 기판(100)의전면에 형성하고(도 2f 참조), 패드 질화막(300)이 노출될 때까지 평탄화 공정, 예를 들면 CMP 공정을 수행한다(도 2g 참조). 그 다음에, 패드 질화막(300)을 제거하여 소자 분리막(900)을 형성한다(도 2h 참조).Next, a filling oxide film 800 filling the trench 500 is formed on the front surface of the semiconductor substrate 100 (see FIG. 2F), and a planarization process, for example, a CMP process, until the pad nitride film 300 is exposed. (See FIG. 2G). Next, the pad nitride film 300 is removed to form the device isolation film 900 (see FIG. 2H).

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 소자 분리막 제조 방법은 트렌치 형성 공정 후에 발생하는 패드 질화막 하부의 언더컷을 매립하는 충분한 두께의 산화막을 트렌치 내부에 형성함으로써, 충진 산화막 형성 단계에서 발생하는 보이드(void)를 방지하고, 산화 공정을 한번만 수행함으로써, 활성 영역의 감소를 억제하며, 공정을 간단히 하여 생산 비용을 줄일 수 있는 동시에 트렌치 상부 코너의 라운딩을 달성하는 효과가 있다.As described above, the device isolation film manufacturing method of the semiconductor device according to the present invention forms an oxide film having a sufficient thickness to fill an undercut under the pad nitride film generated after the trench forming process in the trench, thereby forming the filling oxide film forming step. By preventing voids and performing the oxidation process only once, it is possible to suppress the reduction of the active area, simplify the process and reduce the production cost and at the same time achieve the rounding of the trench upper corner.

Claims (4)

반도체 기판 상부에 패드 산화막 및 패드 질화막을 순차적으로 형성하는 단계;Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; 상기 패드 질화막 및 패드 산화막의 소정 영역을 식각하여 소자 분리막이 형성될 영역의 반도체 기판을 노출시키는 단계;Etching a predetermined region of the pad nitride layer and the pad oxide layer to expose a semiconductor substrate in a region where the device isolation layer is to be formed; 노출된 반도체 기판을 산화시켜 새부리 형태의 희생 산화막을 형성하는 단계;Oxidizing the exposed semiconductor substrate to form a sacrificial oxide film in the form of a beak; 상기 희생 산화막을 제거하는 단계;Removing the sacrificial oxide film; 상기 패드 질화막을 마스크로 노출된 반도체 기판을 식각하여 트렌치를 형성하는 단계;Etching the semiconductor substrate exposing the pad nitride layer as a mask to form a trench; 상기 트렌치의 측벽에 형성되는 산화막이 상기 패드 산화막 두께의 2배 이상이 되도록 상기 트렌치의 바닥 및 측벽에 산화막을 형성하는 단계;Forming an oxide film on the bottom and sidewalls of the trench such that an oxide film formed on the sidewalls of the trench is at least twice the thickness of the pad oxide film; 상기 트렌치를 매립하는 충진 산화막을 상기 반도체 기판의 전면에 형성하는 단계;Forming a filling oxide film filling the trench on the entire surface of the semiconductor substrate; 상기 패드 질화막이 노출되도록 평탄화 공정을 수행하는 단계; 및Performing a planarization process to expose the pad nitride layer; And 상기 패드 질화막을 제거하는 단계Removing the pad nitride film 를 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.Device isolation film manufacturing method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 희생 산화막을 형성하는 단계는 1000℃ 이상의 온도에서 수행되는 고온 건식 산화 공정인 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.The forming of the sacrificial oxide film is a device isolation film manufacturing method of a semiconductor device, characterized in that the high temperature dry oxidation process is performed at a temperature of 1000 ℃ or more. 제 1 항에 있어서,The method of claim 1, 상기 희생 산화막을 제거하는 단계는 습식 제정 공정인 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.The removing of the sacrificial oxide film is a method of manufacturing a device isolation film of a semiconductor device, characterized in that the wet manufacturing process. 제 1 항에 있어서,The method of claim 1, 상기 트렌치의 바닥 및 측벽에 산화막을 형성하는 단계는 1000℃ 이상의 온도에서 수행되는 고온 건식 산화 공정인 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.Forming an oxide film on the bottom and sidewalls of the trench is a high temperature dry oxidation process performed at a temperature of 1000 ℃ or more.
KR10-2002-0037646A 2002-06-29 2002-06-29 Method for fabricating device isolation film of semiconductor device KR100461328B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-2002-0037646A KR100461328B1 (en) 2002-06-29 2002-06-29 Method for fabricating device isolation film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2002-0037646A KR100461328B1 (en) 2002-06-29 2002-06-29 Method for fabricating device isolation film of semiconductor device

Publications (2)

Publication Number Publication Date
KR20040002200A true KR20040002200A (en) 2004-01-07
KR100461328B1 KR100461328B1 (en) 2004-12-14

Family

ID=37313906

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0037646A KR100461328B1 (en) 2002-06-29 2002-06-29 Method for fabricating device isolation film of semiconductor device

Country Status (1)

Country Link
KR (1) KR100461328B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100731074B1 (en) * 2005-12-29 2007-06-22 동부일렉트로닉스 주식회사 Method of fabricating a semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0773582A3 (en) * 1995-11-13 1999-07-14 Texas Instruments Incorporated Method of forming a trench isolation structure in an integrated circuit
KR970053405A (en) * 1995-12-22 1997-07-31 김주용 Method for manufacturing inter-element separator of semiconductor device
US5910018A (en) * 1997-02-24 1999-06-08 Winbond Electronics Corporation Trench edge rounding method and structure for trench isolation
JPH11135610A (en) * 1997-10-29 1999-05-21 Seiko Epson Corp Manufacture of semiconductor device
KR20020017763A (en) * 2000-08-31 2002-03-07 박종섭 Method for forming the Isolation Layer of Semiconductor Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100731074B1 (en) * 2005-12-29 2007-06-22 동부일렉트로닉스 주식회사 Method of fabricating a semiconductor device

Also Published As

Publication number Publication date
KR100461328B1 (en) 2004-12-14

Similar Documents

Publication Publication Date Title
KR100461328B1 (en) Method for fabricating device isolation film of semiconductor device
KR20010046153A (en) Method of manufacturing trench type isolation layer in semiconductor device
KR100596876B1 (en) Method for forming device isolation film of semiconductor device
KR20050028618A (en) Method for forming isolation layer of semiconductor device
KR100455093B1 (en) Method of forming an isolation layer in a semiconductor device
KR100429555B1 (en) Method for forming trench type isolation layer in semiconductor device
KR100539001B1 (en) Method for fabricating shallow trench isolation of semiconductor device
KR100967672B1 (en) The method for forming shall trench isolation in semiconductor device
KR100439105B1 (en) Method for fabricating isolation layer of semiconductor device to improve cut-off characteristic at both corners of trench and inwe between narrow lines
KR100921329B1 (en) Method of forming an isolation layer in a semiconductor device
KR20040003650A (en) Method for forming the Isolation Layer of Semiconductor Device
KR100800104B1 (en) Field region of semiconductor device and the method of thereof
KR20030052663A (en) method for isolating semiconductor device
KR960013501B1 (en) Field oxide film forming method of semiconductor device
KR20040004873A (en) Method for forming trench type isolation layer in semiconductor device
KR20050002061A (en) Fabricating method of trench isolation layer in semiconductor device
KR19990057376A (en) Device Separating Method of Semiconductor Device
KR20070060341A (en) Method for forming isolation layer of semiconductor device
KR20030055792A (en) Method for forming isolation layer of semiconductor device
KR20050068064A (en) Fabrication method of semiconductor device having a trench isolation layer
KR20050012652A (en) Method for forming element isolation layer of semiconductor device
JP2002043414A (en) Semiconductor device and its manufacturing method
KR20060000484A (en) Method for forming isolation layer of semiconductor device
KR20040001228A (en) Method for manufacturing isolation layer in semiconductor device
KR20040004866A (en) Method for forming trench type isolation layer in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101125

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee