KR100731074B1 - Method of fabricating a semiconductor device - Google Patents

Method of fabricating a semiconductor device Download PDF

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KR100731074B1
KR100731074B1 KR1020050133323A KR20050133323A KR100731074B1 KR 100731074 B1 KR100731074 B1 KR 100731074B1 KR 1020050133323 A KR1020050133323 A KR 1020050133323A KR 20050133323 A KR20050133323 A KR 20050133323A KR 100731074 B1 KR100731074 B1 KR 100731074B1
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South Korea
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oxide film
semiconductor device
trench
manufacturing
nitride film
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KR1020050133323A
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Korean (ko)
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이주현
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

Abstract

A method for manufacturing a semiconductor device is provided to prevent the generation of divot and to prevent the generation of leakage current due to the divot by removing a hard mask made of oxide in a trench forming process using a diluted HF. A nitride layer and an oxide layer are sequentially formed on a substrate(200). A trench is formed on the resultant structure by using the oxide layer as a hard mask. A pullback process is performed on the resultant structure, so that an undercut portion is formed at the nitride layer adjacent to the trench. The oxide layer is removed from the resultant structure by performing an etching process using a diluted HF. A CVD oxide layer(240) is formed on the resultant structure and planarized.

Description

반도체 소자의 제조 방법 {Method of Fabricating a Semiconductor Device}Method of manufacturing a semiconductor device {Method of Fabricating a Semiconductor Device}

도 1a 내지 도 1e는 종래기술에 의한 반도체 소자의 제조 방법을 나타낸 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2f는 본 발명의 일 실시예에 의한 반도체 소자의 제조 방법을 나타낸 단면도이다.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a는 종래기술에 의해 디벗이 발생한 기판의 사진도이며, 도 3b는 본 발명의 일 실시예에 의한 디벗의 발생이 억제된 기판의 사진도이다.3A is a photographic view of a substrate in which a divert is generated by a prior art, and FIG. 3B is a photographic view of a substrate in which generation of a divert is suppressed according to an embodiment of the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 좀 더 상세하게는 STI(Shallow Trench Isolation) 공정을 이용하는 반도체 소자의 제조 방법에서 디벗(divot)의 발생을 방지하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for preventing the generation of a divot in a method of manufacturing a semiconductor device using a shallow trench isolation (STI) process.

이하, 도 1a 내지 도 1e를 참조하여, 종래기술에 의한 반도체 소자의 제조 방법을 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to FIGS. 1A to 1E.

도 1a는 기판(100) 상에 질화막(nitride, 110), 산화막(oxide, 120)을 순서대로 도포한 후, STI 공정에 의해 산화막(120)을 하드 마스크(hard mask)로 하여 트렌치(trench, 130)를 형성한 상태를 나타낸다. 도 1a에는 도시되어 있지 않으나, 기판(100)과 질화막(110) 사이에 100 옹스트롬(Å) 이하의 얇은 두께로 산화막이 도포되어 있다. 이는 기판(100)과 질화막(110)의 접착력을 증가시켜 주는 역할을 한다. 그리고 도 1b는 풀백(pullback) 공정에 의해 트렌치(130) 부근에 있는 산화막(120) 아래의 질화막(110)을 언더컷(undercut)한 상태를 나타낸다.FIG. 1A illustrates that a nitride film 110 and an oxide 120 are sequentially coated on a substrate 100, and then trenches are formed using the oxide film 120 as a hard mask by an STI process. 130) is shown. Although not shown in FIG. 1A, an oxide film is coated between the substrate 100 and the nitride film 110 to a thin thickness of 100 angstroms or less. This serves to increase the adhesion between the substrate 100 and the nitride film 110. 1B illustrates a state in which the nitride film 110 under the oxide film 120 in the vicinity of the trench 130 is undercut by a pullback process.

그 다음, 도 1c에서 처럼 화학 기상 증착(Chemical Vapor Deposition; CVD) 방식에 의해 CVD 산화물(CVD oxide, 140)을 증착하여 트렌치(130)를 채운다. 이때, 질화막(110)만을 국부적으로 언더컷하였기 때문에 산화막(120)에 의해 CVD 산화물(140)이 갭 필(gap fill)되지 않는 공간(145)이 생긴다.Next, as shown in FIG. 1C, the CVD oxide 140 is deposited by chemical vapor deposition (CVD) to fill the trench 130. At this time, since only the nitride film 110 is locally undercut, a space 145 is formed in which the CVD oxide 140 is not gap filled by the oxide film 120.

그리고, 도 1d와 같이 트렌치(30)가 형성된 활성 영역(active area)을 평탄화(chemical mechanical planarization; CMP) 공정에 의해 평탄화한다. 그 다음, 도 1e에서 처럼 비활성 영역의 질화막(110)을 제거하는데, 여전히 활성 영역에 산화물(140)이 갭 필되지 않은 디벗(150)을 발생하게 된다. 이는 후속 공정에서 누설 전류(leakage current)를 발생하여 반도체 소자의 오동작을 유발하는 문제점이 있다.1D, the active area in which the trench 30 is formed is planarized by a chemical mechanical planarization (CMP) process. Next, as shown in FIG. 1E, the nitride film 110 in the inactive region is removed, and the divot 150 in which the oxide 140 is not gap-filled is still generated in the active region. This is a problem that causes a leakage current (leakage current) in the subsequent process causing a malfunction of the semiconductor device.

본 발명은 STI 공정을 포함하는 반도체 소자의 제조 방법에서 디벗의 발생을 방지함에 의해, 누설 전류의 발생을 억제하고, 반도체 소자의 오동작을 방지하는 것을 목적으로 한다.An object of the present invention is to prevent the occurrence of leakage current and to prevent malfunction of a semiconductor device by preventing the generation of a divot in the method of manufacturing a semiconductor device including an STI process.

이러한 기술적 과제를 해결하기 위하여, 본 발명은 기판 상에 질화막과 산화막을 순서대로 도포하고, 상기 산화막을 하드 마스크로 하여 트렌치를 형성하는 STI 공정과; 상기 트렌치 부근에 존재하는 상기 질화막의 일부를 언더컷하는 풀백 공정과; 상기 산화막을 전체적으로 식각하여 제거하는 공정과; 화학 기상 증착 방식에 의해 상기 트렌치에 CVD 산화막을 증착하는 공정과; 상기 CVD 산화막을 평탄화하는 공정과; 상기 질화막을 제거하는 공정을 포함하는, 반도체 소자의 제조 방법을 제공한다. 여기서, 상기 풀백 공정은 H3PO4를 이용하여 식각하는 것이 바람직하다. 또한, 상기 산화막은 DHF(Diluted Hydrogen Fluoride)를 이용하여 식각하는 것이 바람직하다.In order to solve the above technical problem, the present invention is the STI process of applying a nitride film and an oxide film in order on the substrate, and forming a trench using the oxide film as a hard mask; A pullback step of undercutting a portion of the nitride film present near the trench; Etching away the oxide film as a whole; Depositing a CVD oxide film in said trench by chemical vapor deposition; Planarizing the CVD oxide film; It provides a method for manufacturing a semiconductor device, including the step of removing the nitride film. Here, the pullback process is preferably etched using H 3 PO 4 . In addition, the oxide film is preferably etched using Diluted Hydrogen Fluoride (DHF).

이하, 도 2a 내지 도 2f를 참조하여, 본 발명의 일 실시예에 의한 반도체 소자의 제조 방법을 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2F.

도 2a는 기판(200) 상에 질화막(210), 산화막(220)을 순서대로 도포한 후, STI 공정에서 하드 마스크로 사용하는 산화막(220)과 그 하부의 질화막(210)을 제거하여 트렌치(230)를 형성한 상태를 나타낸다. 도 2a에는 도시되어 있지 않으나, 기판(200)과 질화막(210) 사이에 100 옹스트롬(Å) 이하의 얇은 두께로 산화막이 도포되어 있다. 이는 기판(200)과 질화막(210)의 접착력을 증가시켜 주는 역할을 한다.FIG. 2A illustrates that the nitride film 210 and the oxide film 220 are sequentially coated on the substrate 200, and then the oxide film 220 and the lower nitride film 210 used as hard masks are removed in the STI process. 230) is shown. Although not shown in FIG. 2A, an oxide film is applied between the substrate 200 and the nitride film 210 to a thin thickness of 100 angstroms or less. This serves to increase the adhesion between the substrate 200 and the nitride film 210.

그리고 도 2b는 풀백 공정에 의해 트렌치(230) 상측 가장자리 부근의 산화막(220) 아래에 있는 질화막(210)을 국부적으로 언더컷한 상태를 나타낸다. 이러한 풀백 공정은 후속하는 CVD 산화막의 필링(filling) 마진을 확보하여, 필링을 용이하게 하기 위함이다. 아울러, 필링 과정 후에 STI 구조상 다양하게 발생 가능한 STI 스트레스(STI stress)를 완화시켜 주는 효과가 있다. 이러한 풀백 공정은 H3PO4를 이용하여 식각한다.2B illustrates a state in which the nitride film 210 under the oxide film 220 near the upper edge of the trench 230 is locally undercut by the pullback process. This pullback process is to ensure the filling margin of the subsequent CVD oxide film, to facilitate the filling. In addition, there is an effect of reducing the STI stress (STI stress) that can be variously generated in the STI structure after the peeling process. This pullback process is etched using H 3 PO 4 .

도 2c에서는 종래기술과 달리 트렌치(230) 형성시에 하드 마스크로 사용한 산화막(220)을 전체적으로 제거한다. 이때 DHF를 이용한 식각을 한다. 이러한 DHF를 이용한 식각 공정에서는 HF의 농도 조절에 의해서 식각률(etching rate) 등을 제어한다. 여기서는 DHF의 농도를 물과 HF가 100 대 1의 비율로 하여, 분당 식각률이 20 내지 30 옹스트롬(Å)이 되도록 한다.In FIG. 2C, unlike the prior art, the oxide film 220 used as a hard mask when the trench 230 is formed is entirely removed. At this time, etching is performed using DHF. In the etching process using the DHF, the etching rate is controlled by adjusting the concentration of HF. Here, the concentration of DHF is set at a ratio of water to HF of 100 to 1 so that the etching rate per minute is 20 to 30 angstroms.

그 다음, 도 2d에서 처럼 화학 기상 증착 방식에 의해 CVD 산화막(240)을 증착하여 트렌치(230)를 필링한다. 종래기술에서는 산화막 아래에 질화막을 언더컷한 부분에 산화물이 갭 필되지 않는 공간이 생겼으나, 본 발명에서는 산화막(220)을 모두 제거한 상태이므로, CVD 산화막(240)이 갭 필되지 않는 공간은 생기지 않는다.Next, as illustrated in FIG. 2D, the CVD oxide layer 240 is deposited by chemical vapor deposition to fill the trench 230. In the prior art, there is a space where the oxide film is not gap-filled under the oxide film under the oxide film. However, in the present invention, since the oxide film 220 is completely removed, the space where the CVD oxide film 240 is not gap-filled is not created. .

또한, 도 2e와 같이 트렌치(230)가 형성된 활성 영역을 평탄화한다. 이때, 질화막(210)은 평탄화 공정의 정지층(stopper) 역할을 한다. 따라서, 도 1f에서 처럼 질화막(210)을 모두 제거해 내면, 트렌치(230) 내의 CVD 산화막(240)의 표면이 기판(200)의 표면 보다 더 높게 위치하게 된다. 그리고, 종래기술과 달리 CVD 산화막(240)이 모두 갭 필되어 디벗이 발생되지 않는다.In addition, as shown in FIG. 2E, the active region where the trench 230 is formed is planarized. In this case, the nitride film 210 serves as a stopper of the planarization process. Therefore, when all of the nitride film 210 is removed as shown in FIG. 1F, the surface of the CVD oxide film 240 in the trench 230 is positioned higher than the surface of the substrate 200. And, unlike the prior art, the CVD oxide film 240 is all gap-filled and no divert occurs.

즉, 도 3a에서 보는 바와 같이 종래기술에 의한 STI 구조의 사진도에선 디벗이 형성되어 있으며, 도 3b에서는 본 발명에 의한 STI 구조의 사진도로서 디벗의 형성이 방지된 것을 알 수 있다.That is, as shown in FIG. 3A, a divot is formed in the STI structure photogram according to the prior art, and in FIG. 3B, it is understood that the divot is prevented as a photographic view of the STI structure according to the present invention.

이러한 본 발명은 종래기술에서 디벗에 의한 누설 전류의 발생이 반도체 소자의 오동작을 유발하는 문제점을 해결한다.This invention solves the problem that the generation of leakage current by the divert causes the malfunction of the semiconductor device in the prior art.

지금까지 본 발명의 바람직한 실시예에 대해 설명하였으나, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명의 본질적인 특성을 벗어나지 않는 범위 내에서 변형된 형태로 구현할 수 있을 것이다. 그러므로 여기서 설명한 본 발명의 실시예는 한정적인 관점이 아니라 설명적인 관점에서 고려되어야 하고, 본 발명의 범위는 상술한 설명이 아니라 특허청구범위에 나타나 있으며, 그와 동등한 범위 내에 있는 모든 차이점은 본 발명에 포함되는 것으로 해석되어야 한다.Although a preferred embodiment of the present invention has been described so far, those skilled in the art will be able to implement in a modified form without departing from the essential characteristics of the present invention. Therefore, the embodiments of the present invention described herein are to be considered in descriptive sense only and not for purposes of limitation. Should be interpreted as being included in.

본 발명에 따르면, STI 공정을 포함하는 반도체 소자의 제조 방법에서, 트렌치 형성시에 하드 마스크로 사용하는 산화막을 DHF 방식으로 제거하는 구성에 의해 디벗의 발생을 방지하는 효과가 있다. 아울러, 디벗으로 인해 생기는 누설 전류의 발생이 억제되며, 아울러 반도체 소자의 오동작을 방지하는 효과가 있다.According to the present invention, in the method of manufacturing a semiconductor device including the STI process, the generation of the divot can be prevented by the structure in which the oxide film used as the hard mask at the time of trench formation is removed by the DHF method. In addition, the generation of leakage current caused by the dividing is suppressed, and there is an effect of preventing the malfunction of the semiconductor device.

Claims (3)

반도체 소자의 제조 방법으로서,As a manufacturing method of a semiconductor device, 기판 상에 질화막과 산화막을 순서대로 도포하고, 상기 산화막을 하드 마스크로 하여 트렌치를 형성하는 STI 공정과;An STI process of coating a nitride film and an oxide film on the substrate in order and forming a trench using the oxide film as a hard mask; 상기 트렌치 부근에 존재하는 상기 질화막의 일부를 언더컷하는 풀백 공정과;A pullback step of undercutting a portion of the nitride film present near the trench; 상기 산화막을 전체적으로 식각하여 제거하는 공정과;Etching away the oxide film as a whole; 화학 기상 증착 방식에 의해 상기 트렌치에 CVD 산화막을 증착하는 공정과;Depositing a CVD oxide film in said trench by chemical vapor deposition; 상기 CVD 산화막을 평탄화하는 공정과;Planarizing the CVD oxide film; 상기 질화막을 제거하는 공정을 포함하는, 반도체 소자의 제조 방법.The manufacturing method of a semiconductor element including the process of removing the said nitride film. 제 1 항에서,In claim 1, 상기 풀백 공정은 H3PO4를 이용하여 식각하는 것을 특징으로 하는, 반도체 소자의 제조 방법.The pull back process is etched using H 3 PO 4 , characterized in that the manufacturing method of the semiconductor device. 제 1 항에서,In claim 1, 상기 산화막은 DHF를 이용하여 식각하는 것을 특징으로 하는, 반도체 소자의 제조 방법.The oxide film is etched using DHF, characterized in that the manufacturing method of the semiconductor device.
KR1020050133323A 2005-12-29 2005-12-29 Method of fabricating a semiconductor device KR100731074B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020077699A (en) * 2001-04-02 2002-10-14 아남반도체 주식회사 Method for a trench isolation for use in semiconductor manufacturing
KR20040002200A (en) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 Method for fabricating device isolation film of semiconductor device
KR20040054094A (en) * 2002-12-17 2004-06-25 아남반도체 주식회사 Method for fabricating trench of semiconductor device
KR20040059278A (en) * 2002-12-28 2004-07-05 동부전자 주식회사 Method For Manufacturing Semiconductor Devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020077699A (en) * 2001-04-02 2002-10-14 아남반도체 주식회사 Method for a trench isolation for use in semiconductor manufacturing
KR20040002200A (en) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 Method for fabricating device isolation film of semiconductor device
KR20040054094A (en) * 2002-12-17 2004-06-25 아남반도체 주식회사 Method for fabricating trench of semiconductor device
KR20040059278A (en) * 2002-12-28 2004-07-05 동부전자 주식회사 Method For Manufacturing Semiconductor Devices

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