KR20040001967A - Method for manufacturing metal line in semiconductor device - Google Patents
Method for manufacturing metal line in semiconductor device Download PDFInfo
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- KR20040001967A KR20040001967A KR1020020037302A KR20020037302A KR20040001967A KR 20040001967 A KR20040001967 A KR 20040001967A KR 1020020037302 A KR1020020037302 A KR 1020020037302A KR 20020037302 A KR20020037302 A KR 20020037302A KR 20040001967 A KR20040001967 A KR 20040001967A
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- layer
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- silicon nitride
- photoresist pattern
- etching
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000002184 metal Substances 0.000 title claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 31
- 239000011229 interlayer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B3/00—Window sashes, door leaves, or like elements for closing wall or like openings; Layout of fixed or moving closures, e.g. windows in wall or like openings; Features of rigidly-mounted outer frames relating to the mounting of wing frames
- E06B3/32—Arrangements of wings characterised by the manner of movement; Arrangements of movable wings in openings; Features of wings or frames relating solely to the manner of movement of the wing
- E06B3/34—Arrangements of wings characterised by the manner of movement; Arrangements of movable wings in openings; Features of wings or frames relating solely to the manner of movement of the wing with only one kind of movement
- E06B3/42—Sliding wings; Details of frames with respect to guiding
- E06B3/46—Horizontally-sliding wings
- E06B3/4663—Horizontally-sliding wings specially adapted for furniture
-
- E—FIXED CONSTRUCTIONS
- E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
- E05Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
- E05Y2201/00—Constructional elements; Accessories therefor
- E05Y2201/60—Suspension or transmission members; Accessories therefor
- E05Y2201/622—Suspension or transmission members elements
- E05Y2201/684—Rails; Tracks
-
- E—FIXED CONSTRUCTIONS
- E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
- E05Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
- E05Y2900/00—Application of doors, windows, wings or fittings thereof
- E05Y2900/30—Application of doors, windows, wings or fittings thereof for domestic appliances
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- Engineering & Computer Science (AREA)
- Civil Engineering (AREA)
- Structural Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속배선 제조방법에 관한 것으로, 보다 구체적으로는 다마신 공정을 이용한 금속배선 제조방법에 관한 것이다.The present invention relates to a method for manufacturing metal wiring of a semiconductor device, and more particularly to a method for manufacturing metal wiring using a damascene process.
통상, 금속배선은 두 가지 방법으로 형성되고 있다. 첫번째 방법은 금속막 상에 감광막 패턴을 형성하고, 그런다음, 상기 감광막 패턴을 식각 장벽으로 하는 플라즈마 식각 공정으로 상기 금속막을 직접 식각하여 소망하는 형태의 금속배선을 형성하는 방법이다. 그런데, 이 방법은 금속배선의 임계 치수(critical dimension)가 감소되고 있는 추세에서, 그 전기적 특성의 확보가 매우 어려운 문제점이 있다.Usually, metal wiring is formed by two methods. The first method is a method of forming a photoresist pattern on a metal film, and then directly etching the metal film by a plasma etching process using the photoresist pattern as an etching barrier to form a metal wiring in a desired form. However, this method has a problem that it is very difficult to secure the electrical characteristics in the trend that the critical dimension of the metal wiring is reduced.
두번째 방법은 다마신(damascene) 공정을 이용한 방법으로서, 이 방법은 전자의 방법 보다 상대적으로 우수한 전기적 특성을 얻을 수 있으며, 아울러, 공정 비용이 적기 때문에, 점차 그 이용이 확대되고 있다.The second method is a method using a damascene process, which is able to obtain relatively superior electrical characteristics than the former method, and also has a small process cost, and thus its use is gradually expanded.
도 1a 내지 도 1d는 종래 기술에 따른 다마신 공정을 이용한 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device using a damascene process according to the prior art.
종래 기술에 따른 반도체 소자의 금속배선 형성방법은, 도 1a에 도시된 바와같이, 반도체 기판(10)상에 하부 금속 배선층(12)을 형성한다. 도면에는 도시하지 않았지만, 상기 반도체 기판(10) 상에는 트랜지스터(transistor)와 같은 하부 패턴들(미도시) 및, 상기 하부패턴들을 덮는 층간절연막(미도시)이 형성되어 있다. 또한, 상기 층간절연막에는 상기 트랜지스터의 활성영역을 개구시키는 개구부(미도시)가 형성되며, 상기 개구부를 통해 하부 금속 배선층(12)이 상기 활성영역과 전기적으로 연결된다.In the method of forming metal wirings of a semiconductor device according to the prior art, as shown in FIG. 1A, the lower metal wiring layer 12 is formed on a semiconductor substrate 10. Although not shown in the drawing, lower patterns (not shown) such as transistors and an interlayer insulating film (not shown) covering the lower patterns are formed on the semiconductor substrate 10. In addition, an opening (not shown) for opening the active region of the transistor is formed in the interlayer insulating layer, and the lower metal wiring layer 12 is electrically connected to the active region through the opening.
이어, 상기 하부 금속 배선층(12)이 형성된 전체 구조 상면에 베리어 금속막(14), 저유전절연막(16), 옥사이드 계열의 절연막(18) 및 실리콘 질화막(20)의 2중 적층 구조의 하드마스크막을 차례로 형성한다. 그 다음, 상기 실리콘 질화막(20) 상에 비아홀영역을 정의하는 제 1감광막 패턴(50)을 형성한다.Next, a hard mask having a double stacked structure of the barrier metal film 14, the low dielectric insulating film 16, the oxide insulating film 18, and the silicon nitride film 20 on the upper surface of the entire structure on which the lower metal wiring layer 12 is formed. The films are formed in sequence. Next, a first photoresist layer pattern 50 defining a via hole region is formed on the silicon nitride layer 20.
이 후, 도 1b에 도시된 바와 같이, 상기 제 1감광막 패턴(50)을 식각장벽으로 실리콘 질화막을 식각하여 소정부분을 노출시킨다. 이때, 도면부호 21는 식각 공정 후에 잔류된 실리콘 질화막을 나타낸 것이다.Thereafter, as illustrated in FIG. 1B, the silicon nitride film is etched using the first photoresist pattern 50 as an etch barrier to expose a predetermined portion. In this case, reference numeral 21 denotes a silicon nitride film remaining after the etching process.
이어, 상기 제 1감광막 패턴을 제거하고 나서, 상기 결과의 기판 상에 트렌치영역을 정의하는 제 2감광막 패턴(52)을 형성한다.Subsequently, after removing the first photoresist pattern, a second photoresist pattern 52 defining a trench region is formed on the resultant substrate.
그런 다음, 도 1c에 도시된 바와 같이, 상기 실리콘 질화막(12)을 식각 장벽으로 하고 옥사이드계 절연막 및 저유전 절연막의 일부를 식각한다. 이때, 상기 식각 공정에서 저유전 절연막 전체에 대한 식각이 아닌 부분 식각을 진행한다.Then, as shown in FIG. 1C, the silicon nitride film 12 is used as an etch barrier and a portion of the oxide-based insulating film and the low dielectric insulating film are etched. At this time, in the etching process, partial etching is performed instead of etching the entire low dielectric insulating film.
이 후, 도 1d에 도시된 바와 같이, 상기 제 2감광막 패턴(23)을 식각 장벽으로 하고 실리콘 질화막(21), 옥사이드계 절연막, 저유전 절연막을 이방성 식각하여 하부 금속배선층(12)의 소정 부분을 노출시키는 비아홀(40)을 형성한다. 이때, 상기 이방성 식각 공정은 베리어 금속막을 식각정지점으로 이용한다.After that, as shown in FIG. 1D, the second photoresist layer pattern 23 is used as an etch barrier, and anisotropic etching of the silicon nitride layer 21, the oxide-based insulating layer, and the low dielectric layer is performed to form a predetermined portion of the lower metal wiring layer 12. To form a via hole 40 to expose the. In this case, the anisotropic etching process uses a barrier metal film as an etching stop point.
이어, 도면에 도시하지 않았지만, 상기 비아홀(40)을 매립시키는 다마신 구조의 상부 금속배선층(미도시)을 형성한다.Subsequently, although not shown in the drawing, an upper metal wiring layer (not shown) having a damascene structure filling the via hole 40 is formed.
그러나, 종래기술에서는, 비아홀 부분 식각시에 감광막 선택비가 낮아서 거의 대부분의 감광막(제 2감광막 패턴:52)이 제거되어 결국 후속의 트렌치 패턴 식각 공정을 진행하지 못하게 되는 문제점이 있었다.However, in the prior art, the photoresist selectivity is low at the time of the via hole partial etching, so that most of the photoresist film (second photoresist pattern 52) is removed, thereby preventing the subsequent trench pattern etching process.
따라서, 본 발명의 목적은, 선택비가 낮은 감광막을 사용하지 않고도 비아홀 부분 식각 공정을 진행할 수 있는 반도체 소자의 금속배선 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method for manufacturing a metal wiring of a semiconductor device capable of performing a via hole partial etching process without using a photoresist film having a low selectivity.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 제조공정도.2A to 2F are manufacturing process diagrams for explaining a method for manufacturing a semiconductor device according to the present invention.
상기 목적 달성을 위한 본 발명의 반도체 소자 금속배선 제조방법은, 반도체 기판 상에 하부 금속 배선층을 형성하는 단계; 하부 금속 배선층 상부에 배리어 절연막, 저유전 절연막. 옥사이드 계열의 절연막, 실리콘 질화막 및 산화질화막을 차례로 증착하는 단계; 산화질화막 상에 비아홀영역이 정의된 제 1감광막 패턴을 형성하는 단계; 제 1감광막을 마스크로 하고 상기 산화질화막 및 실리콘 질화막을 1차 식각하여 상기 절연막을 노출시키는 단계; 제 1감광막 패턴을 제거하는 단계; 1차 식각 공정이 완료된 기판에 트렌치영역을 한정하는 제 2감광막 패턴을 형성하는 단계; 제 2감광막 패턴을 마스크로 하고 절연막을 2차 건식 식각하는 단계; 제 2감광막 패턴을 마스크로 하고 잔류된 산화질화막을 3차 건식 식각하는 단계; 제 2감광막 패턴을 제거하는 단계; 잔류된 실리콘 질화막을 마스크로 하고 상기 저유전 절연막을 소정두께로 4차 건식 식각하는 단계; 및 잔류된 산화질화막을 마스크로 하고 식각 잔류물을 이방성으로 5차 건식 식각하여 하부금속 배선층 소정부분을 노출시키는 트렌치 구조를 가진 비아홀을 형성하는 단계를 포함한 것을 특징으로 한다.The semiconductor device metal wiring manufacturing method of the present invention for achieving the above object comprises the steps of: forming a lower metal wiring layer on a semiconductor substrate; A barrier insulating film and a low dielectric insulating film on the lower metal wiring layer. Sequentially depositing an oxide-based insulating film, a silicon nitride film, and an oxynitride film; Forming a first photoresist pattern on which the via hole region is defined; Exposing the insulating film by first etching the oxynitride film and the silicon nitride film using a first photoresist film as a mask; Removing the first photoresist pattern; Forming a second photoresist layer pattern defining a trench region on the substrate on which the primary etching process is completed; Second dry etching the insulating film using the second photoresist pattern as a mask; Tertiary dry etching the remaining oxynitride film using the second photoresist pattern as a mask; Removing the second photoresist pattern; Performing a fourth dry etching of the low dielectric insulating film to a predetermined thickness using the remaining silicon nitride film as a mask; And forming a via hole having a trench structure that exposes a predetermined portion of the lower metallization layer by using the remaining oxynitride film as a mask and etching the etching residue anisotropically by the fifth dry etching.
이하, 본 발명의 바람직한 실시예를 첨부한 도면에 의거하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명의 일실시예에 따른 반도체 소자의 금속배선 제조방법을 설명하기 위한 제조공정도이다.2A to 2F are manufacturing process diagrams for explaining a method for manufacturing metal wirings of a semiconductor device according to an embodiment of the present invention.
본 발명의 일실시예에 따른 반도체 소자의 금속배선 제조방법은, 도 2a에 도시된 바와같이, 반도체 기판(100) 상에 하부 금속 배선층(102)을 형성한다. 도면에는 도시하지 않았지만, 상기 반도체 기판(100) 상에는 트랜지스터와 같은 하부 패턴들이 형성되고, 상기 패턴들을 덮되 상기 트랜지스터의 활성영역을 노출시키는 개구부를 가진 층간절연막이 형성된다. 상기 층간절연막의 개구부를 통해 트랜지스터의 활성영역과 하부 금속배선층(102)이 전기적으로 연결된 구조를 가진다.In the method of manufacturing a metal wiring of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 2A, the lower metal wiring layer 102 is formed on the semiconductor substrate 100. Although not shown in the drawing, lower patterns such as transistors are formed on the semiconductor substrate 100, and an interlayer insulating layer having an opening covering the patterns but exposing the active region of the transistor is formed. The active region of the transistor and the lower metal wiring layer 102 are electrically connected to each other through an opening of the interlayer insulating layer.
이어, 상기 하부 금속 배선층(102)이 형성된 전체구조 상면에 베리어 절연막(104), 저유전 절연막(106), 옥사이드계열의 절연막(108), 실리콘 질화막(110) 및 산화질화막(112)을 차례로 형성한다. 이때, 상기 절연막(108), 질리콘 질화막(110) 및 산화질화막(112)은 100∼1000Å 두께로 형성한다. 또한, 상기 옥사이드계열의 절연막(108), 산화질화막(110) 및 실리콘 질화막(112)은 3중 적층 구조의 하드 마스크막이 된다.Subsequently, a barrier insulating film 104, a low dielectric insulating film 106, an oxide insulating film 108, a silicon nitride film 110, and an oxynitride film 112 are sequentially formed on an upper surface of the entire structure on which the lower metal wiring layer 102 is formed. do. In this case, the insulating film 108, the silicon nitride film 110 and the oxynitride film 112 are formed to a thickness of 100 ~ 1000∼. In addition, the oxide-based insulating film 108, the oxynitride film 110, and the silicon nitride film 112 may be a hard mask film having a triple stacked structure.
그 다음, 상기 산화질화막(112) 상에 비아홀영역이 정의된 제 1 감광막 패턴(150)을 형성한다.Next, a first photoresist layer pattern 150 having a via hole region defined on the oxynitride layer 112 is formed.
이 후, 도 2b에 도시된 바와같이, 상기 제 1감광막 패턴을 마스크로 하고 산화질화막 및 실리콘 질화막을 1차 건식 식각하여 절연막(108)을 노출시킨다. 이때, 도면 부호 111 및 113은 각각 1차 식각 공정에서 잔류된 실리콘 질화막 및 산화질화막을 나타낸 것이다.Thereafter, as shown in FIG. 2B, the first photoresist layer pattern is used as a mask, and the oxynitride layer and the silicon nitride layer are first dry-etched to expose the insulating layer 108. In this case, reference numerals 111 and 113 represent silicon nitride films and oxynitride films remaining in the first etching process, respectively.
이어, 제 1감광막 패턴을 제거하고 나서, 상기 1차 건식 식각이 완료된 결과물 상에 트렌치영역이 정의된 제 2감광막 패턴(152)을 형성한다.Subsequently, after the first photoresist pattern is removed, a second photoresist pattern 152 in which a trench region is defined is formed on the resultant of the first dry etching.
그런 다음, 도 2c에 도시된 바와 같이, 상기 1차 건식 식각 공정에서 잔류된 식각물(113) 및 제 2감광막(152)을 마스크로 하고 절연막을 2차 건식 식각하고 나서, 도 2d에 도시된 바와 같이, 제 2감광막 패턴(152)을 마스크로 하고 잔류된 산화질화막을 3차 건식 식각한다. 이때, 상기 2차 건식 식각 공정은 CxFy 계통의 실리콘 질화막에 대한 선택비가 있는 조건의 기체를 사용하며, 보조기체로는 O2, CO및 Ar 중 어느 하나를 이용한다.Then, as shown in FIG. 2C, the etching material 113 and the second photoresist layer 152 remaining in the first dry etching process are used as a mask, and the insulating film is secondly dry-etched, and then, as shown in FIG. 2D. As described above, the second photosensitive film pattern 152 is used as a mask, and the remaining oxynitride film is tertiarily dry-etched. In this case, the secondary dry etching process uses a gas having a selectivity to the silicon nitride film of the CxFy system, and uses any one of O 2, CO, and Ar as an auxiliary gas.
또한, 도면 부호 109는 2차 식각 공정에서 잔류된 절연막을 나타낸 것이고, 도면부호 113a은 3차 건식 식각공정에서 잔류된 산화질화막을 나타낸 것이다.In addition, reference numeral 109 denotes an insulating film remaining in the secondary etching process, and reference numeral 113a denotes an oxynitride film remaining in the tertiary dry etching process.
이 후, 제 2감광막 패턴을 제거하고 나서, 도 2e에 도시된 바와 같이, 잔류된 실리콘 질화막(111)을 마스크로 하고 저유전 절연막을 소정 두께로 4차 건식 식각한다. 이때, 저유전 절연막 식각 공정은, N2및 O2기체를 주 식각 기체로 사용하고, 보조가스로 C2H4,SO2및 Ar을 이용한다.Thereafter, after removing the second photoresist film pattern, as shown in FIG. 2E, the low dielectric insulating film is quaternarily dry-etched using the remaining silicon nitride film 111 as a mask. In this case, in the low dielectric insulating film etching process, N 2 and O 2 gas are used as the main etching gas, and C 2 H 4 , SO 2, and Ar are used as auxiliary gases.
이어, 도 2f에 도시된 바와 같이, 3차 건식 식각 공정에서 잔류된 산화질화막을 마스크로 하고 상기 식각 잔류물들(111,109, 106)을 5차 건식 식각하여 하부 금속배선층(102)의 소정 부분을 노출시키는 비아홀(140)을 형성한다. 또한, 5차 건식 식각 공정은 이방성 식각 공정으로 진행한다.Subsequently, as shown in FIG. 2F, the oxynitride layer remaining in the third dry etching process is used as a mask, and the etching residues 111, 109 and 106 are fifth dry etched to expose a predetermined portion of the lower metallization layer 102. To form a via hole 140. In addition, the fifth dry etching process proceeds to an anisotropic etching process.
본 발명에서는 실리콘 질화막 및 산화질화막 식각 공정은 CxHyFz 계통의 가스를 이용하고, 보조가스로는 O2, CO, Ar가스를 이용한다.In the present invention, the silicon nitride film and the oxynitride film etching process uses a CxHyFz-based gas, and the auxiliary gas uses O 2 , CO, or Ar gas.
이후, 도시하지 않았지만, 상기 형성된 비아홀 (140)을 매립시키는 반도체 소자의 상부 금속배선을 형성한다.Subsequently, although not shown, an upper metal wiring of the semiconductor device filling the formed via hole 140 is formed.
이상에서 설명한 본 발명은 상술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
상술한 본 발명의 반도체 소자 금속배선 제조방법에 의하면, 옥사이드계 절연막/실리콘 질화막/산화질화막의 3층 적층 구조의 마스크를 이용하여 듀얼 다마신 구조를 이용하여 금속배선을 형성함으로써, 감광막 마진 부족을 해결하고, 또한, 공정이 단순화되고 캐리어 이동시간이 감소되어 디바이스의 특성이 개선되는 이점이 있다.According to the method for manufacturing a semiconductor device metal wiring of the present invention described above, by forming a metal wiring by using a dual damascene structure using a mask of a three-layer laminated structure of an oxide-based insulating film / silicon nitride film / oxynitride film, there is a lack of photosensitive film margin In addition, there is an advantage that the process is simplified and the carrier travel time is reduced to improve the characteristics of the device.
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| CN103066088A (en) * | 2012-12-21 | 2013-04-24 | 豪威科技(上海)有限公司 | Manufacturing method of backside illuminated complementary metal-oxide-semiconductor transistor (CMOS) image sensor |
| CN103066093A (en) * | 2013-01-14 | 2013-04-24 | 陆伟 | Image sensor manufacturing method through adoption of deep groove isolation and image sensor structure |
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| KR20000033546A (en) * | 1998-11-24 | 2000-06-15 | 윤종용 | Semiconductor device having conductive lines formed by damascene process, and manufacturing method thereof |
| KR100384876B1 (en) * | 1999-06-24 | 2003-05-22 | 주식회사 하이닉스반도체 | Improved dual damascene process in semiconductor device |
| KR100596431B1 (en) * | 1999-06-30 | 2006-07-06 | 주식회사 하이닉스반도체 | Patterning method using top surface imaging process by silylation |
| KR100420413B1 (en) * | 2000-06-30 | 2004-03-03 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
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| CN103066088A (en) * | 2012-12-21 | 2013-04-24 | 豪威科技(上海)有限公司 | Manufacturing method of backside illuminated complementary metal-oxide-semiconductor transistor (CMOS) image sensor |
| CN103066093A (en) * | 2013-01-14 | 2013-04-24 | 陆伟 | Image sensor manufacturing method through adoption of deep groove isolation and image sensor structure |
| CN103066093B (en) * | 2013-01-14 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | A kind of deep trench isolation manufactures method and the image sensor structure of image sensor |
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