KR20030072115A - Driving method of plasma display panel - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel is provided to perform an addressing operation with high speed by overlapping an address period with a sustain period in a driving process. CONSTITUTION: A method for driving a plasma display panel includes a process for driving the plasma display panel in divided blocks of n number. In the driving method, an address period is overlapped with a sustain period in the divided blocks of n number. Scan pulses are sequentially supplied to the first electrode of the ith block. Data pulses are supplied to an address electrode when the scan pulses are sequentially supplied to the first electrode. The first sustain pulse is supplied to the first electrode of the ith block. The scan pulses are supplied to the first electrode of the i+1th block when first sustain pulse is supplied to the first electrode of the ith block.

Description

Driving method of plasma display panel {DRIVING METHOD OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel capable of high speed addressing.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when vacuum ultraviolet rays generated by gas discharge excite the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP is formed on a first electrode 12Y and a second electrode 12Z formed on an upper substrate 10, and on a lower substrate 18. The address electrode 20X is provided.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the first electrode 12Y and the second electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the first electrode 12Y and the second electrode 12Z.

The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible rays of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper substrate 10, the lower substrate 18, and the partition wall 24.

2 is a view showing a driving apparatus of a conventional three-electrode AC surface discharge type plasma display.

Referring to FIG. 2, in the driving apparatus of a conventional three-electrode AC surface discharge type PDP, m × n discharge cells 1 may include first electrode lines Y1 to Ym and second electrode lines Z1 to Zm. And a PDP 30 arranged in a matrix so as to be connected to the address electrode lines X1 to Xn, a scan / sustain driver 32 for driving the first electrode lines Y1 to Ym, and a second The common sustain driver 34 for driving the electrode lines Z1 to Zm, the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and the even-numbered address electrode lines X2. First and second address drivers 36A and 36B for dividing and driving .X4, ..., Xn-2, Xn are provided.

The scan / sustain driver 32 sequentially supplies scan pulses to the first electrode lines Y1 to Ym. In addition, the scan / sustain driver 32 supplies a sustain pulse to the first electrode lines Y1 to Ym in common. The common sustain driver 34 supplies a sustain pulse to all of the second electrode lines Z1 to Zm.

The first and second address drivers 36A and 36B supply image data to the address electrode lines X1 through Xn in synchronization with the scan pulse. The first address driver 36A supplies image data to the odd address electrode lines X1, X3, ..., Xn-3, Xn-1. The second address driver 36B supplies image data to even-numbered address electrode lines X2, X4, ..., Xn-2, Xn.

Such a PDP is driven by dividing one frame into several subfields having different discharge times in order to express gray levels of an image. Each subfield is further divided into an initialization period for generating discharge uniformly, an address period for selecting discharge cells, and a sustain period for expressing gray levels according to the number of discharges.

For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. In addition, each of the eight subfields SF1 to SF8 is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased.

4 is a waveform diagram showing a driving method of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 4, one subfield may include a reset period for initializing all screens, an address period for writing data while scanning the entire screen in a linear order manner, a sustain period for maintaining the light emission state of cells in which data is written, and a sustain period. It is divided into an erasing period for erasing discharge.

First, in the reset period, the reset waveform RP is supplied to the first electrode lines Y1 to Ym. When the reset waveform RP is supplied to the first electrode lines Y1 to Ym, a reset discharge is generated between the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm to initialize the discharge cell. do.

In the address period, the scan pulse SP is sequentially applied to the first electrode lines Y1 to Ym. The data pulse Dp synchronized with the scan pulse SP is applied to the address electrode lines X1 to Xn. At this time, address discharge occurs in the discharge cells to which the data pulse Dp and the scan pulse SP are applied.

In the sustain period, the first and second sustain pulses SUSPy and SUSPz are supplied to the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm. At this time, sustain discharge is generated in the discharge cells in which the address discharge is generated.

In the erase period, the erase pulse Ep is supplied to the second electrode lines Z1 to Zm. When the erase pulse Ep is supplied to the second electrode lines Z1 to Zm, the sustain discharge is erased.

In such a conventional PDP, sufficient time must be allocated to the address period so that the address discharge can be made stable, that is, miswriting can be prevented. For example, the pulse width of the scan pulse SP supplied to the first electrode lines Y1 to Ym in the address period may be set to 2.8 GHz to prevent miswriting.

When a scan pulse SP having a pulse width of 2.8 [mu] s is supplied to a video graphics array (VGA) class PDP and one frame includes eight subfields, the address period requires 11.52 [mu] s in total. In contrast, the sustain period is assigned 3.05 ms in consideration of the vertical synchronization signal Vsync. In other words, too short a time is allocated to the sustain period which contributes to the luminance, and thus it is impossible to display sufficient luminance.

Accordingly, an object of the present invention is to provide a method of driving a plasma display panel that enables high speed addressing.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a view showing a driving apparatus of a conventional three-electrode AC surface discharge type plasma display.

3 is a view showing one frame of a conventional three-electrode AC surface discharge type plasma display panel.

Fig. 4 is a waveform diagram showing driving waveforms supplied to one subfield of a conventional three-electrode alternating surface discharge type plasma display panel.

5 illustrates a plasma display panel according to an embodiment of the present invention.

6 is a view showing a method of driving a plasma display panel according to a first embodiment of the present invention;

7 is a view showing a driving method of a plasma display panel according to a second embodiment of the present invention;

8 is a view showing a driving method of a plasma display panel according to a third embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y: first electrode

12Z: second electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26 phosphor layer 30, 40 plasma display panel

32: scan / sustain driver 34: common sustain driver

36A, 36B: Address driver 42A, 42B, 42N: block

In order to achieve the above object, in the driving method of the plasma display panel of the present invention, an address period for selecting a discharge cell to be turned on and a sustain period for generating sustain discharge in the discharge cell selected in the address period overlap each other with the address period and block.

Sequentially supplying scan pulses to the first electrode included in the i (i is a natural number greater than 0) block; supplying data pulses to the address electrode when the scan pulses are supplied to the first electrode; The first sustain pulse is supplied to the first electrode after the scan pulse is supplied to the first electrode, and the first + second block included in the i + first block when the first sustain pulse is supplied to the first electrode included in the i-th block The scanning pulse is supplied to one electrode.

When a scan pulse is supplied to any one of the first electrodes included in the n blocks, a second sustain pulse is supplied to all second electrodes included in the n blocks.

The second sustain pulse is supplied in synchronization with the scan pulse.

The second sustain pulse is supplied to alternate with the first sustain pulse.

When the first sustain pulse is supplied to the first electrode included in the i-th block, a second sustain pulse alternated with the first sustain pulse is supplied to the second electrode included in the i-th block.

One frame of the plasma display panel is divided into n subfields, and different gray levels are displayed for each block in one subfield.

Displaying a gray level value of j in an i-th block of the i th subfield, displaying a gray level value of j-1 in an i-1 th block of the i th subfield, and displaying an i + 1 subfield In the i-th block, a gray value of j-1 is displayed.

A plasma display panel according to another embodiment of the present invention comprises the steps of: dividing the panel into n (n is one or more natural numbers) blocks to include at least one first electrode and a second electrode; dividing j (j is a natural number less than n) blocks into one block group so that n blocks can be divided into at least two block groups; An address period for selecting a discharge cell to be turned on and a sustain period for causing sustain discharge in the discharge cell selected in the address period overlap each other with the address period and the block groups.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 8.

5 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the PDP 40 according to an embodiment of the present invention is divided into n blocks (n is a natural number of 1 or more) 42 blocks 42A, 42B, ..., 42N, and each of the n blocks is k At least one natural number) first electrode line (Y) and second electrode line (Z).

In other words, k first electrode lines Y1, ... Yk and k second electrode lines Z1, ... Zk are formed in the first block 42A. In addition, k first electrode lines Yk + 1, ... Y2k and k second electrode lines Zk + 1, ..., Z2k are formed in the second block 42B.

As such, the PDP 40 according to the embodiment of the present invention is driven in units of blocks. On the other hand, the PDP 40 according to the embodiment of the present invention includes an address electrode (not shown) formed in a direction crossing the first electrode line (Y) and the second electrode line (Z).

FIG. 6 is a diagram illustrating a first driving method of the PDP according to the first embodiment of the present invention shown in FIG. 5.

Referring to FIG. 6, the subfields of the PDP according to the first embodiment of the present invention are driven by being divided into a reset period, an address / sustain period, and an erase period.

First, the reset waveform RP is supplied to the first electrode lines Y1 to Ynk in the reset period. When the reset waveform RP is supplied to the first electrode lines Y1 to Ynk, a reset discharge is generated between the first electrode lines Y1 to Ynk and the second electrode lines Z1 to Znk to initialize the discharge cell. do.

In the address / sustain period, an address and a sustain are performed simultaneously. In detail, first, the scan pulse SP is sequentially supplied to the first electrode lines Y1 to Yk formed in the first block 42A. The data pulse Dp synchronized with the scan pulse SP is applied to the address electrode lines X. At this time, address discharge occurs in the discharge cells to which the data pulse Dp and the scan pulse SP are applied.

Meanwhile, the second sustain pulse SUSPz is supplied to the second electrode lines Z1 to Znk in the address / sustain period. As such, the second sustain pulse SUSPz is supplied to be synchronized with the scan pulse SP supplied to the first electrode lines Y1 to Ynk. In other words, when the scan pulse SP is supplied to the first electrode lines Y1 to Ynk, the bipolar second sustain pulse SUSPz is supplied to the second electrode lines Z1 to Znk. This is the same as the conventional address discharge condition.

In other words, when the scan pulse SP is supplied to the first electrode line Y in the conventional address period, the bipolar pulse is supplied to the second electrode line Z. Similarly, since the second sustain pulse SUSPz according to the embodiment of the present invention is supplied in synchronization with the scan pulse SP, the address discharge condition is satisfied. Therefore, even when scan pulses are supplied to the second electrode lines Z1 to Znk in the address / sustain period, address discharge can be caused without miswriting.

Meanwhile, after the scan pulse is supplied to the first electrode lines Y1 to Yk of the first block 42A, the first sustain pulse SUSPy is supplied to the first electrode lines Y1 to Yk. The first sustain pulse SUSPy is supplied alternately with the second sustain pulse SUSPz. Therefore, sustain discharge occurs in the discharge cells in which the address discharge has occurred among the discharge cells included in the first block 42A.

As such, when the first sustain pulse SUSPy is supplied to the first electrode lines Y1 to Yk included in the first block 42A, the first electrode lines Yk + included in the second block 42B. 1 to Y2k), the scan pulse SP is supplied. After the scan pulse SP is supplied to the first electrode lines Yk + 1 to Y2k included in the second block 42B, the first sustain pulse SUSPy is applied to the first electrode lines Yk + 1 to Y2k. ) Is supplied. In the present invention, the first electrode lines Y (n-1) +1 to Ynk included in the n-th block 42N are sequentially driven in this manner.

As described above, in the present invention, the address period and the sustain period are overlapped for each block, thereby shortening the address period. In other words, when a specific block is performing address discharge, sustain discharge occurs in other blocks, thereby minimizing address time.

6, the highest gray value is represented in the first block 42A, and the lowest gray value is represented in the nth block 42N. Subsequently, in the next subfield, the highest gray value is represented in the second block 42A, and the lowest gray value is represented in the first block 42A. In other words, in the present invention, if the PDP is divided into eight blocks, the grayscale value of one frame may be expressed as shown in Table 1 below.

1 block 2 blocks 3 blocks 4 blocks 5 blocks 6 blocks 7 blocks 8 blocks 128 64 32 16 8 4 2 One One 128 64 32 16 8 4 2 2 One 128 64 32 16 8 4 4 2 One 128 64 32 16 8 8 4 2 One 128 64 32 16 16 8 4 2 One 128 64 32 32 16 8 4 2 One 128 64 64 32 16 8 4 2 One 128

Referring to Table 1, one frame is divided into eight subfields (the driving waveform of FIG. 6 corresponds to the first subfield of Table 1). In each subfield, a gray level value expressed for each block is different. .

In other words, the scan pulse is supplied from the first block to the eighth block in the first subfield. Therefore, the highest gray value is represented in the first block, and the lowest gray value is represented in the eighth block.

In the second subfield, scan pulses are supplied from the second block to the first block. Therefore, the highest gray value is represented in the second block in the second subfield, and the lowest gray value is represented in the first block.

On the other hand, in the eighth subfield, the scan pulse is supplied from the eighth block to the seventh block. Therefore, the highest gray value is represented in the eighth block in the eighth subfield, and the lowest gray value is represented in the seventh block. In this manner, in the present invention, an image according to a gray value may be expressed in all blocks during one frame.

In the erase period, the erase pulse Ep is supplied to the second electrode lines Z1 to Zm. When the erase pulse Ep is supplied to the second electrode lines Z1 to Zm, the sustain discharge is erased.

FIG. 7 is a diagram illustrating a second driving method of the PDP according to the embodiment of the present invention shown in FIG. 5.

Referring to FIG. 7, in the second driving method of the PDP according to the embodiment of the present invention, one subfield is driven by being divided into a reset period, an address / sustain period, and an erase period.

The reset period and the erase period in the second drive method of the present invention are the same as the first drive method of the present invention shown in FIG. Therefore, the description of the reset period and the erase period will be omitted.

In the address / sustain period, an address and a sustain are performed simultaneously. In detail, first, the scan pulse SP is sequentially supplied to the first electrode lines Y1 to Yk formed in the first block 42A. The data pulse Dp synchronized with the scan pulse SP is applied to the address electrode lines X. At this time, address discharge occurs in the discharge cells to which the data pulse Dp and the scan pulse SP are applied.

Thereafter, the first sustain pulse SUSPy is supplied to the first electrode lines Y1 to Yk formed in the first block 42A. In this case, the second sustain pulse SUSPz is supplied to the second electrode lines Z1 to Zk formed in the first block 42A so as to alternate with the first sustain pulse SUSPy. That is, in the second driving method of the present invention, the second electrode lines Z are driven for each of the blocks 42A, 42B, ..., 42N.

Compared with the first driving method of the present invention shown in FIG. 6, the second electrode lines Z1 to Znk are commonly driven in the first driving method of the present invention. Accordingly, the second sustain pulse SUSPz is supplied to all of the second electrode lines Z1 to Znk in the address / sustain period.

However, in the second driving method of the present invention, the second electrode lines Z are driven block by block. Therefore, after the scan pulse SP is supplied to the first electrode lines Y1 to Yk formed in the first block 42A, the second sustain pulse SUSPz is supplied to the second electrode lines Z1 to Zk. do. Similarly, after the scan pulse SP is supplied to the first electrode lines Y (n-1) +1 to Ynk formed in the nth block 42N, the second electrode lines Z (n-1) + are supplied. 1 to Znk is supplied with a second sustain pulse SUSPz.

As described above, the second driving method of the present invention overlaps the address period and the sustain period similarly to the first driving method of the present invention, thereby enabling high-speed addressing. On the other hand, the gray scale expression method in the second driving method of the present invention is the same as the first embodiment of the present invention.

Meanwhile, in the present invention, a plurality of blocks including at least one first electrode line Y may be driven by one block group. At this time, the PDP has a block group corresponding to the gray scale value to be expressed. For example, in the case of representing 256 gray levels, the PDP is divided into eight block groups.

FIG. 8 is a waveform diagram showing a driving method when one block includes two first electrode lines Y. FIG.

8, the scan pulse SP is sequentially supplied to the Y1 and Y2 first electrode lines Y1 and Y2 formed in the first block L during the address / sustain period. Thereafter, the scan pulse SP is sequentially supplied to the Yj + 1 and Yj + 2 first electrodes Yj + 1 and Yj + 2 formed in the jth j (j is a natural number of 0 or more) block L + j. do.

That is, in the present invention, the first block L, the j-th block L + j, and the like are driven in one block group. Scan pulses SP are sequentially supplied to the first electrodes Y included in one block group. After the scan pulse Sp is supplied to the first electrodes Y included in one block group, the first sustain pulse SUSPy is supplied to the first electrodes Y.

Meanwhile, the second sustain pulse SUSPz is supplied to the second electrode lines Z in the address / sustain period. The second sustain pulse SUSPz is supplied in synchronization with the scan pulse SP supplied to the first electrode lines Y1 to Ynk. In other words, when the scan pulse SP is supplied to the first electrode lines Y1 to Ynk, the bipolar second sustain pulse SUSPz is supplied to the second electrode lines Z1 to Znk.

As such, the second sustain pulse SUSPz supplied to the second electrode Z may be supplied as the second driving method of the present invention illustrated in FIG. 7.

When the first sustain pulse SUSPy is supplied to the first electrode lines Y included in the first block group, the second electrode lines Y included in the second block L + 1 are sequentially formed. Scan pulse SP is supplied. That is, when the electrodes included in the first block group are sustain driven, the electrodes included in the second block group are address driven. Through this process it is driven from the first block group to the n-th block group. On the other hand, the gray scale representation method and the like are the same as the driving methods of the present invention shown in Figs.

As described above, according to the driving method of the plasma display panel according to the present invention, high-speed addressing can be performed by driving the address period and the sustain period to overlap each other.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A driving method of a plasma display panel driven by dividing n (n is one or more natural numbers) blocks; And an address period for selecting a discharge cell to be turned on and a sustain period for causing sustain discharge in the discharge cell selected in the address period overlap each other with the address period. The method of claim 1, Sequentially supplying scan pulses to a first electrode included in the i (i is a natural number greater than 0) block; Supplying a data pulse to an address electrode when a scan pulse is supplied to the first electrode; Supplying a first sustain pulse to the first electrode after the scan pulse is supplied to the first electrode; And supplying a scan pulse to the first electrode included in the i + 1 th block when the first sustain pulse is supplied to the first electrode included in the i th block. . The method of claim 1, And a second sustain pulse is supplied to all second electrodes included in the n blocks when a scan pulse is supplied to any one of the first electrodes included in the n blocks. How to drive the panel. The method of claim 3, wherein And the second sustain pulse is supplied in synchronization with a scan pulse. The method of claim 2 or 3, And the second sustain pulse is supplied alternately with the first sustain pulse. The method of claim 2, When the first sustain pulse is supplied to the first electrode included in the i-th block, the second sustain pulse alternated with the first sustain pulse is supplied to the second electrode included in the i-th block. How to drive the display panel. The method of claim 1, One frame of the plasma display panel is divided into n subfields, and different gray levels are displayed for each block in one subfield. The method of claim 7, wherein Displaying a gray value of j in an i th block of the i th subfield; Displaying a gray value of j-1 in an i-1th block of the ith subfield; And a gray value of j-1 is displayed in the i-th block of the i + 1th subfield. Dividing the panel into n (n is one or more natural numbers) blocks to include at least one first and second electrodes; Dividing j blocks (j is a natural number less than n) into one block group so that the n blocks can be divided into at least two block groups; And an address period for selecting a discharge cell to be turned on and a sustain period for causing sustain discharge in the discharge cell selected in the address period overlap each of the address period and the block groups.