KR20030054279A - A thin film transistor array substrate for a liquid crystal display and method manufacturing the same - Google Patents

Abstract

PURPOSE: A thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same are provided to minimize contact resistance at contacting parts and slowly form profiles of contact parts by removing under cut at the contact parts by using a semiconductor layer as an etching stopper layer. CONSTITUTION: A chrome lower film(201) and an aluminum alloy conductive film(202) are sequentially accumulated and patterned to form gate wire including gate lines(22), gate electrodes(24), and gate pads(26) on a substrate. A gate insulating film(30) is formed on the gate wire, and a semiconductor layer(40) and resistance contact layers(55,56) are sequentially formed on the gate insulating film. Data wire including data lines, source and drain electrodes(65,66), and data pads(68) is formed. A protective layer(70) is accumulated and patterned to form contacts holes(74,76,78) exposing the drain electrodes, the gate pads, and the data pads. The contact holes are formed to expose the lower film of the gate lines and the data lines, and expose boundary lines of the drain electrodes, the gate pads, and the data pads, wherein boundary lines of the contact holes exposing the drain electrodes and the data pads are placed on the semiconductor layer exposed outside the drain electrodes and the data pads.

Description

A thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same {A THIN FILM TRANSISTOR ARRAY SUBSTRATE FOR A LIQUID CRYSTAL DISPLAY AND METHOD MANUFACTURING THE SAME}

The present invention relates to a thin film transistor array substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is used.

In general, a substrate including a thin film transistor includes a wiring line including a gate line for transmitting a scan signal and a data line for transmitting an image signal, and a scan signal or an image signal from an external source, respectively, to the gate line and the data line. A gate pad and a data pad to be transferred are formed, and a pixel electrode electrically connected to the thin film transistor is formed in a pixel region defined by crossing the gate line and the data line.

In the method of manufacturing a thin film transistor array substrate for a liquid crystal display device, a process of exposing a wire to expose a pad or connecting other wires to receive a signal from the outside is required. However, when the lower layer is etched using the insulating film having contact holes as a mask, step coverage of the contact portion is deteriorated when severe under cut occurs under the insulating film. As a result, there is a problem in that a profile of another upper layer formed afterwards is deteriorated or a disconnection occurs at the contact portion, thereby degrading reliability of the pad portion or the contact portion. In order to solve this problem, it is preferable to form a stepped sidewall of the contact hole in the contact portion, but this has a problem in that the manufacturing process is complicated because the insulating film must be patterned by several photolithography processes.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the same, which can eliminate contact defects in a contact portion and improve a profile of the contact portion.

In addition, another object of the present invention is to simplify the manufacturing method of the thin film transistor array substrate.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along line IV-IV.

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate, illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 and 9 are cross-sectional views of the thin film transistor substrate shown in FIG. 7 taken along lines VIII-VIII 'and IX-IX',

10A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

10B and 10C are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' in FIG. 10A, respectively.

11A and 11B are cross-sectional views taken along the lines Xb-Xb 'and XVc-Xc' in FIG. 10A, respectively, and are cross-sectional views taken in the next steps of FIGS. 10B and 10C, and

12A is a layout view of a thin film transistor substrate in FIGS. 11A and 11B next steps;

12B and 12C are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively.

13A, 14A, 15A and 13B, 14B, and 15B are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, illustrating the following steps in the order of the process. ,

16A is a layout view of a thin film transistor substrate at a next step of FIGS. 15A and 15B,

16B and 16C are cross-sectional views taken along the lines XVIb-XVIb 'and XVIc-XVIc', respectively, of FIG. 16A.

In order to solve this problem, in the present invention, the wiring is formed by including a conductive film of aluminum or aluminum alloy, and the sidewall of the wiring is exposed through the contact hole at the contact portion, and another layer is extended to the outside of the boundary of the wiring where the sidewall is exposed. Used as an etch stop layer.

More specifically, the thin film transistor array substrate for a liquid crystal display according to the present invention includes a gate line, a gate electrode connected to the gate line, and a gate connected to the gate line and receiving a scan signal from the outside to the gate line on the insulating substrate. The gate wiring including the pad is formed. A semiconductor layer is formed on an upper portion of the gate insulating layer covering the gate wiring, and a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode separated from the source electrode and facing the source electrode centered on the gate electrode. And a data pad connected to the data line to receive an image signal from the outside and transmit the image signal to the data line. A pixel electrode electrically connected to the drain electrode is formed on the passivation layer covering the data line and the semiconductor layer. In this case, a portion of the semiconductor layer except for the channel portion between the source and drain electrodes extends at least outside the boundary line between the drain electrode and the data pad, and is used as an etch stop layer for preventing the gate insulating layer from being etched at the contact portion during the manufacturing process.

Here, the passivation layer has a contact hole for exposing the data pad, the drain electrode or the gate pad, and the boundary line of the data pad, the drain electrode or the gate pad is preferably exposed through the contact hole, and the contact hole for exposing the drain electrode or the data pad is formed. The boundary line is preferably positioned above the semiconductor layer extending out of the boundary line of the drain electrode and the data pad.

In this case, the gate wiring or the data wiring may be formed of a lower layer of chromium, molybdenum or molybdenum alloy, and an upper layer of aluminum or aluminum alloy.

In addition, the thin film transistor array substrate for a liquid crystal display according to the present invention is formed on the same layer as the pixel electrode, and the auxiliary data pad or auxiliary data pad which is in contact with at least a gate pad or a lower layer of the data pad through a contact hole. It includes more.

The protective layer may be made of silicon nitride or an organic insulating material, and the pixel electrode may be made of IZO.

Then, a thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. Explain.

Next, a thin film transistor array substrate and a manufacturing method for a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

First, a structure of a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II '.

The lower layer 201 made of a conductive material having a low contact resistance and contacting other materials such as chromium or molybdenum or molybdenum alloy or tantalum or titanium with low resistance on the insulating substrate 10 and aluminum or aluminum alloy or silver or silver A gate wiring including an upper film 202 made of a conductive material having a low resistance such as an alloy is formed. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating layer 30, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), Data wires 62, 64, 66, 68 made of metal or a conductor such as titanium (Ti) are formed. The data line is formed in a vertical direction and is connected to the data line 62 and the data line 62 defining the pixel by crossing the gate line 22, and extending to an upper portion of the ohmic contact layer 54. 65, a data pad 68 connected to one end of the data line 62 and separated from the source pad 65 and the source electrode 65 to which an image signal from the outside is applied, and the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed over the opposite ohmic contact layer 56.

The data lines 62, 65, 66, 68 are preferably formed of a single film of aluminum or aluminum alloy, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having a low contact resistance with other materials, especially IZO. Examples include Al (or Al alloys) / Cr or Al (or Al alloys) / Mo (or Mo alloys), and the like. In an embodiment of the present invention, the data wires 62, 65, 66, and 68 are made of chromium. The double film of the lower film 601 and the upper film 602 of aluminum-neodymium alloy.

In this case, the semiconductor layer 40 is generally formed under the data line 62, and particularly, extends beyond the boundary lines of the 66 and 68 under the drain electrode 66 and the data pad 68. This prevents undercuts from occurring at the bottom of the drain electrode 66 and the data pad 68 when forming contact holes exposing the drain electrode 66 and the data pad 68 in the manufacturing process of the thin film transistor array substrate. It is extended for the purpose of this, it will be described in detail in the subsequent manufacturing process.

The passivation layer 70 made of silicon nitride is formed on the data lines 62, 65, 66, and 68 and the semiconductor layer 40 which is not covered.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the data pad 68, respectively. The contact hole 74 exposing the gate pad 24 together with the gate insulating layer 30 is formed. Is formed. In this case, the boundary of the drain electrode 66 and the data pad 68 is exposed in the contact holes 76 and 78, and the boundary of the contact holes 76 and 78 is located above the semiconductor layer 40. The upper electrode 602 of the drain electrode 76 and the data pad 68 is removed so that only the drain electrode 66 and the lower layer 601 of the data pad 68 are exposed in the contact holes 76 and 78. In addition, the contact hole 74 exposing the gate pad 24 is formed so that the boundary line of the gate pad 24 is exposed, and only the lower layer 2010 of the gate pad 24 is exposed.

On the passivation layer 70, a pixel electrode 82 electrically connected to the drain electrode 66 and positioned in the pixel is formed through the contact hole 76. At this time, the pixel electrode 82 is in sufficient contact with the lower layer 601 of the drain electrode 66 exposed from the contact hole 76.

In addition, the auxiliary gate pad 86 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. At this time, the auxiliary data pad 88 is in contact with the lower layer 601 of the data pad 68 exposed by the contact hole 78. The pixel electrode 82, the auxiliary gates, and the data pads 86 and 88 are made of indium zinc oxide (IZO).

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

Next, a method of manufacturing the TFT array substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 6B.

First, as shown in FIGS. 3A and 3B, 2 at% Nd of the metal of the aluminum alloy having low resistance and chromium, which is one of the conductive materials having low contact resistance with other materials, particularly IZO, is placed on the substrate 10. Stacking and patterning the Al-Nd alloy containing by sputtering to include a gate line 22, a gate electrode 26 and a gate pad 24 consisting of a lower layer 201 and an upper layer 202 and tapered A horizontal gate wiring having a structure is formed.

Next, as shown in FIGS. 4A and 4B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is successively laminated, and a mask is formed. The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 facing the gate electrode 24 by patterning the semiconductor layer 40 and the doped amorphous silicon layer 50 by the patterning process. do. In this case, the semiconductor layer 40 and the ohmic contact layer 50 may be formed to extend along the data lines formed thereafter, particularly at the lower portion of the drain electrode 66 and the data pad 68. It is formed to extend beyond the boundary line.

Next, as shown in Figs. 5A to 5B, the lower film 601 made of molybdenum, molybdenum alloy, chromium or the like has a thickness of about 500 GPa, and 2 at% of the metal of aluminum or aluminum alloy having low resistance. The upper layer 602 was sequentially laminated by sputtering at a temperature of about 150 ° C. to about 2,500 mm using a target of Al-Nd alloy including Nd, and then patterned by a photo process using a mask to form a gate line. A data line 62 intersecting with the 22, a source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26, and a data pad 62 connected to one end thereof. 68 and the drain electrode 66 which is separated from the source electrode 64 and faces the source electrode 65 around the gate electrode 26, and forms a data wiring having a tapered structure. Here, both the upper layer 602 and the lower layer 601 may be etched by wet etching, the upper layer 602 may be etched by wet etching, and the lower layer 601 may be etched by dry etching, and the lower layer 601 may be etched. ) Is a molybdenum or molybdenum alloy film may be patterned by one etching condition with the upper film 602. In addition, an opening may be formed in the drain electrode 66 or the data pad 68 so that a part of the semiconductor layer 40 is exposed.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 6A and 6B, an inorganic insulating film such as silicon nitride is laminated in the range of 250 to 400 ° C. or an inorganic insulating film is applied to form the protective film 70, and the gate insulating film is subjected to a photolithography process using a mask. Patterned by dry etching together with 30 to form contact holes 74, 76, 78 that expose the gate pad 24, the drain electrode 66, and the data pad 68, respectively. In this case, the contact holes 74, 76, and 78 are formed so that the boundary line of the gate pad 24, the drain electrode 66, and the data pad 68 is exposed, but the contact which exposes the drain electrode 66 and the data pad 68 is exposed. The boundary line of the holes 76 and 78 is formed to be located above the semiconductor layer 40, and the semiconductor layer 40 must be etched under an etching condition where the semiconductor layer 40 is not etched. This prevents the etching of the gate layer 30 from being etched to the lower portion of the semiconductor layer 40 when forming the contact holes 74, 76, and 78 using the semiconductor layer 40 as an etch stop layer. This is to prevent undercuts from occurring in the lower portions of the drain electrode 66 and the data pad 68 when forming the contact holes 76 and 78. That is, when the boundary lines of the contact holes 76 and 78 are located outside the semiconductor layer 40, the gate insulating film under the drain electrode 66 or the data pad 68 when the contact holes 76 and 78 are formed. 30 is excessively etched and undercut occurs. In this case, the pixel electrode 82 or the auxiliary data pad 88 formed thereafter may be disconnected from the lower portion of the drain electrode 66 and the data pad 68 due to the step difference of the gate insulating layer 30. Contact failure occurs at the contact or the contact resistance of the contact increases.

Subsequently, an aluminum front surface is etched to etch the aluminum alloy films 202 and 602 exposed through the contact holes 74, 76 and 78 to etch the gate pads 24 and the data pads at the contact holes 74, 76 and 78. 66 and the lower layer 601 is exposed at the drain electrode 68. This is to minimize the contact resistance with the IZO film formed later in the contact portion.

Next, as shown in FIGS. 1 and 2, the IZO film is laminated by sputtering and patterned using a mask to contact the pixel electrode 82 and the contact hole connected to the drain electrode 66 through the contact hole 76. An auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 are formed through the 74 and 78, respectively. In this case, the pixel electrode 82 and the auxiliary data pad 88 are not disconnected because under cut does not occur at the bottom of the drain electrode 66 and the data pad 68, and the profile of the contact portion is formed smoothly, and the IZO film ( 82, 84, and 88 are sufficiently in contact with the lower layer 601 having low contact resistance, thereby minimizing contact resistance of the contact portion. In the exemplary embodiment of the present invention, a target for forming the IZO films 82, 86, and 88 is a product called indium x-metal oxide (IDIXO) manufactured by Imitsu, and the target is In ₂ O ₃ and ZnO, and the content of Zn in In + Zn is preferably in the range of 15-20 at%. In addition, in order to minimize contact resistance, the IZO film is preferably laminated in the range of 250 ° C or lower.

The structure of the thin film transistor array substrate according to the embodiment of the present invention includes a conductive film of aluminum or aluminum alloy in which the gate wirings 22, 24, 26 and the data wirings 62, 64, 66, and 68 have low resistance. At the same time, the contact resistance between the contact portion, in particular, the data wiring and the pixel electrode 82 of the IZO film can be minimized, so that it can be applied to a liquid crystal display device having a large screen. In addition, the semiconductor layer while ensuring the contact characteristics of the contact portion

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9.

FIG. 7 is a layout view of a thin film transistor substrate for a liquid crystal display device according to a second exemplary embodiment of the present invention, and FIGS. 8 and 9 are lines VIII-VIII 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. A cross-sectional view taken along the line.

First, a gate wiring including a low resistance conductive material of aluminum or an aluminum alloy and including a gate line 22, a gate pad 24, and a gate electrode 26 is formed on the insulating substrate 10 as in the first embodiment. Formed. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive pattern 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

The gate wirings 22, 24, 26, and 28 may likewise be formed of a single layer made of aluminum or an aluminum alloy, but the lower layer 201 made of chromium or molybdenum or molybdenum alloy or tantalum or titanium having a low contact resistance with IZO. ) And an upper film 202 made of aluminum or an aluminum alloy having low resistance.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, a data line including a conductive film made of a conductive material of aluminum or an aluminum alloy having low resistance is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may also be formed of a single layer made of a metal of aluminum or an aluminum alloy like the gate lines 22, 24, 26, 28, but the same as in the first embodiment. It is formed of a double film including a lower film 601 made of chromium or molybdenum or molybdenum alloy or tantalum or titanium and a top film 602 made of aluminum or aluminum alloy.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

In addition, most of the semiconductor patterns 42 and 48 are the same as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. It is in shape. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor. In the same manner as in the first embodiment, the source and drain electrodes 65 and 66 and the data pad 68 are lower than the boundary between the source and drain electrodes 65 and 66 and the data pad 68. The lower part of the conductor pattern 64 for capacitors also extends out of the boundary of the conductor pattern 64 for some storage capacitors.

A protective film 70 made of silicon nitride is formed on the data lines 62, 64, 65, 66, and 68.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 68, and the conductive pattern 64 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24. In this case, all of the contact holes 72, 74, 76, and 78 are formed with the conductive pattern 64 for the storage capacitor, the gate pad 24, the drain electrode 66, and the sidewalls of the data pad 68, in particular, each of the IZO and The lower layers 201 and 601 having low contact resistance are formed to be exposed, and the contact holes 72 are positioned outside the boundaries of the conductive capacitor 64 for the storage capacitor, the drain electrode 66 and the data pad 68. The boundary lines 76 and 78 are positioned on the semiconductor patterns 42 and 48.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional. Here too, at the contacts, the IZO films 82, 86 and 88 have low contact resistance with the conductor patterns 64 for the storage capacitor, the gate pads 24 and the drain electrodes 66 and the sidewalls of the data pads 68, in particular with the IZO. The branches are in contact with the underlayers 201 and 601.

Although the transparent IZO is mentioned as an example of the material of the pixel electrode 82, it may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 7 to 9 using four masks will be described in detail with reference to FIGS. 7 to 9 and 10A to 16C. .

First, as shown in FIGS. 10A to 10C, 2 at% of the lower layer 201 made of molybdenum, molybdenum alloy, chromium, etc. having a lower contact resistance with IZO than aluminum, and aluminum or aluminum alloy having low resistance, After stacking the upper layer 202 by sputtering using a target of Al-Nd alloy including Nd, the gate line 22 and the gate on the substrate 10 by a photolithography process using one mask. The gate wiring including the pad 24, the gate electrode 26, and the sustain electrode 28 is formed in a tapered structure. Here, it is preferable that the lower layer 201 is prevented from being cut under the upper layer 202 or the lower layer comes out of the upper layer so that the IZO layer and the lower layer 201 formed thereafter are sufficiently in contact with each other. . To this end, when the lower layer 201 is formed of molybdenum or molybdenum alloy, the ratio of the thicknesses of the lower layer 201 and the upper layer 202 is 1: 5 or more, and the entire substrate is immersed in an etchant to perform etching. Etching is performed in DIP mode to optimize cell response to prevent under film from being cut. In addition, when the lower layer 201 is formed of chromium, a portion of the upper layer 202 of aluminum or an aluminum alloy may be removed in the process of laminating the lower layer 201 to a thickness of 500 GPa or less and removing the photosensitive layer. Conditions are applied to form the lower layer 201 of chromium out of the upper layer 202.

Next, as shown in FIGS. 11A and 11B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. A conductor layer including a top film 601 made of aluminum or an aluminum alloy having a low resistance and a bottom film 601 made of chromium or molybdenum or molybdenum alloy. 60) is deposited to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then the photosensitive film 110 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 12B and 12C. At this time, between the source electrode 65 and the drain electrode 66 among the photosensitive film patterns 112 and 114, and the circumference of the source and drain electrodes 65 and 66, the conductor pattern 64 for the storage capacitor, and the data pad 68. The first portion 114 located at the portion corresponding to the thickness is smaller than the data wiring portion A, that is, the second portion 112 positioned at the portion where the data lines 62, 64, 65, 66, and 68 are to be formed. The photosensitive film of the other part (B) is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the portion C and the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process, which will be described later. It is preferable to make the thickness of 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good to be 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. At this time, the data line and the layers below it remain in the data wiring portion A, only the semiconductor layer should remain in the portion C, and the upper three layers 60, 50, and 40 are in the remaining portion B. All must be removed to reveal the gate insulating film 30.

First, as shown in FIGS. 13A and 13B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 includes one of Mo or MoW alloy, Al or Al alloy, and Ta, any of dry etching and wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 13A and 13B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor, are shown. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 14A and 14B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

In this case, as shown in FIGS. 14A and 14B, the photosensitive film pattern 114 of the C portion is removed to expose the conductor pattern 67 for the source / drain, and the intermediate layer 50 and the semiconductor layer ( 40 is removed to expose the lower gate insulating film 30. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 15A and 15B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57, and the source / drain conductor pattern 67 may be wet-etched and the intermediate layer pattern ( 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in the " For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 thereunder, and the source electrode. The semiconductor patterns 43 and 48 are exposed between the 65 and the drain electrode 66 and around them, and the conductive pattern 64 for the storage capacitor and the circumference of the data pad 68.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66 and 68 are formed in this manner, as shown in FIGS. 16A and 16B, silicon nitride is deposited in the range of 250 to 400 DEG C by the CVD method as shown in the first embodiment. An organic insulating material is coated to form the protective film 70. The protective layer 70 is etched together with the gate insulating layer 30 by using a third mask to form a lower layer of the drain electrode 66, the gate pad 24, the data pad 68, and the conductive pattern 64 for the storage capacitor. Contact holes 76, 74, 78, and 72 are formed to expose 201 and 601, respectively. Again, as in the first embodiment, the boundary lines of the contact holes 76, 78, 72 exposing the drain electrode 66, the data pad 68, and the conductive capacitor pattern 64 for the storage capacitor are formed in the semiconductor pattern 42 ,. The semiconductor patterns 42 and 48 are used as the etch stop layer when forming the contact holes 76, 72, and 78 so as to be positioned above the 48.

Finally, as shown in FIGS. 7 to 8, the IZO layer having a thickness of 400 kHz to 500 kHz is deposited by a sputtering method and etched using a fourth mask to etch the drain electrode 66 in the same manner as in the first embodiment. And a pixel electrode 82 connected to the conductive capacitor 64 for the storage capacitor, an auxiliary gate pad 86 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68. The etchant for patterning IZO uses chromium etchant which is used to etch the metal film of chromium (Cr), which does not corrode aluminum and thus prevents corrosion of data wiring or gate wiring, and the etching solution (HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O), and the like.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

As described above, according to the present invention, the wiring at the contact portion contacts the IZO film and the conductive film having low contact resistance and the IZO film, so that the contact resistance can be minimized at the contact portion, thereby ensuring the reliability of the contact portion. By extending and using the semiconductor layer as an etch stop layer in the contact portion, the undercut can be removed from the contact portion to form a smooth profile of the contact portion. In addition, by forming a wiring including a conductive film containing low resistance aluminum or an aluminum alloy, the characteristics of a large screen high definition product can be improved. In addition, the manufacturing process may be simplified to manufacture a thin film transistor substrate for a liquid crystal display, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Claims (7)

A gate wiring formed on an insulating substrate, the gate wiring including a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line to receive a scan signal from the outside and to transfer the scan signal to the gate line; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed on the gate insulating layer or the semiconductor layer and intersecting the gate line, a source electrode connected to the data line, and a drain electrode separated from the source electrode and facing the source electrode around the gate electrode; And a data line connected to the data line and including a data pad receiving an image signal from the outside and transferring the image signal to the data line. A protective film covering the semiconductor layer, A pixel electrode electrically connected to the drain electrode In the thin film transistor substrate for a liquid crystal display device comprising: A portion of the semiconductor layer except for the channel portion between the source and drain electrodes extends at least outside the boundary between the drain electrode and the data pad. In claim 1, The passivation layer has a contact hole that exposes the data pad, the drain electrode, or the gate pad, and a boundary line of the data pad, the drain electrode, or the gate pad is exposed through the contact hole. In claim 2, And a boundary line of the contact hole exposing the drain electrode or the data pad is disposed above the semiconductor layer extending out of the boundary line of the drain electrode and the data pad. In claim 3, The gate wiring or the data wiring is a thin film transistor substrate comprising a lower film of chromium or molybdenum or molybdenum alloy and an upper film of aluminum or aluminum alloy. In claim 4, And an auxiliary data pad or an auxiliary data pad formed on the same layer as the pixel electrode and in contact with at least the gate pad or the lower layer of the data pad through the contact hole. . In claim 3, The passivation layer is a thin film transistor substrate made of silicon nitride or an organic insulating material. In claim 3, The pixel electrode is a thin film transistor substrate made of IZO.