KR20030050357A - 비씨디(bcd) 소자의 제조방법 - Google Patents
비씨디(bcd) 소자의 제조방법 Download PDFInfo
- Publication number
- KR20030050357A KR20030050357A KR1020010080778A KR20010080778A KR20030050357A KR 20030050357 A KR20030050357 A KR 20030050357A KR 1020010080778 A KR1020010080778 A KR 1020010080778A KR 20010080778 A KR20010080778 A KR 20010080778A KR 20030050357 A KR20030050357 A KR 20030050357A
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- semiconductor substrate
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 29
- 150000002500 ions Chemical class 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 18
- 238000005530 etching Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (4)
- 반도체 기판에 출력 드라이버용 고내압 LDPMOS와 LDNMOS 및 LV-PSA, 초고속 아날로그/디지털용 HV-PNP와 HV-NPN, 수 암페어급 VDMOS, 저전압 LVNMOS와 LVPMOS, 중전압 HV-NMOS와 HVPMOS 및 ZENER로 이루어진 BCD 소자의 제조방법에 있어서,상기 반도체 기판 표면내의 HV-PNP/HV-NPN/LV-PSA/LV-PMOS/VDMOS/HV-PMOS 영역에 제 1 매몰층을 형성하는 단계;상기 제 1 매몰층이 형성된 LV-PSA 및 HV-PMOS에 서로 다른 도전형을 갖는 제 2 매몰층 및 제 3 매몰층을 형성하는 단계;상기 반도체 기판에 딥콜렉트 영역을 정의한 후 불순물 이온을 주입하여 제 1 딥콜렉트 영역을 형성하는 단계;상기 반도체 기판의 전면에 에피텍셜층을 성장하는 단계;상기 LDNMOS 및 LDPMOS에 n-웰 영역과 n-드리프트 영역을 형성하는 단계;상기 HV-PNP, LV-NMOS, LDNMOS, VDNMOS, LDPMOS, ZENER, HVNMOS, HVPMOS에 p-웰 및 p-드리프트 영역을 형성하는 단계;상기 에피택셜층을 선택적으로 제거하여 복수개의 트랜치를 형성하는 단계;상기 트랜치 내부에 절연막과 도전막을 매립하는 단계;상기 반도체 기판의 필드 영역에 필드 산화막을 형성하는 단계;상기 제 1 딥콜렉트 영역에 불순물 이온을 주입하여 제 2 딥콜렉트 영역을 형성하는 단계를 포함하여 형성함을 특징으로 하는 BCD 소자의 제조방법.
- 제 1 항에 있어서, 상기 제 1, 제 2 딥콜렉트 영역은 n형 불순물 이온을 주입하여 형성함을 특징으로 하는 BCD 소자의 제조방법.
- 제 1 항에 있어서, 상기 제 1, 제 2 매몰층은 n형 불순물 이온을 주입하여 형성함을 특징으로 하는 BCD 소자의 제조방법.
- 제 1 항에 있어서, 상기 트랜치 내부에 매립되는 절연막과 도전막은 각각 산화막과 폴리 실리콘막으로 형성하는 것을 특징으로 하는 BCD 소자의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0080778A KR100437828B1 (ko) | 2001-12-18 | 2001-12-18 | 비씨디(bcd) 소자의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0080778A KR100437828B1 (ko) | 2001-12-18 | 2001-12-18 | 비씨디(bcd) 소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030050357A true KR20030050357A (ko) | 2003-06-25 |
KR100437828B1 KR100437828B1 (ko) | 2004-06-30 |
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KR10-2001-0080778A KR100437828B1 (ko) | 2001-12-18 | 2001-12-18 | 비씨디(bcd) 소자의 제조방법 |
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KR (1) | KR100437828B1 (ko) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100602096B1 (ko) * | 2004-12-29 | 2006-07-19 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
KR100847837B1 (ko) * | 2006-12-29 | 2008-07-23 | 동부일렉트로닉스 주식회사 | 디모스 소자 및 그 제조 방법 |
CN102194818A (zh) * | 2011-04-26 | 2011-09-21 | 电子科技大学 | 一种基于p型外延层的bcd集成器件及其制造方法 |
WO2013023445A1 (zh) * | 2011-08-12 | 2013-02-21 | 上海先进半导体制造股份有限公司 | 嵌入bcd工艺的eeprom核结构及其形成方法 |
US8487383B2 (en) | 2009-12-15 | 2013-07-16 | Samsung Electronics Co., Ltd. | Flash memory device having triple well structure |
CN112968060A (zh) * | 2019-11-27 | 2021-06-15 | 上海积塔半导体有限公司 | 基于bcd工艺的全隔离ldnmos的制作方法及芯片 |
CN117955485A (zh) * | 2024-03-18 | 2024-04-30 | 粤芯半导体技术股份有限公司 | 输出接口电路、输出接口电路板及输出接口设备 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102136493B (zh) * | 2010-01-21 | 2013-02-13 | 上海华虹Nec电子有限公司 | 高压隔离型ldnmos器件及其制造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100188121B1 (ko) * | 1996-06-27 | 1999-06-01 | 김광호 | 비씨디 모스의 제조 공정 |
KR100248372B1 (ko) * | 1997-10-16 | 2000-03-15 | 정선종 | 바이폴라 시모스-디모스 전력 집적회로 소자의 제조방법 |
KR100412539B1 (ko) * | 2001-07-24 | 2003-12-31 | 한국전자통신연구원 | 비씨디 소자 및 그 제조 방법 |
US6849491B2 (en) * | 2001-09-28 | 2005-02-01 | Dalsa Semiconductor Inc. | Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices |
-
2001
- 2001-12-18 KR KR10-2001-0080778A patent/KR100437828B1/ko active IP Right Grant
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100602096B1 (ko) * | 2004-12-29 | 2006-07-19 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
US7329570B2 (en) | 2004-12-29 | 2008-02-12 | Dongbu Electronics Co., Ltd. | Method for manufacturing a semiconductor device |
KR100847837B1 (ko) * | 2006-12-29 | 2008-07-23 | 동부일렉트로닉스 주식회사 | 디모스 소자 및 그 제조 방법 |
US8487383B2 (en) | 2009-12-15 | 2013-07-16 | Samsung Electronics Co., Ltd. | Flash memory device having triple well structure |
CN102194818A (zh) * | 2011-04-26 | 2011-09-21 | 电子科技大学 | 一种基于p型外延层的bcd集成器件及其制造方法 |
WO2013023445A1 (zh) * | 2011-08-12 | 2013-02-21 | 上海先进半导体制造股份有限公司 | 嵌入bcd工艺的eeprom核结构及其形成方法 |
US9553206B2 (en) | 2011-08-12 | 2017-01-24 | Advanced Semiconductor Manufacturing Co., Ltd. | EEPROM core structure embedded into BCD process and forming method thereof |
CN112968060A (zh) * | 2019-11-27 | 2021-06-15 | 上海积塔半导体有限公司 | 基于bcd工艺的全隔离ldnmos的制作方法及芯片 |
CN117955485A (zh) * | 2024-03-18 | 2024-04-30 | 粤芯半导体技术股份有限公司 | 输出接口电路、输出接口电路板及输出接口设备 |
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Publication number | Publication date |
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KR100437828B1 (ko) | 2004-06-30 |
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