KR20030033672A - Method for forming gate electrode of semiconductor device and gate electrode thereby - Google Patents
Method for forming gate electrode of semiconductor device and gate electrode thereby Download PDFInfo
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- KR20030033672A KR20030033672A KR1020010065755A KR20010065755A KR20030033672A KR 20030033672 A KR20030033672 A KR 20030033672A KR 1020010065755 A KR1020010065755 A KR 1020010065755A KR 20010065755 A KR20010065755 A KR 20010065755A KR 20030033672 A KR20030033672 A KR 20030033672A
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 229920000642 polymer Polymers 0.000 claims abstract description 7
- 239000012495 reaction gas Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims description 23
- 239000007769 metal material Substances 0.000 claims description 18
- 229910021332 silicide Inorganic materials 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 7
- 238000007517 polishing process Methods 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 게이트전극 형성방법 및 이에 따른 게이트전극에 관한 것으로써, 보다 상세하게는 동작속도를 향상시켜 고집적화된 반도체소자에 대응할 수 있는 반도체소자의 게이트전극 형성방법 및 이에 따른 게이트전극에 관한 것이다.The present invention relates to a method for forming a gate electrode and a gate electrode according to the semiconductor device, and more particularly, to a method of forming a gate electrode of a semiconductor device and a gate electrode according to the method that can improve the operation speed to correspond to a highly integrated semiconductor device It is about.
최근에, 반도체소자의 동작속도를 향상시키기 위하여 소오스전극(Source electrode), 드레인전극(Drain electrode) 및 게이트전극(Gate electrode) 상에 코발트 실리사이드(Cobalt silicide) 및 니켈 실리사이드(Nikel silicide) 등의 금속 실리사이드(Metal silicide)를 형성함으로써 동작전압 인가시에 발생하는 저항값을 낮추고 있다.Recently, metals such as cobalt silicide and nickel silicide are formed on a source electrode, a drain electrode, and a gate electrode to improve the operation speed of a semiconductor device. By forming a silicide, the resistance value generated when the operating voltage is applied is reduced.
도1은 종래의 반도체소자의 게이트전극 형성방법 및 이에 따른 게이트전극을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a gate electrode forming method and a gate electrode according to the conventional semiconductor device.
도1을 참조하면, 종래의 반도체소자의 게이전극 형성방법은 소오스전극(12) 및 드레인전극(14)이 기형성된 반도체 기판(10) 상에 얇은 게이트 산화막(16)을 형성하고, 상기 게이트 산화막(16) 상에 게이트 금속물질을 형성한다.Referring to FIG. 1, in the conventional method of forming a gay electrode of a semiconductor device, a thin gate oxide film 16 is formed on a semiconductor substrate 10 on which source and drain electrodes 12 and 14 are formed. A gate metal material is formed on (16).
이어서, 상기 게이트 산화막 및 게이트 금속물질을 사진식각하여 소정 패턴의 게이트 산화막(16) 및 게이트전극(18)을 형성한다.Subsequently, the gate oxide film and the gate metal material are etched to form a gate oxide film 16 and a gate electrode 18 having a predetermined pattern.
다음으로, 상기 소정 패턴의 게이트 산화막(16) 및 게이트전극(18)이 형성된 반도체 기판(10) 상에 질화막 등의 절연막을 형성한후, RIE(Reactive Ion Etching)등을 통해서 게이트전극(18) 측벽에 스페이서(Spacer : 20)를 형성한다.Next, an insulating film such as a nitride film is formed on the semiconductor substrate 10 on which the gate oxide film 16 and the gate electrode 18 of the predetermined pattern are formed, and then the gate electrode 18 is formed through a reactive ion etching (RIE) or the like. Spacers 20 are formed on the sidewalls.
마지막으로, 상기 스페이서(20)가 형성된 반도체 기판(10) 상에 니켈(Ni) 및 코발트(Co) 등의 금속물질막을 형성한 다음 RTP(Rapid Thermal Process)를 수행함으로써 반도체 기판(10)의 소오스전극(12), 드레인전극(14) 및 게이트전극(18) 상에 도전성이 높은 금속 실리사이드막(22)을 형성한다.Finally, a source of the semiconductor substrate 10 by forming a metal material film such as nickel (Ni) and cobalt (Co) on the semiconductor substrate 10 on which the spacer 20 is formed and then performing a rapid thermal process (RTP). A highly conductive metal silicide film 22 is formed on the electrode 12, the drain electrode 14, and the gate electrode 18.
이후, 금속 실리사이드에 대한 식각 선택비가 뛰어난 식각액을 사용한 습식식각공정을 수행하여 스페이서(20) 측벽의 금속물질막을 제거한다.Thereafter, a wet etching process using an etchant having an excellent etching selectivity with respect to the metal silicide is performed to remove the metal material film on the sidewall of the spacer 20.
그러나, 상기 금속 실리사이드를 반도체소자에 채용하는 것은 금속 실리사이드의 재질 특성 등의 원인에 기인하여 한계에 부딪히고 있는 실정이다.However, the use of the metal silicide in the semiconductor device is facing a limit due to the material characteristics of the metal silicide and the like.
또한, 게이트전극의 폭이 넓어 동작속도가 떨어지는 문제점이 있었다.In addition, there is a problem that the operation speed is reduced because the width of the gate electrode is wide.
따라서, 반도체소자의 동작속도를 높일 수 있도록 게이트전극의 형상을 변화시키기 위한 노력이 경주되어야 할 것이다.Therefore, efforts to change the shape of the gate electrode to increase the operation speed of the semiconductor device will have to be raced.
본 발명의 목적은, 마이너스(-) 경사진 역상 구조의 게이트전극을 형성함으로써 동작속도를 향상시킬 수 있는 반도체소자의 게이트전극 형성방법 및 이에 따른 게이트전극을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a gate electrode forming method of a semiconductor device capable of improving an operation speed by forming a gate electrode having a negative (-) inclined reverse phase structure, and a gate electrode according thereto.
도1은 종래의 반도체소자의 게이트전극 형성방법 및 이에 따른 게이트전극을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a gate electrode forming method and a gate electrode according to the conventional semiconductor device.
도2a 내지 도2j는 본 발명의 일 실시예에 따른 반도체소자의 게이트전극 형성방법 및 이에 따른 게이트전극을 설명하기 위한 단면도들이다.2A through 2J are cross-sectional views illustrating a method of forming a gate electrode and a gate electrode according to an embodiment of the present invention.
도3은 본 발명의 다른 실시예에 따른 반도체소자의 게이트전극 형성방법 및 이에 따른 게이트전극을 설명하기 위한 단면도이다.3 is a cross-sectional view illustrating a gate electrode forming method and a gate electrode according to the semiconductor device according to another embodiment of the present invention.
※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing
10, 30 ; 반도체 기판 12, 32 : 소오스전극10, 30; Semiconductor substrate 12, 32: source electrode
14, 34 : 드레인전극 16, 44 : 게이트 산화막14, 34: drain electrode 16, 44: gate oxide film
18, 48 : 게이트전극 20, 50, 60 : 스페이서18, 48: gate electrode 20, 50, 60: spacer
22, 52, 62 : 금속 실리사이드막 36 : 스톱핑 산화막22, 52, 62: metal silicide film 36: stopping oxide film
38 : 질화규소막 40 : 포토레지스트 패턴38 silicon nitride film 40 photoresist pattern
42 : 질화규소막 패턴 46 : 폴리실리콘막42 silicon nitride film pattern 46 polysilicon film
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 게이트전극 형성방법은, 소오스전극 및 드레인전극이 기형성된 반도체기판 상에 스톱핑 산화막을 형성하는 단계; 상기 스톱핑 산화막 상에 절연막을 형성하는 단계; 상기 절연막상에 상기 소오스전극 및 드레이전극 사이의 상기 절연막 상부를 개방하는 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴과 반응하여 폴리머를 발생시킬 수 있는 반응가스를 이용한 건식식각공정을 수행함으로써 상부길이보다 하부길이가 짧은 절연막 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 상기 절연막 패턴의 내부를 충진하는 도전막을 형성하는 단계; 상기 절연막 패턴이 노출되도록 상기 도전막을 소정두께로 폴리싱(Polishing)하는 단계; 및 상기 절연막 패턴을 제거함으로써 마이너스(-) 경사진 역상 구조의 게이트전극을 형성하는 단계;를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate electrode of a semiconductor device, the method including: forming a stopping oxide film on a semiconductor substrate on which source and drain electrodes are formed; Forming an insulating film on the stopping oxide film; Forming a photoresist pattern on the insulating film to open an upper portion of the insulating film between the source electrode and the drain electrode; Forming an insulating layer pattern having a lower length than an upper length by performing a dry etching process using a reaction gas capable of reacting with the photoresist pattern to generate a polymer; Removing the photoresist pattern; Forming a conductive film filling the inside of the insulating film pattern; Polishing the conductive film to a predetermined thickness so that the insulating film pattern is exposed; And forming a gate electrode having a negative (-) inclined reverse phase structure by removing the insulating layer pattern.
여기서, 상기 게이트전극을 형성한 후, 상기 게이트전극 측벽에 스페이서를 형성하는 단계를 더 수행할 수 있고, 상기 스페이서가 형성된 반도체 기판 상에 금속물질을 도포한 후, RTP(Rapid Thermal Process)를 수행함으로써 상기 소오스전극, 드레이전극 및 게이트전극 상부에 금속 실리사이드막을 형성하는 단계와 상기 스페이서 측벽의 금속물질을 제거하는 단계를 더 수행할 수 있다.Here, after forming the gate electrode, a step of forming a spacer on the sidewall of the gate electrode may be further performed, and after applying a metal material on the semiconductor substrate on which the spacer is formed, a rapid thermal process (RTP) is performed. The method may further include forming a metal silicide layer on the source electrode, the drain electrode, and the gate electrode, and removing the metal material on the sidewall of the spacer.
그리고, 본 발명에 따른 다른 반도체소자의 게이트전극 형성방법은, 소오스전극 및 드레인전극이 기형성된 반도체기판 상에 스톱핑 산화막을 형성하는 단계; 상기 스톱핑 산화막 상에 절연막을 형성하는 단계; 상기 절연막 상에 상기 소오스전극 및 드레이전극 사이의 상기 절연막 상부를 개방하는 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴과 반응하여 폴리머를 발생시킬 수 있는 반응가스를 이용한 건식식각공정을 수행함으로써 상부길이보다 하부길이가 짧은 절연막 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 상기 절연막 패턴의 내부를 충진하는 도전막을 형성하는 단계; 상기 절연막 패턴이 노출되도록 상기 도전막을 소정두께로 폴리싱(Polishing)하는 단계; 및 상기 도전막이 소정두께로 폴리싱된 상기 반도체 기판에 대해서 마스크를 사용하여 상기 절연막 패턴을 건식식각하여 스페이서 및 마이너스(-) 경사진 역상 구조의 게이트전극을 동시에 형성하는 단계;를 포함하여 이루어지는 것을 특징으로 한다.In addition, a method of forming a gate electrode of another semiconductor device according to the present invention may include forming a stopping oxide film on a semiconductor substrate on which source and drain electrodes are already formed; Forming an insulating film on the stopping oxide film; Forming a photoresist pattern on the insulating film to open an upper portion of the insulating film between the source electrode and the drain electrode; Forming an insulating layer pattern having a lower length than an upper length by performing a dry etching process using a reaction gas capable of reacting with the photoresist pattern to generate a polymer; Removing the photoresist pattern; Forming a conductive film filling the inside of the insulating film pattern; Polishing the conductive film to a predetermined thickness so that the insulating film pattern is exposed; And forming a spacer and a gate electrode having a negative (-) inclined reverse phase structure by dry etching the insulating film pattern with respect to the semiconductor substrate polished to a predetermined thickness using a mask. It is done.
여기서, 상기 스페이서가 형성된 반도체 기판 상에 금속물질을 도포한 후, RTP(Rapid Thermal Process)를 수행함으로써 상기 소오스전극, 드레인전극 및 게이트전극 상부에 금속 실리사이드막을 형성하는 단계와 상기 스페이서 측벽의 금속물질을 제거하는 단계를 더 수행할 수 있다.Here, after applying a metal material on the semiconductor substrate formed with the spacer, forming a metal silicide layer on the source electrode, drain electrode and gate electrode by performing a rapid thermal process (RTP) and the metal material of the sidewall of the spacer The step of removing may be further performed.
그리고, 본 발명에 따른 반도체소자의 게이트전극은, 소오스전극 및 드레인전극이 기형성된 반도체 기판 상에 게이트 산화막을 개재하여 마이너스(-) 경사진 역상 구조로 설치된 것을 특징으로 한다.The gate electrode of the semiconductor device according to the present invention is characterized in that the gate electrode and the drain electrode are provided in a negative (-) inclined reverse phase structure via a gate oxide film on a semiconductor substrate.
여기서, 상기 게이트전극 측벽에 스페이서가 더 구비될 수 있고, 상기 소오스전극, 드레인전극 및 게이트전극 상부에 금속 실리사이드막이 더 구비될 수 있다.Here, a spacer may be further provided on the sidewall of the gate electrode, and a metal silicide layer may be further provided on the source electrode, the drain electrode, and the gate electrode.
이하, 첨부한 도면을 참고로 하여 본 발명의 구체적인 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2a 내지 도2j는 본 발명의 일 실시예에 따른 반도체소자의 게이트 형성방법 및 이에 따른 게이트를 설명하기 위한 공정 단면도들이다.2A through 2J are cross-sectional views illustrating a method of forming a gate of a semiconductor device and a gate according to the embodiment of the present invention.
본 발명에 따른 반도체소자의 게이트 형성방법은, 먼저 도2a에 도시된 바와같이 일련의 반도체소자 제조공정의 수행에 의해서 소오스전극(32) 및 드레인전극(34)이 기형성된 반도체 기판(30) 상에 스톱핑 산화막(36)을 약 200Å의 두께로 형성한다.In the method of forming a gate of a semiconductor device according to the present invention, first, as shown in FIG. 2A, a series of semiconductor device manufacturing processes are performed on a semiconductor substrate 30 on which source and drain electrodes 34 and 34 are formed. The stopping oxide film 36 is formed to a thickness of about 200 kPa.
이때, 상기 스톱핑 산화막(36)은 산소가스를 이용한 열산화법 등을 이용하여 형성할 수 있고, 상기 스톱핑 산화막(36)은 후속 식각공정을 진행하는 과정에 식각 종말점을 검출하는 데 사용된다.In this case, the stopping oxide layer 36 may be formed using a thermal oxidation method using oxygen gas, and the stopping oxide layer 36 is used to detect an etching end point in a subsequent etching process.
다음으로, 도2b에 도시된 바와 같이 스톱핑 산화막(36) 상에 질화규소막(38) 등의 절연막을 약 2,000Å의 두께로 형성한다.Next, as shown in FIG. 2B, an insulating film such as a silicon nitride film 38 or the like is formed on the stopping oxide film 36 to a thickness of about 2,000 kPa.
이때, 상기 질화규소막(38)은 실란(SiH4)가스 및 암모니아(NH3)가스를 사용한 저압화학기상증착공정을 이용하여 형성할 수 있고, 상기 질화규소막(38)은 후속공정의 수행에 의해서 마이너스(-) 경사진 역상 구조의 게이트전극을 형성하기 위한 마스크로 사용된다.In this case, the silicon nitride film 38 may be formed using a low pressure chemical vapor deposition process using a silane (SiH 4 ) gas and an ammonia (NH 3 ) gas, and the silicon nitride film 38 may be formed by performing a subsequent process. It is used as a mask for forming a gate electrode of negative (-) inclined reverse phase structure.
계속해서, 도2c에 도시된 바와 같이 질화규소막(38)이 형성된 반도체 기판(30) 상에 소정두께의 포토레지스트를 코팅한 후, 노광 및 현상공정을 수행함으로써 소오스전극(32) 및 드레인전극(34) 사이의 질화규소막(38) 상부 소정부를 개방하는 포토레지스트 패턴(40)을 형성한다.Subsequently, as shown in FIG. 2C, the photoresist having a predetermined thickness is coated on the semiconductor substrate 30 on which the silicon nitride film 38 is formed, and then the exposure electrode and the development process are performed to perform a source electrode 32 and a drain electrode ( A photoresist pattern 40 is formed to open a predetermined portion of the upper portion of the silicon nitride film 38 therebetween.
이어서, 도2d에 도시된 바와 같이 상기 포토레지스트 패턴(40)을 마스크로 이용하여 질화규소막(38)을 건식식각함으로써 약 85°정도의 경사각도를 지니고, 상부거리(A)는 약 0.1㎛ 정도이고, 하부거리(B)는 약 0.06㎛ 정도인 질화규소막 패턴(42)을 형성한다.Subsequently, as shown in FIG. 2D, the silicon nitride film 38 is dry-etched using the photoresist pattern 40 as a mask to have an inclination angle of about 85 °, and the upper distance A is about 0.1 μm. The bottom distance B forms a silicon nitride film pattern 42 having a thickness of about 0.06 μm.
이때, 상기 약 85°정도의 경사각도를 지닌 질화규소막 패턴(42)은 삼불화질소(NF3) 등과 같은 반응가스가 포토레지스트 패턴(40)과 반응하여 다량의 폴리머(Polymer)를 연속적으로 발생시킴으로써 발생된 폴리머가 다시 마스크 역할을 수행하여 형성된 것이다. 그리고, 상기 건식식각은 스톱핑 산화막(36)이 검출될 때까지 소정시간동안 수행된다. 또한, 약 85°정도의 경사각도를 지닌 질화규소막 패턴(42)을 형성한 후, 포토레지스트 패턴(40)을 습식 또는 건식식각 방법으로 제거한다. 그리고, 상기 반도체 기판(30)이 노출되도록 스톱핑 산화막(36)을 습식 또는 건식식각 방법으로 제거한다.In this case, in the silicon nitride film pattern 42 having an inclination angle of about 85 °, a reaction gas such as nitrogen trifluoride (NF 3 ) and the like react with the photoresist pattern 40 to continuously generate a large amount of polymer. The polymer generated by forming the mask acts as a mask again. The dry etching is performed for a predetermined time until the stopping oxide film 36 is detected. In addition, after the silicon nitride film pattern 42 having an inclination angle of about 85 ° is formed, the photoresist pattern 40 is removed by a wet or dry etching method. Then, the stopping oxide layer 36 is removed by a wet or dry etching method so that the semiconductor substrate 30 is exposed.
다음으로, 도2e에 도시된 바와 같이 스톱핑 산화막(36)이 제거된 소오스전극(32) 및 드레인전극(34) 사이의 반도체 기판(30) 상에 약 15 Å정도의 두께로 얇은 게이트 산화막(44)을 형성한다.Next, as shown in FIG. 2E, a thin gate oxide film having a thickness of about 15 μs is formed on the semiconductor substrate 30 between the source electrode 32 and the drain electrode 34 from which the stop oxide film 36 is removed. 44).
이때, 상기 게이트 산화막(44)은 산소가스를 사용한 열산화법 등에 의해서 형성할 수 있고, 상기 열산화법에 의해서 게이트 산화막(44)을 형성할 때 질화규소막 패턴(42) 상부에도 소정의 산화막이 형성될 수 있으나 게이트 산화막(44)과 비교하여 질화규소막 패턴(42) 상부에 형성되는 산화막은 선택비가 약 40 ; 1로 무시할 수 있다.In this case, the gate oxide film 44 may be formed by a thermal oxidation method using oxygen gas, and when a gate oxide film 44 is formed by the thermal oxidation method, a predetermined oxide film may be formed on the silicon nitride film pattern 42. The oxide film formed on the silicon nitride film pattern 42 as compared with the gate oxide film 44 may have a selectivity of about 40; Can be ignored as 1.
계속해서, 도2f에 도시된 바와 같이 반도체 기판(30) 전면에 질화규소막 패턴(42) 내부를 충진하는 도전성의 폴리실리콘막(46)을 4,000 Å 이상의 두께로 형성한다.Subsequently, as shown in FIG. 2F, a conductive polysilicon film 46 filling the inside of the silicon nitride film pattern 42 on the entire surface of the semiconductor substrate 30 is formed to a thickness of 4,000 kPa or more.
이때, 상기 폴리실리콘막(46)은 실란(SiH4)가스를 사용한 저압화학기상증착 등의 방법으로 형성할 수 있다.In this case, the polysilicon film 46 may be formed by low pressure chemical vapor deposition using a silane (SiH 4 ) gas.
이어서, 도2g에 도시된 바와 같이 폴리실리콘막(46)이 형성된 반도체 기판(30) 상부 전면을 CMP(Chemical Mechamical Polishing) 등의 방법으로 소정두께 폴리싱(Polishing)한다.Subsequently, as illustrated in FIG. 2G, the entire upper surface of the semiconductor substrate 30 on which the polysilicon film 46 is formed is polished to a predetermined thickness by a method such as chemical mechanical polishing (CMP).
이때, 후속공정의 수행에 의해서 형성되는 스페이서 및 게이트전극 상의 폴리실리콘막 패턴(42)은 완전히 폴리싱된다.At this time, the polysilicon film pattern 42 on the spacer and the gate electrode formed by performing the subsequent process is completely polished.
다음으로, 도2h에 도시된 바와 같이 습식식각을 통해서 반도체기판(30) 상의 질화규소막 패턴(42)을 제거하여 마이너스(-) 경사 기울기를 가지는 역상 구조의 게이트전극(48)을 형성한다.Next, as shown in FIG. 2H, the silicon nitride film pattern 42 on the semiconductor substrate 30 is removed by wet etching to form a gate electrode 48 having a reverse phase structure having a negative inclination slope.
이때, 상기 게이트전극(48)은 마이너스(-) 경사 기울기를 가지는 역상 구조로 이루어져 게이트전극 하부폭은 축소시키고 상부폭은 기존대로 유지함으로써 채널의 폭을 축소시켜 반도체소자의 동작속도를 향상시킬 수 있다.At this time, the gate electrode 48 has a reverse phase structure having a negative (-) inclination inclination, thereby reducing the width of the lower portion of the gate electrode and keeping the upper width as it is, thereby reducing the width of the channel, thereby improving the operation speed of the semiconductor device. have.
특히, 상기 게이트전극(48)의 하부폭은 약 0.06㎛로써 현재의 사진공정으로는 구현하기 어려운 실정이다.In particular, the lower width of the gate electrode 48 is about 0.06㎛, which is difficult to implement in the current photographic process.
이어서, 도2i에 도시된 바와 같이 게이트전극(48)이 형성된 반도체 기판(30) 상에 질화막 등의 절연막을 형성한후, RIE(Reactive Ion Etching) 등을 통해서 게이트전극(48) 측벽에 스페이서(50)를 형성한다.Subsequently, an insulating film such as a nitride film is formed on the semiconductor substrate 30 on which the gate electrode 48 is formed, as shown in FIG. 50).
마지막으로, 상기 스페이서(50)가 형성된 반도체 기판(30) 상에 니켈 및 코발트 등의 금속물질막을 형성한 다음 RTP(Rapid Thermal Process)를 수행함으로써 반도체 기판(30) 상의 소오스전극(32), 드레인전극(34) 및 게이트전극(48) 상에 금속 실리사이드막(52)을 형성한다.Finally, the source electrode 32 and the drain on the semiconductor substrate 30 are formed by forming a metal material film such as nickel and cobalt on the semiconductor substrate 30 on which the spacer 50 is formed, and then performing a rapid thermal process (RTP). The metal silicide film 52 is formed on the electrode 34 and the gate electrode 48.
이후, 금속물질막에 대한 식각 선택비가 뛰어난 식각액을 사용한 습식식각공정을 수행하여 스페이서(50) 측벽의 금속물질막을 제거한다.Thereafter, a wet etching process using an etchant having an excellent etching selectivity with respect to the metal material film is performed to remove the metal material film on the sidewall of the spacer 50.
도3은 본 발명의 다른 실시이예에 따른 반도체소자의 게이트전극 형성방법 및 이에 따른 게이트전극을 설명하기 위한 단면도이다.3 is a cross-sectional view for describing a gate electrode forming method and a gate electrode according to the semiconductor device according to another embodiment of the present invention.
도3을 참조하면, 질화규소막 패턴(42) 내부를 충진하는 도전성의 폴리실리콘막(46)이 4,000 Å 이상의 두께로 형성된 반도체 기판(30) 상부 전면을 CMP(Chemical Mechamical Polishing) 등의 방법으로 소정두께 폴리싱한후, 건식식각공정을 수행함으로써 게이트전극(48) 및 스페이서(60)를 동시에 형성한다.Referring to FIG. 3, a conductive polysilicon film 46 filling the inside of the silicon nitride film pattern 42 is formed by a method such as chemical mechanical polishing (CMP) on the entire upper surface of the semiconductor substrate 30 having a thickness of 4,000 두께 or more. After polishing the thickness, the gate electrode 48 and the spacer 60 are simultaneously formed by performing a dry etching process.
이어서, 상기 게이트전극(48) 및 스페이서(60)가 형성된 반도체 기판(30) 상에 전술한 바와 같이 니켈 및 코발트 등의 금속물질막을 형성한 다음 RTP(Rapid Thermal Process)를 수행함으로써 반도체 기판(30) 상의 소오스전극(32), 드레인전극(34) 및 게이트전극(48) 상에 금속 실리사이드막(62)을 형성한다.Subsequently, a metal material film such as nickel and cobalt is formed on the semiconductor substrate 30 on which the gate electrode 48 and the spacer 60 are formed, and then a rapid thermal process (RTP) is performed to form the semiconductor substrate 30. The metal silicide film 62 is formed on the source electrode 32, the drain electrode 34, and the gate electrode 48 on the ().
이후, 금속물질막에 대한 식각 선택비가 뛰어난 식각액을 사용한 습식식각공정을 수행하여 스페이서(60) 측벽의 금속물질막을 제거한다.Thereafter, a wet etching process using an etchant having an excellent etching selectivity with respect to the metal material film is performed to remove the metal material film on the sidewall of the spacer 60.
본 발명에 의하면, 마이너스(-) 기울기를 가지는 역상 구조의 게이트전극을형성하여 게이트 산화막과 접촉하는 게이트전극 하부폭은 축소시키고 상부폭은 기존대로 유지함으로써 채널의 폭을 축소시켜 반도체소자의 동작속도를 향상시킬 수 있는 효과가 있다.According to the present invention, a gate electrode having a negative phase (−) slope is formed to reduce the width of the lower portion of the gate electrode in contact with the gate oxide layer and keep the upper width as it is, thereby reducing the width of the channel, thereby reducing the operation speed of the semiconductor device. There is an effect to improve.
그리고, 게이트전극 및 스페이서가 반도체소자 내부에 차지하는 점유면적을 축소시킬 수 있으므로 고집적화된 반도체소자의 크기를 축소시킬 수 있고, 사진공정의 마진(Margine) 확보가 유리한 효과가 있다.In addition, since the occupied area occupied by the gate electrode and the spacer in the semiconductor device can be reduced, the size of the highly integrated semiconductor device can be reduced, and securing a margin of the photo process is advantageous.
이상에서는 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술 사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical spirit of the present invention, and such modifications and modifications belong to the appended claims.
Claims (8)
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| KR1020010065755A KR20030033672A (en) | 2001-10-24 | 2001-10-24 | Method for forming gate electrode of semiconductor device and gate electrode thereby |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210102807A (en) * | 2020-02-11 | 2021-08-20 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor device and method |
| US11430865B2 (en) | 2020-01-29 | 2022-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
| US11990509B2 (en) | 2020-01-29 | 2024-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices having gate structures with slanted sidewalls |
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2001
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11430865B2 (en) | 2020-01-29 | 2022-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
| US11990509B2 (en) | 2020-01-29 | 2024-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices having gate structures with slanted sidewalls |
| KR20210102807A (en) * | 2020-02-11 | 2021-08-20 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor device and method |
| US11398384B2 (en) | 2020-02-11 | 2022-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for manufacturing a transistor gate by non-directional implantation of impurities in a gate spacer |
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