CN113497148A - Semiconductor structure and method for forming semiconductor structure - Google Patents

Semiconductor structure and method for forming semiconductor structure Download PDF

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Publication number
CN113497148A
CN113497148A CN202010270719.2A CN202010270719A CN113497148A CN 113497148 A CN113497148 A CN 113497148A CN 202010270719 A CN202010270719 A CN 202010270719A CN 113497148 A CN113497148 A CN 113497148A
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China
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opening
forming
dielectric layer
semiconductor structure
gate
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Inventor
张海洋
纪世良
崇二敏
和阿雷
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010270719.2A priority Critical patent/CN113497148A/en
Publication of CN113497148A publication Critical patent/CN113497148A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate; a dielectric layer located on the substrate; the dielectric layer is arranged between the first opening and the second opening, the first opening is arranged at the top of the second opening, and an included angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle; a gate structure located within the first opening and within the second opening. The performance of the semiconductor structure is improved.

Description

Semiconductor structure and method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of integrated circuit manufacturing technology, the feature size of the MOS transistor is smaller and smaller, and in order to reduce the parasitic capacitance of the gate of the MOS transistor and increase the device speed, a gate stack structure of a high-K (dielectric constant greater than 3.9) gate dielectric layer and a metal gate is introduced into the MOS transistor. In order to avoid the influence of the metal material of the metal gate on other structures of the transistor, the gate stack structure of the metal gate and the high-K gate dielectric layer is usually manufactured by a "gate last" process.
However, the existing gate-last process still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the existing gate-last process.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a dielectric layer located on the substrate; the dielectric layer is arranged between the first opening and the second opening, the first opening is arranged at the top of the second opening, and an included angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle; a gate structure located within the first opening and within the second opening.
Optionally, the substrate includes a base and a fin structure located on the base; the gate structure spans the fin structure.
Optionally, the depth of the second opening ranges from 100 angstroms to 200 angstroms.
Optionally, the obtuse angle ranges from 120 ° to 150 °.
Optionally, the method further includes: and the top of the side wall is positioned at the bottom of the first opening.
Optionally, the material of the sidewall spacer includes a dielectric material, and the dielectric material includes silicon nitride.
Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.
Optionally, the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal comprising tungsten.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a dummy gate structure on a substrate; forming an initial side wall on the side wall of the pseudo gate structure; forming a dielectric layer on the substrate, wherein the dielectric layer is positioned on the surface of the side wall of the initial side wall; removing part of the initial side wall to form a side wall, and forming an initial first opening positioned at the top of the side wall in the dielectric layer, wherein the initial first opening exposes part of the surface of the side wall of the dielectric layer; removing part of the side wall of the dielectric layer exposed by the initial first opening, and forming a first opening in the dielectric layer, wherein an included angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle; and after the first opening is formed, removing the dummy gate structure and forming a second opening communicated with the first opening.
Optionally, the depth of the second opening ranges from 100 angstroms to 200 angstroms.
Optionally, the obtuse angle ranges from 120 ° to 150 °.
Optionally, the substrate includes a base and a fin structure located on the base; the gate structure spans the fin structure.
Optionally, the process of removing a portion of the sidewall of the dielectric layer exposed by the initial first opening includes an isotropic dry etching process.
Optionally, the process for removing part of the initial sidewall includes a radical etching process.
Optionally, the radical etching process includes a first step and a second step: the first step comprises: performing ion activation reaction on activated ions and the initial side wall to generate a modified layer; the second step includes: and removing the modified layer by adopting a free radical reaction.
Optionally, the ions of the ion activation reaction include hydrogen ions; the free radical of the radical reaction comprises NF3、CH4、H2And radicals of a mixed gas of Ar and He.
Optionally, the material of the initial sidewall spacer includes a dielectric material, and the dielectric material includes silicon nitride.
Optionally, the method for removing the dummy gate structure includes: removing part of the dummy gate structure to form a transition structure; and removing the transition structure until the surface of the substrate is exposed, and forming the second opening.
Optionally, the process of removing part of the dummy gate structure includes a dry etching process.
Optionally, the dry etching process includes a radical plasma etching process.
Optionally, the process for removing the transition structure includes a dry etching process.
Optionally, the dry etching process includes a radical plasma etching process.
Optionally, after forming the second opening, forming a gate structure in the first opening and the second opening; the grid structure comprises a grid dielectric layer and a grid layer positioned on the grid dielectric layer; the gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal comprising tungsten.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure of the technical scheme of the invention, the included angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle, so that the top width of the first opening is greater than that of the second opening, and when a gate structure is formed in the second opening and the first opening, the material of the gate structure is easily filled to the bottom of the second opening, so that a gate structure with a compact material structure can be formed, and the performance of the semiconductor structure is further improved.
According to the forming method of the semiconductor structure, the first opening is formed in the dielectric layer, and the included angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle, so that the top width of the first opening is larger than that of the second opening, and when the grid electrode structure is formed in the second opening and the first opening in the follow-up process, the material of the grid electrode structure is easy to fill to the bottom of the second opening, the grid electrode structure with a compact material structure can be formed, and the performance of the semiconductor structure is improved.
Further, the process for removing part of the initial side wall comprises a free radical etching process, wherein the free radical etching process has a larger etching selection ratio to the side wall material silicon nitride, so that the damage to other structures of the device is smaller while the part of the initial side wall is accurately removed.
Further, the process for removing the dummy gate structure comprises a free radical plasma etching process, and the free radical plasma etching process has a large etching selection ratio on the material of the dummy gate structure, so that the damage to other structures of the device is small while the clean dummy gate structure is removed.
Drawings
Fig. 1 to 8 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, the existing gate-last process still needs to be improved.
Specifically, the gate-last process requires forming a dummy gate structure, then forming a dielectric layer, removing the dummy gate structure to form a gate opening in the dielectric layer, and finally forming a metal gate in the gate opening. As semiconductor technology nodes are further scaled down, the gate structures are also smaller and smaller in size, and the aspect ratios of the gate openings are larger and larger. When the grid structure is formed in the grid opening, the material of the grid structure is deposited in the grid opening by adopting a vapor deposition process, the depth-to-width ratio of the grid opening is larger, and the reaction gas is difficult to reach the bottom of the grid opening and preferentially deposits on the top of the grid opening, so that the formed grid structure is loose and has a cavity, and the performance of the formed semiconductor structure is influenced.
In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, wherein a first opening is formed in a dielectric layer, an included angle between a sidewall surface of the first opening and a top surface of the dielectric layer is an obtuse angle, and the first opening exposes the top of a second opening, so that the top width of the first opening is greater than the top width of the second opening, and thus when a gate structure is formed in the second opening and the first opening in the following process, a material of the gate structure is easily filled to the bottom of the second opening, and a gate structure with a compact material structure can be formed, thereby improving the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 8 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 1, a substrate is provided.
In this embodiment, the substrate includes: a substrate 100; a fin structure 101 on the substrate 100; an isolation layer (not shown) on the surface of the substrate 100 and on the sidewall surfaces of the fin structures 101, wherein the top surface of the isolation layer is lower than the top surface of the fin structures 101.
In this embodiment, the material of the substrate 100 is monocrystalline silicon; the material of the fin structure 101 includes monocrystalline silicon.
In other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon-on-insulator, or germanium-on-insulator; the fin structure may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, or germanium on insulator.
The material of the isolation layer comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbonitride. In this embodiment, the material of the isolation layer includes silicon oxide.
In other embodiments, the substrate is a planar substrate.
Referring to fig. 2, a dummy gate structure 102 is formed on the substrate, and the dummy gate structure crosses over the fin structure 101.
The dummy gate structure 102 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) on the dummy gate dielectric layer.
The forming method of the dummy gate structure 102 comprises the following steps: forming a dummy gate dielectric material layer (not shown) on the substrate; forming a dummy gate material layer (not shown) on the dummy gate dielectric material layer; forming a patterned mask layer (not shown) on the dummy gate material layer; and etching the pseudo gate material layer and the pseudo gate dielectric material layer by taking the patterned mask layer as a mask until the surface of the substrate is exposed to form the pseudo gate structure 102.
The material of the pseudo gate dielectric layer comprises silicon oxide or low-K (K is less than 3.9) material; the material of the dummy gate layer comprises polysilicon.
With continued reference to fig. 2, initial spacers 103 are formed on the sidewalls of the dummy gate structure 102.
The forming method of the initial side wall 103 comprises the following steps: forming a side wall material layer (not shown) on the surface of the substrate, the top surface and the side wall surface of the dummy gate structure 102; and etching back the side wall material layer until the surface of the substrate is exposed, and forming an initial side wall 103 on the side wall of the pseudo gate structure 102.
The material of the initial sidewall spacers 103 comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the material of the initial sidewall spacers 103 includes silicon nitride.
With reference to fig. 2, a dielectric layer 104 is formed on the substrate, the dielectric layer 104 is located on the sidewall surface of the initial sidewall spacer 103, and the top surface of the dummy gate structure 102 and the top surface of the initial sidewall spacer 103 are exposed on the surface of the dielectric layer 104.
The forming method of the dielectric layer 104 comprises the following steps: forming a dielectric material layer (not shown) on the substrate, the top surface of the dummy gate structure 102 and the sidewalls of the initial sidewall spacers 103; and flattening the dielectric material layer until the top surface of the dummy gate structure 102 is exposed to form the dielectric layer 104.
The material of the dielectric layer 104 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride. The process for forming the dielectric material layer comprises a chemical vapor deposition process, a heat treatment process or an atomic layer deposition process.
In this embodiment, the material of the dielectric layer 104 includes silicon oxide; the process of forming the dielectric material layer includes a chemical vapor deposition process.
Next, removing a portion of the initial sidewall spacers 103 to form sidewall spacers, and forming an initial first opening in the dielectric layer 104, where the initial first opening exposes a portion of the sidewall surface of the dielectric layer 104.
In the present embodiment, the process of removing a portion of the initial sidewall spacers 103 includes a radical etching process.
The radical etching process comprises a first step and a second step, wherein the first step comprises the following steps: performing an ion activation reaction on the activated ions and the initial side wall 103 to generate a modified layer; the second step includes: and removing the modified layer by adopting a free radical reaction. Please refer to fig. 3 and fig. 4 for a specific process of the first step and the second step.
In other embodiments, the process of removing the part of the initial sidewall spacer includes one or more of a dry etching process and a wet etching process.
Referring to fig. 3, activated ions are used to perform an ion activation reaction with a portion of the initial sidewall 103 to form a modified layer 105.
The ions of the ion activation reaction include hydrogen ions.
The hydrogen ions react with the silicon nitride to generate a modified layer 105, and the modified layer 105 can be sufficiently removed in subsequent free radical reactions, and meanwhile, the damage to other structures of the device is small.
Referring to fig. 4, the modification layer 105 is removed by a radical reaction to form a sidewall spacer 106, and an initial first opening 107 located at the top of the sidewall spacer 106 is formed in the dielectric layer 104, where the initial first opening 107 exposes a portion of the sidewall surface of the dielectric layer 104.
The free radical of the radical reaction comprises NF3、CH4、H2And radicals of a mixed gas of Ar and He.
The radical etching process has a large etching selection ratio to the silicon nitride material of the initial side wall 103, so that the damage to other structures of the device is small while a part of the initial side wall 103 is accurately removed.
Referring to fig. 5, a portion of the sidewall of the dielectric layer 104 exposed by the initial first opening 107 is removed, a first opening 108 is formed in the dielectric layer 104, a top dimension of the first opening 108 is greater than a bottom dimension, and an included angle between a sidewall surface of the first opening 108 and a top surface of the dielectric layer 104 is an obtuse angle.
The process of removing the sidewalls of the dielectric layer 104 exposed by the initial first opening 107 may include one or more of an isotropic dry etching process and a wet etching process.
In this embodiment, the process of removing the sidewall of the dielectric layer 104 exposed by a portion of the initial first opening 107 includes an isotropic dry etching process; the reaction gas of the isotropic dry etching process comprises CF4、CHF3、CH2F2And O2The mixed gas has a larger etching selectivity ratio to the material of the dielectric layer 104, so that the first opening 108 in the angle range can be formed, and the damage to other structures of the device is smaller.
The obtuse angle ranges from 120 degrees to 150 degrees.
The sidewall surface of the first opening 108 with the angle range enables the material of the gate structure to be easily filled to the bottom of the second opening when the gate structure is formed in the second opening and the first opening 108, so that the gate structure with a dense material structure can be formed. If the angle is too small, namely less than 120 degrees, the filling effect of the gate structure material cannot be greatly improved; if the angle is too large, i.e., greater than 150 °, the reliability of the semiconductor structure may be affected if the dimensions of the gate structure within the first opening 108 and the dimensions within the second opening after the subsequent formation of the gate structure are different.
Next, after forming the first opening 108, the dummy gate structure 102 is removed to form a second opening, and the first opening exposes the top of the second opening.
In this embodiment, a portion of the dummy gate structure 102 is removed to form a transition structure; and removing the transition structure to form the second opening. Please refer to fig. 6 and 7 for a specific process of forming the second opening.
Referring to fig. 6, a portion of the dummy gate structure 102 is removed to form a transition structure 109.
The process of removing a portion of the dummy gate structure 102 includes a dry etching process including a radical plasma etching process.
In this embodiment, the process of removing a portion of the dummy gate structure 102 includes a radical plasma etching process. The free radicals of the free radical plasma etching process comprise: containing NF3、H2、NH3And Ar.
The radical plasma etching process has a large etching selection ratio on the material of the dummy gate structure 102, so that the damage on other structures of the device is small while the dummy gate structure 102 is removed.
Referring to fig. 7, the transition structure 109 is removed until the substrate surface is exposed, forming a second opening 110.
The method for removing the transition structure 109 includes one or more of a wet etching process and a dry etching process.
In this embodiment, the process of removing the transition structure 109 includes a dry etching process, and the dry etching process includes a radical plasma etching process.
The second opening 110 has a depth ranging from 100 to 200 angstroms.
The second opening 110 in the depth range prevents the depth of the second opening 110 from being too small, namely less than 100 angstroms, so that the fin structure 101 is damaged by the etching process when the dummy gate structure is removed; meanwhile, the situation that the depth of the second opening 110 is too large, so that the dummy gate structure is not easy to remove is avoided.
In other embodiments, the dummy gate structure can be removed at one time to form the second opening.
In other embodiments, the process of removing the dummy gate structure includes a dry etching process including a radical plasma etching process.
Referring to fig. 8, a gate structure 111 is formed in the first opening 108 and the second opening 110.
The gate structure 111 includes a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
In this embodiment, the gate structure 111 further includes a work function layer (not shown) on the gate dielectric layer, and the gate layer is located on the surface of the work function layer.
The method for forming the gate structure 111 comprises the following steps: forming a gate dielectric material layer (not shown) on the surface of the dielectric layer 104, the inner wall surface of the first opening 108 and the inner wall surface of the second opening 110; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate material layer (not shown) on the surface of the work function material layer; and flattening the gate material layer, the work function material layer and the gate dielectric material layer until the surface of the dielectric layer 104 is exposed, and forming a gate structure 111 in the first opening 108 and the second opening 110.
The gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal, and the metal comprises tungsten; the material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.
The process for forming the gate dielectric material layer comprises an atomic layer deposition process, a chemical vapor deposition process or a heat treatment process; the process for forming the work function material layer comprises an atomic layer deposition process, a chemical vapor deposition process or a heat treatment process; the process for forming the gate material layer comprises a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the process of forming the gate dielectric material layer includes an atomic layer deposition process; the process of forming the work function material layer comprises an atomic layer deposition process; the process of forming the gate material layer includes a physical vapor deposition process.
Because the top dimension of the first opening 108 is greater than the bottom dimension, and the included angle between the sidewall surface of the first opening 108 and the top surface of the dielectric layer 104 is an obtuse angle, the top width of the first opening 108 is greater than the top width of the second opening 110, so that when the gate structure 111 is formed in the second opening 110 and the first opening 108 in the following process, the material of the gate structure 111 is easily filled to the bottom of the second opening 110, the gate structure 111 with a dense material structure can be formed, and the performance of the semiconductor structure is further improved.
In other embodiments, the gate structure is located within the second opening.
The forming method of the gate structure comprises the following steps: forming an initial gate structure in the first opening and the second opening; and flattening the dielectric layer, the first region of the side wall and the initial grid structure until the top surface of the second region of the side wall is exposed, and forming a grid structure in the second opening.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 8, which includes:
a substrate;
a dielectric layer 104 on the substrate;
a first opening (not shown) and a second opening (not shown) in the dielectric layer 104, wherein the first opening is located at the top of the second opening, the top dimension of the first opening is larger than the bottom dimension, and an included angle between the sidewall surface of the first opening and the top surface of the dielectric layer 104 is an obtuse angle;
a gate structure 111 located within the first opening and within the second opening.
In this embodiment, the substrate includes a base 100 and a fin structure 101 located on the base 100; the gate structure 111 crosses the fin structure 101.
In the present embodiment, the obtuse angle ranges from 120 ° to 150 °.
In this embodiment, the method further includes: and the side wall 106 is positioned on the side wall of the second opening, and the top of the side wall 106 is positioned at the bottom of the first opening.
In this embodiment, the material of the sidewall spacers 106 includes a dielectric material, and the dielectric material includes silicon nitride.
In the present embodiment, the gate structure 111 includes a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
In this embodiment, the material of the gate dielectric layer includes a high-dielectric-constant material, the dielectric constant of the high-dielectric-constant material is greater than 3.9, and the high-dielectric-constant material includes aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal comprising tungsten.
In the semiconductor structure, the top dimension of the first opening is greater than the bottom dimension, and the included angle between the side wall surface of the first opening and the top surface of the dielectric layer 104 is an obtuse angle, so that the top width of the first opening is greater than the top width of the second opening, and when the gate structure 111 is formed in the second opening and the first opening, the material of the gate structure 111 is easily filled to the bottom of the second opening, so that the gate structure 111 with a compact material structure can be formed, and the performance of the semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (23)

1. A semiconductor structure, comprising:
a substrate;
a dielectric layer located on the substrate;
the dielectric layer is arranged between the first opening and the second opening, the first opening is arranged at the top of the second opening, and an included angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle;
a gate structure located within the first opening and within the second opening.
2. The semiconductor structure of claim 1, wherein the substrate comprises a base and a fin structure on the base; the gate structure spans the fin structure.
3. The semiconductor structure of claim 1, wherein a depth of the second opening ranges from 100 angstroms to 200 angstroms.
4. The semiconductor structure of claim 1, wherein the obtuse angle ranges from 120 ° to 150 °.
5. The semiconductor structure of claim 1, further comprising: and the top of the side wall is positioned at the bottom of the first opening.
6. The semiconductor structure of claim 5, wherein the material of the sidewall spacers comprises a dielectric material comprising silicon nitride.
7. The semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate layer located over the gate dielectric layer.
8. The semiconductor structure of claim 7, wherein the material of the gate dielectric layer comprises a high dielectric constant material having a dielectric constant greater than 3.9, the high dielectric constant material comprising aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal comprising tungsten.
9. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a dummy gate structure on a substrate;
forming an initial side wall on the side wall of the pseudo gate structure;
forming a dielectric layer on the substrate, wherein the dielectric layer is positioned on the surface of the side wall of the initial side wall;
removing part of the initial side wall to form a side wall, and forming an initial first opening at the top of the side wall, wherein part of the surface of the side wall of the dielectric layer is exposed by the initial first opening;
removing part of the side wall of the dielectric layer exposed by the initial first opening, and forming a first opening in the dielectric layer, wherein an included angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle;
and removing the dummy gate structure to form a second opening communicated with the first opening.
10. The method of forming a semiconductor structure of claim 9, wherein a depth of the second opening ranges from 100 angstroms to 200 angstroms.
11. The method of claim 9, wherein the obtuse angle ranges from 120 ° to 150 °.
12. The method of claim 9, wherein the substrate comprises a base and a fin structure on the base; the gate structure spans the fin structure.
13. The method of claim 9, wherein the step of removing the exposed sidewalls of the dielectric layer from the initial first opening comprises an isotropic dry etching process.
14. The method of claim 9, wherein the process of removing a portion of the initial sidewall spacers comprises a radical etch process.
15. The method of forming a semiconductor structure of claim 14, wherein the radical etch process comprises a first step and a second step: the first step comprises: performing ion activation reaction on activated ions and the initial side wall to generate a modified layer; the second step includes: and removing the modified layer by adopting a free radical reaction.
16. The method of forming a semiconductor structure of claim 15, wherein ions of the ion activation reaction comprise hydrogen ions; the radical of the radical reaction includes a radical containing a mixed gas of NF3, CH4, H2, Ar and He.
17. The method for forming a semiconductor structure according to claim 16, wherein the material of the initial sidewall spacers comprises a dielectric material, and the dielectric material comprises silicon nitride.
18. The method of forming a semiconductor structure of claim 9, wherein removing the dummy gate structure comprises: removing part of the dummy gate structure to form a transition structure; and removing the transition structure until the surface of the substrate is exposed, and forming the second opening.
19. The method of forming a semiconductor structure of claim 18, wherein the process of removing a portion of the dummy gate structure comprises a dry etch process.
20. The method of forming a semiconductor structure of claim 19, wherein the dry etching process comprises a radical plasma etching process.
21. The method of forming a semiconductor structure of claim 18, wherein the process of removing the transition structure comprises a dry etching process.
22. The method of forming a semiconductor structure of claim 21, wherein the dry etching process comprises a radical plasma etching process.
23. The method of forming a semiconductor structure of claim 9, wherein after forming the second opening, a gate structure is formed within the first opening and within the second opening; the grid structure comprises a grid dielectric layer and a grid layer positioned on the grid dielectric layer; the gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal comprising tungsten.
CN202010270719.2A 2020-04-08 2020-04-08 Semiconductor structure and method for forming semiconductor structure Pending CN113497148A (en)

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