KR20030002357A - Method For Forming The Transitor Of Semiconductor Device - Google Patents

Method For Forming The Transitor Of Semiconductor Device Download PDF

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KR20030002357A
KR20030002357A KR1020010037925A KR20010037925A KR20030002357A KR 20030002357 A KR20030002357 A KR 20030002357A KR 1020010037925 A KR1020010037925 A KR 1020010037925A KR 20010037925 A KR20010037925 A KR 20010037925A KR 20030002357 A KR20030002357 A KR 20030002357A
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spacer
film
region
layer
cell
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KR100400250B1 (en
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김대영
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A method for fabricating a transistor of a semiconductor device is provided to minimize an attack of an active region of a semiconductor substrate and form a transistor in a peripheral circuit area while a poly plug is formed in a cell area when a cell area is opened. CONSTITUTION: A gate oxide layer(12), a polysilicon layer(14), a tungsten layer(16) and a silicon nitride layer(18) are stacked on the substrate(10). Gates are formed in the cell and peripheral areas. After a sealing nitride layer(20) is formed, the first spacer nitride layer(22) is deposited. The second spacer nitride layer(24) and the first spacer oxide layer(26) are stacked. A PMOS region in the peripheral area except the cell portion is blanket-etched to form a wordline spacer. An NMOS region in the peripheral area except the cell portion is blanket-etched to form a spacer. The first insulation layer(30) and the first spacer oxide layer in the cell area are removed. After the first photoresist layer is removed, a blanket etch process is performed to leave the first and second spacer nitride layers in the cell area and the first insulation layer in the peripheral area. The second insulation layer(34) is deposited. The second photoresist layer(36) is stacked to isolate the peripheral area so that the second insulation layer and the first and second spacer nitride layers in the cell area are removed to open the active region. The second photoresist layer is removed and a polysilicon layer for a plug is formed.

Description

반도체장치의 트랜지스터 형성방법 { Method For Forming The Transitor Of Semiconductor Device }Method for Forming The Transitor Of Semiconductor Device

본 발명은 트랜지스터 제조방법에 관한 것으로, 특히, 반도체장치에서 셀영역을 개방할 때, 반도체기판의 활성영역의 어택(Attack)을 최소화하고, 셀영역의 폴리플러그를 형성하면서 주변회로영역의 트랜지스터를 형성하며, 자기정렬콘택의 콘택을 셀영역에서 형성할 때, 식각장벽물질의 손실을 최소화하도록 하는 반도체장치의 트랜지스터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor, and more particularly, when opening a cell region in a semiconductor device, minimizing the attack of the active region of the semiconductor substrate and forming a poly plug of the cell region, thereby forming a transistor in the peripheral circuit region. The present invention relates to a method of forming a transistor in a semiconductor device to minimize loss of an etch barrier material when forming a contact of a self-aligned contact in a cell region.

일반적으로, 반도체장치의 종류에는 여러 가지가 있으며, 이 반도체장치 내에 형성되는 트랜지스터 및 커패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며, 최근에는 반도체기판 상에 산화막을 입혀 전계효과를 내도록 하는 모스형 전계효과 트랜지스터(MOS FET; metal oxide semiconductor field effect transistor)를 점차적으로 많이 사용하고 있는 실정에 있다.In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, etc. formed in the semiconductor device, and in recent years, MOS is formed to apply an oxide film on a semiconductor substrate to produce an electric field effect. Background Art [0002] Metal oxide semiconductor field effect transistors (MOS FETs) are increasingly being used.

상기한 모스형 전계효과 트랜지스터는 반도체 기판상에 형성된 게이트가 반도체층에서 얇은 산화 실리콘막에 의해 격리되어 있는 전계효과 트랜지스터로 접합형과 같이 임피던스가 저하되는 일이 없으며, 확산 공정이 1회로 간단하고, 소자간의 분리가 필요 없는 장점을 지니고 있어서, 고밀도 집적화에 적합한 특성을 지니고 있는 반도체 장치이다.The MOS type field effect transistor is a field effect transistor in which a gate formed on a semiconductor substrate is isolated by a thin silicon oxide film in a semiconductor layer, and the impedance is not lowered like a junction type, and the diffusion process is simple. The semiconductor device is advantageous in that it does not require separation between devices, and is suitable for high density integration.

상기 트랜지스터는 셀영역과 주변회로영역으로 구분되어져서 트랜지스터를 각각 형성하도록 하는 공정을 적용하는 것으로서, 트랜지스터를 제조하는 방법을 살펴 보면, 반도체기판 상에 게이트산화막 및 도전역할을 하는 폴리실리콘층 혹은텅스텐실리사이드층등을 적층하고, 그 위에 재차 반사방지막을 적층한다.The transistor is divided into a cell region and a peripheral circuit region to apply a process of forming a transistor, respectively. Referring to the method of manufacturing a transistor, a polysilicon layer or tungsten that serves as a gate oxide film and a conductive layer on a semiconductor substrate is described. A silicide layer and the like are laminated, and an antireflection film is again stacked thereon.

이와같은 상태에서 상기 결과물 상에 감광막을 적층한 후, 셀영역은 차단하고 주변회로영역을 선택적으로 개방시키도록 한 후 식각공정으로 게이트를 형성하도록 한다.In such a state, after the photoresist layer is deposited on the resultant, the cell region is blocked and the peripheral circuit region is selectively opened, and then a gate is formed by an etching process.

그리고, 상기 주변회로영역에 게이트를 형성한 후에 셀영겨에 잔류된 감광막을 제거한 후, 재차 다른 감광막을 적층하여서 주변회로영역을 개방하여서 식각으로 게이트를 형성하도록 한다.After the gate is formed in the peripheral circuit region, the photoresist film remaining in the cell flakes is removed, and another photosensitive film is stacked again to open the peripheral circuit region to form the gate by etching.

그리고, 상기 게이트에 절연막을 적층하여서 각각 스페이서막을 형성하도록 한다.An insulating film is stacked on the gate to form a spacer film, respectively.

그런데, 종래에는 셀영역의 활성역역을 2회에 걸쳐서 개방하여야 하므로 반도체기판이 심하게 손상되어서 리프레쉬(Refresh) 특성의 악화를 초래하고, 또한 워드라인의 식각장벽물질의 손실이 심화되어지며, 게이트와 상하부배선층과 서로 연결하기 위하여 콘택홀을 형성하기 위한 자기정렬콘택 공정에서 컨택홀이 정확하게 형성되지 않으므로 브릿지(Bridge)가 유발되는 등의 문제점을 지닌다.However, since the active region of the cell region has to be opened twice, the semiconductor substrate is severely damaged, resulting in a deterioration of the refresh characteristics, and the loss of the etch barrier material of the word line is intensified. Since the contact holes are not accurately formed in the self-aligned contact process for forming the contact holes in order to connect with the upper and lower wiring layers, bridges are caused.

즉, 상기 문제점을 해결하면서도 반도체소자의 특성을 유지하는 것이 매우 어려운 공정이었으며, 수율 역시 저하되는 단점을 지닌다.That is, it was a very difficult process to maintain the characteristics of the semiconductor device while solving the above problems, and also has the disadvantage that the yield is also reduced.

본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체장치에서 셀영역을 개방할 때, 반도체기판의 활성영역의 어택을 최소화하고, 셀영역의 폴리플러그를형성하면서 주변회로영역의 트랜지스터를 형성하며, 자기정렬콘택의 콘택을 셀영역에서 형성할 때, 식각장벽물질의 손실을 최소화하도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and when opening a cell region in a semiconductor device, it minimizes the attack of the active region of the semiconductor substrate, forms a polyplug of the cell region, and forms transistors in the peripheral circuit region. The purpose is to minimize the loss of etch barrier material when forming contacts of self-aligned contacts in the cell region.

도 1 내지 도 8은 본 발명의 일실시예에 따른 트랜지스터의 형성방법을 순차적을 보인 도면이다.1 to 8 are diagrams sequentially illustrating a method of forming a transistor according to an embodiment of the present invention.

-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing

10 : 반도체기판 12 : 게이트산화막10 semiconductor substrate 12 gate oxide film

14 : 폴리실리콘막 16 : 텅스텐막14 polysilicon film 16 tungsten film

18 : 실리콘나이트라이드막 20 : 시일링질화막18 silicon nitride film 20 sealing nitride film

22 : 제1스페이스질화막 24 : 제2스페이스질화막22: first space nitride film 24: second space nitride film

26 : 제1스페이스산화막 28 : 스페이스막26: first space oxide film 28: space film

30 : 제1절연막 32 : 제1감광막30: first insulating film 32: first photosensitive film

34 : 제2절연막 36 : 제2절연막34: second insulating film 36: second insulating film

38 : 플러그용 폴리실리콘층38: polysilicon layer for plug

이러한 목적은, 셀영역과 주변회로영역을 갖는 모스형 트랜지스터 제조방법에 있어서, 반도체기판 상에 게이트산화막, 폴리실리콘막, 텅스텐막 및 실리콘나이트라이드막을 적층한 후, 마스킹식각으로 게이트를 셀영역 및 주변회로영역에 각각 형성하는 단계와; 상기 결과물 상에 실링질화막을 도포한 후, 그 위에 제1스페이서질화막을 적층하고, 전 영역에 불순물 이온을 주입하는 단계와; 상기 결과물 상에 제2스페이서질화막과 제1스페이서산화막을 적층하는 단계와; 상기 셀 부분을 제외한 주변 회로 영역의 PMOS 영역을 전면 식각하여 워드라인스페이서를 형성하고 이온 주입을 실시하는 단계와, 상기 셀 부분을 제외한 주변 회로 영역의 NMOS 영역을 전면 식각하여 스페이서를 형성한 후 전면식각과 이온 주입을 실시하는 단계와; 상기 결과물 상에 제1절연막을 적층하고, 셀영역을 개방하도록 제1감광막을 주변회로영역에 적층한 후, 셀영역의 제1절연막 및 제1스페이서산화막을 제거하는 단계와; 상기 제1감광막을 제거한 후 전면식각으로 셀영역에 제1,제2스페이서질화막을 잔류시키고, 주변회로영역의 제1절연막을 잔류시키도록 식각하는 단계와; 상기 제2절연막을 전 영역에 증착한 후, 평탄화를 실시하고, 페리영역을 차단하도록 제2감광막을 적층하여 셀영역의 제2절연막 및 제1,제2스페이서질화막을 제거하여 활성영역을 개방하는 단계와; 상기 결과물에서 잔류된 제2감광막을 제거한 후, 이온주입을 실시하고, 전영역에 플러그용 폴리실리콘층을 적층하는 단계로 이루어진 반도체장치의 트랜지스터 제조방법을 제공함으로써 달성된다.The object of the present invention is to fabricate a MOS transistor having a cell region and a peripheral circuit region, in which a gate oxide film, a polysilicon film, a tungsten film, and a silicon nitride film are laminated on a semiconductor substrate, and then the gate is formed in a cell region by masking etching. Forming each of the peripheral circuit regions; Applying a sealing nitride film on the resultant, stacking a first spacer nitride film thereon, and implanting impurity ions into the entire region; Stacking a second spacer nitride film and a first spacer oxide film on the resultant material; Etching the PMOS region of the peripheral circuit region except for the cell portion to form a word line spacer and performing ion implantation; forming a spacer by etching the NMOS region of the peripheral circuit region except for the cell portion to form a spacer. Performing etching and ion implantation; Stacking a first insulating film on the resultant, stacking a first photosensitive film in a peripheral circuit area to open a cell area, and then removing the first insulating film and the first spacer oxide film in the cell area; Removing the first photoresist layer, and then etching the first and second spacer nitride layers in the cell region by etching the entire surface and leaving the first insulating layer in the peripheral circuit region; After depositing the second insulating film over the entire area, planarization is performed, and a second photoresist film is laminated to block the ferry region, thereby removing the second insulating film and the first and second spacer nitride films of the cell region to open the active region. Steps; After removing the second photoresist film remaining in the resultant, ion implantation is carried out, and a method of manufacturing a transistor of a semiconductor device comprising the steps of laminating a polysilicon layer for plugs over the entire region is achieved.

상기 제1스페이서질화막의 적층 두께는, 10 ∼ 70Å의 범위를 갖고, 상기 제2스페이서질화막의 적층 두께는, 100 ∼ 300Å의 범위를 갖는다.The lamination thickness of the first spacer nitride film has a range of 10 to 70 GPa, and the lamination thickness of the second spacer nitride film has a range of 100 to 300 GPa.

그리고, 상기 제1스페이서산화막은 HTO산화막이고, 적층 두께는, 100 ∼ 300Å의 범위를 갖는다.The first spacer oxide film is an HTO oxide film, and the laminated thickness has a range of 100 to 300 Pa.

상기 제1절연막의 적층 두께는, 500 ∼ 1000Å의 범위로 적층된 후, 전면식각으로 셀영역에 잔류되는 제1,제2스페이서질화막의 두께는 100 ∼ 400Å의 범위를 갖는다.After the stacking thickness of the first insulating film is laminated in the range of 500 to 1000 GPa, the thickness of the first and second spacer nitride films remaining in the cell region by the front surface etching is in the range of 100 to 400 GPa.

그리고, 상기 제2절연막의 적층 두께는, 300 ∼ 1000Å의 범위를 갖는다.And the lamination thickness of the said 2nd insulating film has a range of 300-1000 GPa.

이하, 첨부도면에 의거하여 본 발명의 일실시예에 따른 제조방법을 살펴 보도록 한다.Hereinafter, look at the manufacturing method according to an embodiment of the present invention based on the accompanying drawings.

도 1 내지 도 8은 본 발명의 일실시예에 따른 트랜지스터의 형성방법을 순차적을 보인 도면이다.1 to 8 are diagrams sequentially illustrating a method of forming a transistor according to an embodiment of the present invention.

도 1에 도시된 바와 같이, 반도체기판(10) 상에 게이트산화막(12),폴리실리콘막(14), 텅스텐막(16) 및 실리콘나이트라이드막(18)을 적층한 후, 마스킹식각으로 게이트를 셀영역 및 주변회로영역에 각각 형성하도록 한다.As shown in FIG. 1, the gate oxide film 12, the polysilicon film 14, the tungsten film 16, and the silicon nitride film 18 are stacked on the semiconductor substrate 10, and then the gate is masked. Are formed in the cell region and the peripheral circuit region, respectively.

그리고, 상기 결과물 상에 시일링질화막(20)을 도포한 후, 도 2에 도시된 바와 같이, 그 위에 제1스페이서질화막(22)을 적층하고, 전 영역에 불순물 이온을 주입하도록 한다.After the sealing nitride film 20 is coated on the resultant, as shown in FIG. 2, the first spacer nitride film 22 is stacked thereon, and impurity ions are implanted into the entire region.

상기 제1스페이서질화막(22)의 적층 두께는, 10 ∼ 70Å의 범위를 갖는 것이 바람직 하다.It is preferable that the lamination thickness of the said 1st spacer nitride film 22 has a range of 10-70 GPa.

도 3에 도시된 바와 같이, 상기 결과물 상에 제2스페이서질화막(24)과 제1스페이서산화막(26)을 적층하도록 한다.As shown in FIG. 3, the second spacer nitride layer 24 and the first spacer oxide layer 26 are stacked on the resultant.

상기 제2스페이서질화막(24)의 적층 두께는, 100 ∼ 300Å의 범위를 갖는 것이 바람직 하고, 상기 제1스페이서산화막(26)은 HTO(Hot Thermal Oxide)산화막이고, 적층 두께는, 100 ∼ 300Å의 두께 범위를 갖도록 적층한다.It is preferable that the lamination thickness of the second spacer nitride film 24 has a range of 100 to 300 GPa, and the first spacer oxide film 26 is a HTO (hot thermal oxide) oxide film, and the lamination thickness is 100 to 300 GPa. Laminate to have a thickness range.

도 4에 도시된 바와같이, 상기 결과물 상에 감광막을 도포하고 페리영역을 개방하여 P-MOS 및 N-MOS영역을 각각 전면식각으로 식각하여 스페이서막(28)을 형성한 후, 이온주입을 실시하도록 한다.As shown in FIG. 4, after the photoresist is coated and the ferry region is opened to form a spacer layer 28 by etching the P-MOS and N-MOS regions, the ion implantation is performed. Do it.

그리고, 도 5 및 도 6에 도시된 바와 같이, 상기 결과물 상에 제1절연막(30)을 적층하고, 셀영역을 개방하도록 제1감광막(32)을 주변회로영역에 적층한 후, 셀영역의 제1절연막(30) 및 제1스페이서산화막(18)을 제거하도록 한다.5 and 6, the first insulating film 30 is laminated on the resultant product, and the first photosensitive film 32 is laminated on the peripheral circuit region to open the cell region. The first insulating film 30 and the first spacer oxide film 18 are removed.

도 7에 도시된 바와 같이, 상기 제1감광막(32)을 제거한 후 전면식각으로 셀영역에 제1,제2스페이서질화막(22)(24)을 잔류시키고, 주변회로영역의 제1절연막(30)을 잔류시키도록 식각하도록 한다.As shown in FIG. 7, after the first photoresist layer 32 is removed, the first and second spacer nitride layers 22 and 24 are left in the cell region by front etching, and the first insulating layer 30 in the peripheral circuit region is removed. To etch away).

그리고, 상기 제2절연막(34)을 전 영역에 증착한 후, 평탄화를 실시하고, 페리영역을 차단하도록 제2감광막(36)을 적층하도록 한다.After the second insulating film 34 is deposited on the entire region, the second insulating film 36 is stacked to planarize and block the ferry region.

그리고, 도 8에 도시된 바와 같이, 상기 결과물에서 셀영역의 제2절연막(34) 및 제1,제2스페이서질화막(22)(24)을 제거하여 활성영역을 개방하도록 한다, 그리고, 그 결과물에서 잔류된 제2감광막(36)을 제거한 후, 이온주입을 실시하고, 전영역에 플러그용 폴리실리콘층(38)을 적층하도록 한다.As shown in FIG. 8, the second insulating layer 34 and the first and second spacer nitride layers 22 and 24 of the cell region are removed from the resultant portion to open the active region. After removing the second photosensitive film 36 remaining in the ion implantation, the polysilicon layer 38 for plugging is laminated on the entire region.

따라서, 상기한 바와 같이, 본 발명에 따른 반도체장치의 트랜지스터 제조방법을 이용하게 되면, 반도체장치에서 셀영역을 개방할 때, 반도체기판의 활성영역의 어택을 최소화하고, 셀영역의 폴리플러그를 형성하면서 주변회로영역의 트랜지스터를 형성하며, 자기정렬콘택의 콘택을 셀영역에서 형성할 때, 식각장벽물질의 손실을 최소화하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the transistor manufacturing method of the semiconductor device according to the present invention is used, when the cell region is opened in the semiconductor device, the attack of the active region of the semiconductor substrate is minimized and the polyplug of the cell region is formed. While forming a transistor in the peripheral circuit region, and forming a contact of the self-aligned contact in the cell region, it is a very useful and effective invention to minimize the loss of the etch barrier material.

Claims (6)

셀영역과 주변회로영역을 갖는 모스형 트랜지스터 제조방법에 있어서, 반도체기판 상에 게이트산화막, 폴리실리콘막, 텅스텐막 및 실리콘나이트라이드막을 적층한 후, 마스킹식각으로 게이트를 셀영역 및 주변회로영역에 각각 형성하는 단계와;In a method of manufacturing a MOS transistor having a cell region and a peripheral circuit region, a gate oxide film, a polysilicon film, a tungsten film, and a silicon nitride film are laminated on a semiconductor substrate, and then gates are formed in the cell region and the peripheral circuit region by masking etching. Respectively forming; 상기 결과물 상에 실링질화막을 도포한 후, 그 위에 제1스페이서질화막을 적층하고, 전 영역에 불순물 이온을 주입하는 단계와;Applying a sealing nitride film on the resultant, stacking a first spacer nitride film thereon, and implanting impurity ions into the entire region; 상기 결과물 상에 제2스페이서질화막과 제1스페이서산화막을 적층하는 단계와;Stacking a second spacer nitride film and a first spacer oxide film on the resultant material; 상기 셀 부분을 제외한 주변 회로 영역의 PMOS 영역을 전면 식각하여 워드라인스페이서를 형성하고 이온 주입을 실시하는 단계와,Etching the entire PMOS region of the peripheral circuit region excluding the cell portion to form a word line spacer and performing ion implantation; 상기 셀 부분을 제외한 주변 회로 영역의 NMOS 영역을 전면 식각하여 스페이서를 형성한 후 전면식각과 이온 주입을 실시하는 단계와;Performing a full surface etch and ion implantation after the entire surface is etched in the NMOS region except for the cell portion to form a spacer; 상기 결과물 상에 제1절연막을 적층하고, 셀영역을 개방하도록 제1감광막을 주변회로영역에 적층한 후, 셀영역의 제1절연막 및 제1스페이서산화막을 제거하는 단계와;Stacking a first insulating film on the resultant, stacking a first photosensitive film in a peripheral circuit area to open a cell area, and then removing the first insulating film and the first spacer oxide film in the cell area; 상기 제1감광막을 제거한 후 전면식각으로 셀영역에 제1,제2스페이서질화막을 잔류시키고, 주변회로영역의 제1절연막을 잔류시키도록 식각하는 단계와;Removing the first photoresist layer, and then etching the first and second spacer nitride layers in the cell region by etching the entire surface and leaving the first insulating layer in the peripheral circuit region; 상기 제2절연막을 전 영역에 증착한 후, 평탄화를 실시하고, 페리영역을 차단하도록 제2감광막을 적층하여 셀영역의 제2절연막 및 제1,제2스페이서질화막을 제거하여 활성영역을 개방하는 단계와;After depositing the second insulating film over the entire area, planarization is performed, and a second photoresist film is laminated to block the ferry region, thereby removing the second insulating film and the first and second spacer nitride films of the cell region to open the active region. Steps; 상기 결과물에서 잔류된 제2감광막을 제거한 후, 이온주입을 실시하고, 전영역에 플러그용 폴리실리콘층을 적층하는 단계로 이루어진 것을 특징으로 하는 반도체장치의 트랜지스터 제조방법.Removing the second photoresist film remaining in the resultant, performing ion implantation, and laminating a polysilicon layer for plugging the entire region. 제 1 항에 있어서, 상기 제1스페이서질화막의 적층 두께는, 10 ∼ 70Å의 범위를 갖는 것을 특징으로 하는 반도체장치의 트랜지스터 제조방법.The method of manufacturing a transistor of a semiconductor device according to claim 1, wherein the laminated thickness of said first spacer nitride film has a range of 10 to 70 GPa. 제 1 항에 있어서 상기 제2스페이서질화막의 적층 두께는, 100 ∼ 300Å의 범위를 갖는 것을 특징으로 하는 반도체장치의 트랜지스터 제조방법.The method of manufacturing a transistor of a semiconductor device according to claim 1, wherein the stack thickness of said second spacer nitride film is in the range of 100 to 300 mW. 제 1 항에 있어서, 상기 제1스페이서산화막은, HTO산화막이고, 적층 두께는, 100 ∼ 300Å의 범위를 갖는 것을 특징으로 하는 반도체장치의 트랜지스터 제조방법.The method of manufacturing a transistor of a semiconductor device according to claim 1, wherein said first spacer oxide film is an HTO oxide film, and a lamination thickness is in the range of 100 to 300 kHz. 제 1 항에 있어서, 상기 제1절연막의 적층 두께는, 500 ∼ 1000Å의 범위로 적층된 후, 전면식각으로 셀영역에 잔류되는 제1,제2스페이서질화막의 두께는 100 ∼ 400Å의 범위를 갖는 것을 특징으로 하는 반도체장치의 트랜지스터 제조방법.The thickness of the first and second spacer nitride film remaining in the cell region by the front surface etching after the lamination thickness of the first insulating film is laminated in the range of 500 to 1000 GPa has a range of 100 to 400 GPa. A transistor manufacturing method of a semiconductor device, characterized by the above-mentioned. 제 1 항에 있어서, 상기 제2절연막의 적층 두께는, 300 ∼ 1000Å의 범위를 갖는 것을 특징으로 하는 반도체장치의 트랜지스터 제조방법.The method of manufacturing a transistor of a semiconductor device according to claim 1, wherein the stack thickness of said second insulating film has a range of 300 to 1000 mW.
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SG110063A1 (en) * 2003-03-26 2005-04-28 Ethyl Corp Additives for fuel compositions to reduce formation of combustion chamber deposits
KR101051799B1 (en) * 2004-12-30 2011-07-25 매그나칩 반도체 유한회사 Method of manufacturing semiconductor device
KR101128684B1 (en) * 2004-12-30 2012-03-26 매그나칩 반도체 유한회사 Method for manufacturing a semiconductor device
CN104979292A (en) * 2015-05-15 2015-10-14 上海华力微电子有限公司 Method for forming different sidewall structures
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JPH03101238A (en) * 1989-09-14 1991-04-26 Toshiba Corp Mos type semiconductor device and its manufacture
KR20000032293A (en) * 1998-11-13 2000-06-15 윤종용 Method for manufacturing semiconductor memory device
KR100328810B1 (en) * 1999-07-08 2002-03-14 윤종용 Contact structure for a semiconductor device and manufacturing method thereof
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG110063A1 (en) * 2003-03-26 2005-04-28 Ethyl Corp Additives for fuel compositions to reduce formation of combustion chamber deposits
KR101051799B1 (en) * 2004-12-30 2011-07-25 매그나칩 반도체 유한회사 Method of manufacturing semiconductor device
KR101128684B1 (en) * 2004-12-30 2012-03-26 매그나칩 반도체 유한회사 Method for manufacturing a semiconductor device
CN104979292A (en) * 2015-05-15 2015-10-14 上海华力微电子有限公司 Method for forming different sidewall structures
KR20210000254U (en) 2019-07-23 2021-02-02 정진모 Shading device for a side door of a vehicle

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