KR100338933B1 - Contact fabricating method for semiconductor device - Google Patents
Contact fabricating method for semiconductor device Download PDFInfo
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- KR100338933B1 KR100338933B1 KR1019990048117A KR19990048117A KR100338933B1 KR 100338933 B1 KR100338933 B1 KR 100338933B1 KR 1019990048117 A KR1019990048117 A KR 1019990048117A KR 19990048117 A KR19990048117 A KR 19990048117A KR 100338933 B1 KR100338933 B1 KR 100338933B1
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- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000000635 electron micrograph Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 콘택 형성 방법에 관한 것으로, 종래의 기술에 있어서 게이트 측벽의 폴리 실리콘을 제거하기 위해 과도하게 에칭함으로써, 플러그의 프로파일에 보잉(bowing)이 발생하여 활성 영역이 손상됨과 아울러 상기 플러그의 전기 저항이 커짐에 따라 측벽의 폴리 실리콘 잔류 제거와 플러그의 수직 프로파일 확보를 동시에 만족시킬수 없는 문제점이 있었고, 또한, 게이트 갭의 손실이 심해져 이후의 식각 공정에서 게이트 물질인 금속이 노출되어 장비를 오염시키는 문제점이 있었다. 따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 게이트와 측벽이 형성된 기판의 상부전면에 높은 노핑 농도의 플러그용 폴리 실리콘과 낮은 노핑 농도의 플러그용 폴리 실리콘을 순차적으로 증착함으로써, 프리 폴리 플러그의 식각 공정시 상기 폴리 실리콘의 잔류물을 제거함과 동시에 플러그의 수직 프로파일을 확보하며, 게이트 갭의 손실을 방지하는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and in the prior art, by excessively etching to remove polysilicon of a gate sidewall, bowing occurs in the profile of the plug, and the active region is damaged. As the electrical resistance of the plug increases, there is a problem that it is impossible to simultaneously satisfy the removal of polysilicon residue on the sidewalls and the securing of the vertical profile of the plug. Also, the gate gap is severely lost, and the metal, which is the gate material, is exposed in the subsequent etching process. There was a problem polluting. Accordingly, the present invention has been devised to solve the above-mentioned conventional problems, and sequentially deposits high polypping plug polysilicon and low polypping plug polysilicon on the upper surface of the substrate on which the gate and the sidewall are formed. As a result, the residue of the polysilicon is removed during the etching process of the pre-poly plug, and the vertical profile of the plug is ensured, thereby preventing the loss of the gate gap.
Description
본 발명은 반도체 소자의 콘택 형성 방법에 관한 것으로, 특히 노광 공정의 한계에 도달한 차세대 고집적 소자에 있어서 프리 폴리 플러그(Pre-Poly Plug)의 식각 공정시 폴리 실리콘의 잔류물(Residue)을 완전히 제거함과 동시에 우수한 플러그의 수직 프로파일(Vertical Profile)을 확보하도록 한 반도체 소자의 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and particularly to completely remove residues of polysilicon during an etching process of a pre-poly plug in a next-generation highly integrated device that has reached the limit of an exposure process. In addition, the present invention relates to a method for forming a contact of a semiconductor device to ensure an excellent vertical profile of the plug.
차세대 고집적 소자 형성시 어려움의 하나는 0.2㎛이하의 홀을 패터닝(Pattern)하는 것으로, 현재 상용되고 있는 포토 장비로는 요구되는 해상도(resolution)와 설계상의 중첩 마진(overlay margin)을 만족하기가 어렵다.One of the difficulties in forming next-generation high-density devices is to pattern holes smaller than 0.2 μm, and it is difficult to satisfy the resolution and overlay margin required by current photo equipment. .
이를 극복하기 위하여 사용되는 방법이 자동 정렬 콘택(Self-Aligned Contact : 이하, 에스에이씨라 함)이나, 이 역시 0.15㎛이하로 홀 크기를 줄이면, 해상도가 떨어져 현재의 포토 장비로는 홀을 정의(Define)하기가 매우 어렵게 된다.The method used to overcome this problem is automatic alignment contact (Self-Aligned Contact), but if the hole size is also reduced to less than 0.15㎛, the resolution is lowered and current hole is defined as the current photo equipment ( It becomes very difficult to define.
이에 따라 개발된 기술이 셀 콘택(Cell Contact)을 위하여 도체의 역할을 하는 폴리실리콘을 증착한 후, 이를 이용하여 불필요한 영역을 식각하여 플러그를 형성하는 프리 폴리 플러그 공정이다.Accordingly, the developed technology is a pre-poly plug process for depositing polysilicon that serves as a conductor for cell contact, and then etching the unnecessary area using the same.
이하, 종래 기술에 따른 일실시예 동작과정을 첨부한 도 1a 내지 도 1e를 참조하여 설명한다.Hereinafter, a description will be given with reference to FIGS. 1A to 1E to which an operation process according to the prior art is attached.
우선, 도 1a와 같이 반도체 기판(1)의 상부에 게이트 산화막, 다결정 실리콘 및 상부 질화막(2)을 증착하게 되고, 이를 패터닝하여 상기 반도체 기판(1)의 상부에 다수의 게이트를 형성한 후, 그 게이트 측면에 질화막 측벽(3)을 형성하게 된다.First, as shown in FIG. 1A, a gate oxide film, a polycrystalline silicon, and an upper nitride film 2 are deposited on the semiconductor substrate 1, and then patterned to form a plurality of gates on the semiconductor substrate 1. The nitride film sidewall 3 is formed on the side of the gate.
그리고, 도 1b와 같이 상기 측벽(3)과 상부 질화막(2)으로 보호되는 게이트의 상부에 폴리 실리콘(4)을 두껍게 증착하여 하부의 구조가 노출되지 않도록 하게 되고, 도 1c와 같이 상기 증착된 폴리 실리콘(4)을 화학적 기계적 연마를 통해 평탄화하여 상기 게이트 상부에 증착된 상부 질화막(2)이 노출되도록 한다.In addition, as illustrated in FIG. 1B, the polysilicon layer 4 is thickly deposited on the upper side of the gate protected by the sidewall 3 and the upper nitride layer 2 so that the lower structure is not exposed. As illustrated in FIG. The polysilicon 4 is planarized by chemical mechanical polishing so that the upper nitride film 2 deposited on the gate is exposed.
그리고, 도 1d와 같이 포토 레지스터(Photo Resistor : 이하, '피알'이라 함)(5)를 증착한 후, 셀 콘택에 해당하는 영역을 제거하게 되고, 도 1e에 도시된 바와 같이 상기 피알(5)을 이용하여 상기 폴리 실리콘(4)을 선택적으로 식각하여 비트라인과 커패시터를 형성할 위치인 셀 콘택 영역을 형성하게 된다.Then, after depositing a photo resistor (hereinafter referred to as a 'PH') 5 as shown in FIG. 1D, the region corresponding to the cell contact is removed, as shown in FIG. 1E. The polysilicon 4 is selectively etched to form a cell contact region where a bit line and a capacitor are to be formed.
이때, 상기 프리 폴리 플러그 공정은 각 플러그의 전기적 절연을 위하여 게이트 측벽의 폴리 실리콘(4)을 완벽히 제거함과 동시에 정렬 마진(Align Margin)을 확보하기 위하여 플러그의 프로파일을 수직으로 유지함에 따라 식각 공정에서 등방성과 이방석 식각의 특성이 모두 요구된다.At this time, in the etching process, the pre-poly plug process completely removes the polysilicon 4 of the gate sidewall for electrical insulation of each plug and maintains the plug profile vertically to secure an alignment margin. Both isotropic and anisotropic etching characteristics are required.
따라서, 상기와 같이 종래의 기술에 있어서 게이트 측벽의 폴리 실리콘을 제거하기 위해 과도하게 에칭함으로써, 플러그의 프로파일에 보잉(bowing)이 발생하여 활성 영역이 손상됨과 아울러 상기 플러그의 전기 저항이 커짐에 따라 측벽의 폴리 실리콘 잔류 제거와 플러그의 수직 프로파일 확보를 동시에 만족시킬수 없는 문제점이 있었고, 또한, 게이트 갭의 손실이 심해져 이후의 식각 공정에서 게이트 물질인 금속이 노출되어 장비를 오염시키는 문제점이 있었다.Therefore, in the prior art as described above, by excessively etching to remove the polysilicon of the gate sidewall, bowing occurs in the profile of the plug, which damages the active region and increases the electrical resistance of the plug. There was a problem that the polysilicon residue removal of the sidewalls and the securing of the vertical profile of the plug could not be satisfied at the same time, and the loss of the gate gap was so severe that the metal, which is the gate material, was exposed in the subsequent etching process to contaminate the equipment.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 높은 도핑 농도와 낮은 도핑 농도를 갖는 플러그용 폴리 실리콘을 순차적으로 증착하여 프리 폴리 플러그의 식각 공정시 폴리 실리콘의 잔류물을 제거함과 동시에 플러그의 수직 프로파일을 확보하도록 한 반도체 소자의 콘택 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, by sequentially depositing the plug polysilicon having a high doping concentration and a low doping concentration to remove the residue of the polysilicon during the etching process of the pre-poly plug It is an object of the present invention to provide a method for forming a contact of a semiconductor device to remove the same and to ensure a vertical profile of the plug.
도 1a 내지 도 1e는 종래 반도체 소자의 콘택 형성 공정의 수순 단면도.1A to 1E are procedure cross-sectional views of a contact forming process of a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명 반도체 소자의 콘택 형성 공정의 수순 단면도.2A to 2F are procedure cross-sectional views of a contact forming process of a semiconductor device of the present invention.
도 3 및 도 4는 도핑 농도가 각각 4.75 × 1020및 0.6 × 1020인 폴리 실리콘의 식각 프로파일을 보인 전자 현미경 사진.3 and 4 are electron micrographs showing the etching profile of polysilicon having a doping concentration of 4.75 × 10 20 and 0.6 × 10 20 , respectively.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
10 : 반도체 기판 11 : 질화막10 semiconductor substrate 11 nitride film
12 : 측벽 13, 14 : 폴리 실리콘12: side wall 13, 14: polysilicon
15 : 피알15: PI
상기와 같은 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 게이트 산화막, 다결정 실리콘 및 상부 질화막을 증착 및 패터닝하여 다수의 게이트를 형성하고, 그 게이트 측면에 질화막 측벽을 형성하는 공정과; 상기 다수의 게이트와 측벽이 형성된 기판의 상부전면에 높은 도핑농도의 제1 폴리 실리콘을 증착하는 공정과; 상기 제1 폴리 실리콘의 상부전면에 낮은 도핑농도의 제2 폴리 실리콘을 증착하는 공정과; 화학적 기계적 연마를 통해 상기 증착된 제1,제2 폴리 실리콘을 게이트 상부에 증착된 상부 질화막이 노출되도록 평탄화하는 공정과; 피알을 이용하여 상기 제1,제2 폴리 실리콘을 선택적으로 식각하는 공정으로 이루어진 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of depositing and patterning a gate oxide film, polycrystalline silicon and the upper nitride film on the semiconductor substrate to form a plurality of gates, and forming a nitride film sidewall on the gate side; Depositing a high doping concentration of first polysilicon on an upper surface of the substrate on which the plurality of gates and sidewalls are formed; Depositing a second polysilicon having a low doping concentration on an upper surface of the first polysilicon; Planarizing the deposited first and second polysilicon to expose the upper nitride film deposited on the gate through chemical mechanical polishing; And selectively etching the first and second polysilicon using PAL.
이하, 본 발명에 따른 일실시예에 대한 동작과 작용효과를 첨부한 도 2a 내지 도 4를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, with reference to Figures 2a to 4 attached to the operation and effect for one embodiment according to the present invention will be described in detail.
우선, 반도체 기판(10)의 상부에 게이트 산화막, 다결정 실리콘 및 상부 질화막(11)을 증착하고, 이를 패터닝하여 상기 반도체 기판(10)의 상부에 다수의 게이트를 형성한 후, 그 게이트 측면에 질화막 측벽(12)을 형성한다.First, a gate oxide film, a polycrystalline silicon, and an upper nitride film 11 are deposited on the semiconductor substrate 10, and then patterned to form a plurality of gates on the semiconductor substrate 10, and then a nitride film on the gate side thereof. The side wall 12 is formed.
여기서, 상기 게이트와 측벽(12)이 형성된 기판(10)의 상부전면에 폴리 실리콘을 증착시 노광공정에서 게이트의 프로파일에 보잉이 생기기 때문에 게이트 측벽에 증착된 폴리 실리콘의 완벽한 제거에 어려움이 있으며, 이에 상기 잔류물의 제거를 위해 등방성 특성이 있는 오버 에칭의 시간을 늘리면 플러그의 수직 프로파일 확보가 매우 어렵다.Here, when polysilicon is deposited on the upper surface of the substrate 10 on which the gate and the sidewalls 12 are formed, it is difficult to completely remove the polysilicon deposited on the gate sidewalls because boeing occurs in the profile of the gate during the exposure process. Therefore, it is very difficult to secure the vertical profile of the plug by increasing the time of over etching with the isotropic property to remove the residue.
그러나, 상기 폴리 실리콘의 경우 도핑 농도에 따라 식각 특성이 바뀌므로, 도 3에 도시한 바와 같이 도핑 농도가 큰 약 4.75 × 1020인 폴리 실리콘의 경우 등방향 식각 속도가 빠르기 때문에 잔류 제거가 용이하나 수직 프로파일이 나쁘고, 도 4에 도시한 바와 같이 도핑 농도가 작은 0.6 × 1020인 폴리 실리콘의 경우 등방향 식각 속도가 느려 수직 프로파일이 좋으나 잔류 제거가 용이하지 않다.However, in the case of the polysilicon since the etching characteristics change depending on the doping concentration, in the case of the doping concentration is greater about 4.75 × 10 20 of polysilicon, as shown in Fig. 3 and so on as early a direction etch rate residue removal is easy one As shown in FIG. 4, in the case of polysilicon having 0.6 × 10 20 having a low vertical profile and a low doping concentration, the vertical profile is good due to a low isotropic etching rate, but residual removal is not easy.
따라서, 상기 성질을 이용하여 도 2c와 같이 상기 게이트와 측벽(12)이 형성된 기판(10)의 상부전면에 약 2.0 × 1020∼ 5.0 × 1020로 큰 도핑 농도를 갖는 폴리 실리콘(13)을 증착한 후, 도 2d와 같이 상기 폴리 실리콘(13)의 상부 전면에 0.5 × 1020∼ 1.0 × 1020로 작은 도핑 농도를 갖는 폴리 실리콘(14)를 증착한다.Accordingly, the polysilicon 13 having a large doping concentration of about 2.0 × 10 20 to 5.0 × 10 20 is formed on the upper front surface of the substrate 10 on which the gate and the sidewall 12 are formed as shown in FIG. 2C. After deposition, polysilicon 14 having a small doping concentration of 0.5 × 10 20 to 1.0 × 10 20 is deposited on the entire upper surface of the polysilicon 13 as shown in FIG. 2D.
이에 상기 높은 도핑 농도의 폴리 실리콘(13)과 낮은 도핑 농도의 폴리 실리콘(14)에 의해 식각 공정시 게이트 측벽(12)의 등방성 및 이방성 식각 속도가 빨라져 잔류 제거가 용이하고, 우수한 수직 프로파일을 유지한다.The high doping concentration of polysilicon 13 and the low doping concentration of polysilicon 14 facilitate the isotropic and anisotropic etching rates of the gate sidewalls 12 during the etching process, so that the residue is easily removed and maintains an excellent vertical profile. do.
그리고, 도 2d와 같이 상기 증착된 폴리 실리콘(13)(14)을 화학적 기계적 연마를 통해 상기 게이트 상부에 증착된 상부 질화막(11)이 노출되도록 평탄화하고, 도 2e와 같이 피알(15)을 증착한 후, 셀 콘택에 해당하는 영역에 해당하는 상기 피알(15)을 제거하고, 도 2f에 도시한 바와 같이 상기 피알(15)을 이용하여 상기 폴리 실리콘(13)(14)을 선택적으로 식각하여 비트라인과 커패시터를 형성할 위치인 셀 콘택 영역을 형성한다.2D, the deposited polysilicon 13 and 14 are planarized to expose the upper nitride film 11 deposited on the gate through chemical mechanical polishing, and the PAL 15 is deposited as illustrated in FIG. 2E. After that, the PI 15 corresponding to the region corresponding to the cell contact is removed, and the polysilicon 13 and 14 are selectively etched using the PI 15 as shown in FIG. 2F. A cell contact region, which is a position where a bit line and a capacitor are to be formed, is formed.
상기에서 상세히 설명한 바와 같이, 본 발명은 게이트와 측벽이 형성된 기판의 상부전면에 높은 노핑 농도의 플러그용 폴리 실리콘과 낮은 노핑 농도의 플러그용 폴리 실리콘을 순차적으로 증착함으로써, 프리 폴리 플러그의 식각 공정시 상기 폴리 실리콘의 잔류물을 제거함과 동시에 플러그의 수직 프로파일을 확보하며, 게이트 갭의 손실을 방지하는 효과가 있다.As described in detail above, the present invention sequentially deposits the high polypping plug polysilicon and the low polypping plug polysilicon on the upper surface of the substrate on which the gate and the sidewalls are formed, thereby the pre-poly plug etching process. While removing the residue of the polysilicon at the same time ensures the vertical profile of the plug, there is an effect to prevent the loss of the gate gap.
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| US5670404A (en) * | 1996-06-21 | 1997-09-23 | Industrial Technology Research Institute | Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer |
| JPH1070191A (en) * | 1996-06-19 | 1998-03-10 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| JPH10321838A (en) * | 1997-05-16 | 1998-12-04 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH1187653A (en) * | 1997-09-09 | 1999-03-30 | Fujitsu Ltd | Semiconductor device and its manufacture |
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| JPH1070191A (en) * | 1996-06-19 | 1998-03-10 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| US5670404A (en) * | 1996-06-21 | 1997-09-23 | Industrial Technology Research Institute | Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer |
| JPH10321838A (en) * | 1997-05-16 | 1998-12-04 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH1187653A (en) * | 1997-09-09 | 1999-03-30 | Fujitsu Ltd | Semiconductor device and its manufacture |
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