KR20030000668A - Method for forming a contact hole of a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a contact hole of a semiconductor device is provided to prevent a semiconductor substrate from being exposed in an etch process for forming the contact hole, by making a part of an insulation layer left in an interfacial part between a field region and an active region. CONSTITUTION: An interlayer dielectric(17) is formed on a semiconductor substrate(11) including the field region(21) and the active region(14b). The interlayer dielectric is patterned by an etch process using a predetermined mask so that the contact hole(18) is so formed to expose the semiconductor substrate in the field region and the active region. A part of the interlayer dielectric is left on the semiconductor substrate in the interfacial part between the field region and the active region.

Description

Method for forming a contact hole of a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device for forming a plug having a line shape.

In general, the connection between the conductive layers in the semiconductor device manufacturing process is made through contact holes formed in the insulating film. However, since the size of the pattern decreases as the degree of integration of the semiconductor device increases, the size of the contact hole also decreases, thereby increasing the contact resistance between the conductive layers even when a slight misalignment occurs in the photolithography process for forming the contact hole. So, in recent years, the contact holes are formed long in the form of a line. A conventional method of forming a contact hole in the form of a line will be described with reference to FIGS. 1A to 1C as follows.

The line-type contact holes are formed to expose the junction regions 2 of the three neighboring memory cells. For this purpose, a mask in which the contact pattern 4 is formed as shown in FIG. 1A is used. Therefore, when the patterning process is performed using the mask, a line-type contact hole 4a as shown in FIG. 1B can be obtained.

In FIG. 1A, reference numeral 1 denotes a field region, reference numeral 2 denotes an active region, and reference numeral 3 denotes a portion where a gate is located. In FIG. 1B, reference numeral 4b denotes an upper portion of the contact hole 4a, and reference numeral 4c denotes the contact hole ( The lower part of 4a) is indicated, respectively. The lower portion 4c of the contact hole 4a is formed narrower than the upper portion 4b by a spacer formed on the sidewall of the gate 3.

However, when the contact hole 4a is formed as described above, since the active region 2 and the field region 1 are exposed together during the etching process, the semiconductor of the interface between the active region 2 and the field region 1 having a weak crystal structure is exposed. The substrate is damaged and damage caused by the damage is transferred to the active region 2 to generate a leakage current during operation of the device. This problem also contributes to the deterioration of the reflash characteristics of memory devices such as DRAM.

FIG. 1C is a cross-sectional view of the portion A1-A2 of FIG. 1B, in which the interlayer insulating film 5 is formed on the semiconductor substrate 10 divided into the field region 1 and the active region 2. A contact hole 4a is formed in the interlayer insulating film 5 so that a portion of the region 2 and the field region 1 are exposed, and the active region 2 during the etching process for forming the contact hole 4a. The state where the interface ("X" portion) of the field region 1 is damaged is shown.

Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device, which can solve the above-mentioned disadvantages by partially remaining an insulating film at an interface between a field region and an active region during an etching process for forming a contact hole. have.

According to an aspect of the present invention, there is provided a method of forming a contact hole in a line shape extending over a field region and an active region, the method comprising: forming an interlayer insulating film on a semiconductor substrate including the field region and the active region; Patterning the interlayer insulating film by an etching process using a predetermined mask to form a contact hole to expose the semiconductor substrate in the field region and the active region, and leaving a part of the interlayer insulating layer on the semiconductor substrate at the interface of the field region and the active region Characterized in that comprises a.

In addition, the method for forming a contact hole in a semiconductor device according to the present invention comprises forming a gate electrode on a semiconductor substrate on which an isolation layer and a well are formed, and then forming an LDD region on an exposed semiconductor substrate, and forming both side walls of the gate electrode. Forming a junction region of an LDD structure by implanting impurity ions into the exposed semiconductor substrate after forming a spacer in the spacer; forming an interlayer insulating film on the entire upper surface; and then planarizing the surface; And forming a contact hole to expose the semiconductor substrate in the field region and the active region by patterning the interlayer insulating layer using an etching process, wherein a part of the interlayer insulating layer is left on the semiconductor substrate at the interface of the field region and the active region. It is characterized by.

The mask may include a contact pattern in which junction regions of three neighboring memory cells are exposed and the interface portion of the field region and the active region is narrower than the other portions.

1A is a plan view illustrating a conventional contact hole forming mask.

1B is a cross-sectional view showing a contact hole formed by a conventional method.

1C is a cross-sectional view illustrating a state in which the portion A1-A2 of FIG. 1B is cut out;

2A to 2E are cross-sectional views of devices for explaining a method for forming a contact hole according to the present invention.

3A is a plan view for explaining a contact hole forming mask used in the present invention.

3B is a cross-sectional view illustrating a contact hole formed in accordance with the present invention.

3C is a cross-sectional view illustrating a state in which the portion B1-B2 of FIG. 3B is cut out;

<Explanation of symbols for the main parts of the drawings>

1 and 21: field areas 2 and 14b: active area

3 and 12: gates 4 and 24: contact pattern

4a and 18: contact hole 4b and 18a: upper part of contact hole

4c and 18b: lower portions of contact holes 5 and 17: interlayer insulating film

10 and 11: semiconductor substrate 13: mask pattern

14: LDD region 14a: junction region

15: spacer 16: etching prevention film

19: plug

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 2E are cross-sectional views of devices for describing a method of forming a contact hole in a semiconductor device according to the present invention, which will be described below with reference to FIGS. 3A through 3C.

FIG. 2A illustrates a semiconductor substrate in an exposed portion after forming a conductive layer 12 for a gate electrode on a semiconductor substrate 11 having a device isolation film and a well formed therein, and forming a gate electrode 12 using a mask pattern 13. A cross-sectional view of a state in which the LDD region 14 is formed by implanting impurity ions into (11), wherein the gate electrode conductive layer 12 is formed of doped polysilicon or metal, or doped polysilicon and metal It is formed in a stacked structure, the mask pattern 13 is formed of a nitride film.

2B illustrates that spacers 15 are formed on both sidewalls of the gate electrode 12 and the mask pattern 13, and then impurity ions are implanted into the exposed semiconductor substrate 11 to complete formation of the junction region 14a. As a cross-sectional view of the state, at this time, for example, spacer formation and ion implantation using a mask for an NMOS transistor are performed, followed by spacer formation and ion implantation using a mask for a PMOS transistor.

In addition, the spacer 15 is formed of a structure in which a nitride film and an oxide film are stacked, and in the peripheral circuit region, an oxide film and a nitride film are sequentially etched so that a spacer 15 made of a nitride film and an oxide film is formed on the sidewall of each gate electrode 12. After the oxide layer is removed, the cell region is etched to form a spacer 15 etched on the sidewall of each gate electrode 12 so that the contact area through the contact hole is sufficiently secured.

FIG. 2C is a cross-sectional view of the etch stop layer 16 and the interlayer dielectric layer 17 formed on the entire upper surface thereof sequentially and then planarized, for example, by the chemical mechanical polishing (CMP) process. The etch stop layer 16 is formed of a nitride film, and the interlayer insulating layer 17 is formed of BPSG.

FIG. 2D is a cross-sectional view of a state in which a contact hole 18 is formed to expose the junction region 14a by etching the interlayer insulating layer 17 until a point where the etch stop layer 16 is exposed using a predetermined mask. At this time, the interlayer insulating film 17 remains partially at the interface portion between the field region and the active region so that the semiconductor substrate 11 at the interface between the field region and the active region is not damaged.

For example, as shown in FIG. 3A, the contact region 14a of three neighboring memory cells is exposed, and the contact pattern 24 having the interface portion between the field region 21 and the active region 14b is narrower than the other portions. As shown in FIG. 3B, the lower portion 18b of the contact hole 18 is formed to be narrower than the upper portion 18c by the spacer 15 formed on the sidewall of the gate 12. The interlayer insulating layer 17 partially remains in the semiconductor substrate 11 at the bottom of the contact hole 18, that is, the semiconductor substrate 11 at the interface between the field region 21 and the active region 14b.

Therefore, since the semiconductor substrate 11 at the interface between the field region 21 and the active region 14b is not exposed by the remaining interlayer insulating layer 17, the semiconductor substrate 11 is not damaged during the etching process.

FIG. 2E illustrates that the silicon is planarized by depositing polysilicon on the entire upper surface of the contact hole 18 to be filled and then planarizing the polysilicon until the mask pattern 13 is exposed. It is sectional drawing of the state which made the plug 19 connected with the area | region 14a form.

Subsequently, after forming the interlayer insulating film on the entire upper surface, patterning is performed to form a contact hole so that the plug 19 is exposed, and an upper conductive layer is formed to be connected to the plug 19 through the contact hole. Proceed.

As described above, the semiconductor substrate of the present invention does not expose the semiconductor substrate at the interface between the field region and the active region by allowing the insulating layer to partially remain at the interface between the field region and the active region during the etching process for forming the contact hole. There is no damage to the semiconductor substrate during the etching process. Therefore, the damage of the junction region due to the etch damage of the interface part is not generated, and the yield and reliability of the device are improved. In particular, the leakage current is prevented, thereby improving the refresh characteristics of the memory device such as DRAM.

Claims (6)

In the method for forming a contact hole in the form of a line extending over the field region and the active region, Forming an interlayer insulating film on the semiconductor substrate including the field region and the active region; The interlayer insulating layer is patterned by an etching process using a predetermined mask to form a contact hole to expose the semiconductor substrate of the field region and the active region, and a portion of the interlayer insulating layer is formed on the semiconductor substrate at the interface of the field region and the active region. And forming a contact hole in the semiconductor device. The method of claim 1, And forming a contact pattern in which the junction region of three neighboring memory cells is exposed and the interface portion of the field region and the active region is narrower than the other portions. The method of claim 1, And said interlayer insulating film is a BPSG film. Forming a gate electrode on the semiconductor substrate on which the device isolation layer and the well are formed, and then forming an LDD region on the exposed semiconductor substrate; Forming spacers on both sidewalls of the gate electrode and implanting impurity ions into the exposed semiconductor substrate to form a junction region of the LDD structure; Forming an interlayer insulating film on the entire upper surface and then planarizing the surface; The interlayer insulating layer is patterned by an etching process using a predetermined mask to form contact holes to expose the semiconductor substrates in the field region and the active region, and a portion of the interlayer insulating layer remains on the semiconductor substrate at the interface of the field region and the active region. And forming a contact hole in the semiconductor device. The method of claim 4, wherein And forming a contact pattern in which the junction region of three neighboring memory cells is exposed and the interface portion of the field region and the active region is narrower than the other portions. The method of claim 4, wherein And said interlayer insulating film is a BPSG film.