KR20030000668A - Method for forming a contact hole of a semiconductor device - Google Patents
Method for forming a contact hole of a semiconductor device Download PDFInfo
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- KR20030000668A KR20030000668A KR1020010036732A KR20010036732A KR20030000668A KR 20030000668 A KR20030000668 A KR 20030000668A KR 1020010036732 A KR1020010036732 A KR 1020010036732A KR 20010036732 A KR20010036732 A KR 20010036732A KR 20030000668 A KR20030000668 A KR 20030000668A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히, 라인(Line) 형태의 플러그(Plug)를 형성하기 위한 반도체 소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device for forming a plug having a line shape.
일반적으로 반도체 소자의 제조 공정에서 도전층간의 접속은 절연막에 형성된 콘택홀을 통해 이루어진다. 그런데 반도체 소자의 집적도가 증가되면서 패턴의 크기가 감소되기 때문에 콘택홀의 크기도 감소되고, 이에 따라 콘택홀을 형성하기 위한 사진 공정시 약간의 오정렬이 발생되어도 도전층간의 접촉 저항이 증가된다. 그래서 근래에는 콘택홀을 라인 형태로 길게 형성하는데, 라인 형태로 이루어진 종래의 콘택홀 형성 방법을 도 1a 내지 도 1c를 통해 설명하면 다음과 같다.In general, the connection between the conductive layers in the semiconductor device manufacturing process is made through contact holes formed in the insulating film. However, since the size of the pattern decreases as the degree of integration of the semiconductor device increases, the size of the contact hole also decreases, thereby increasing the contact resistance between the conductive layers even when a slight misalignment occurs in the photolithography process for forming the contact hole. So, in recent years, the contact holes are formed long in the form of a line. A conventional method of forming a contact hole in the form of a line will be described with reference to FIGS. 1A to 1C as follows.
라인 형태의 콘택홀은 이웃하는 세 메모리 셀의 접합영역(2)이 노출되도록 형성되며, 이를 위해 도 1a에 도시된 바와 같은 콘택패턴(4)이 형성된 마스크를 이용한다. 그러므로 상기 마스크를 이용하여 패터닝 공정을 실시하면 도 1b와 같은 라인 형태의 콘택홀(4a)을 얻을 수 있다.The line-type contact holes are formed to expose the junction regions 2 of the three neighboring memory cells. For this purpose, a mask in which the contact pattern 4 is formed as shown in FIG. 1A is used. Therefore, when the patterning process is performed using the mask, a line-type contact hole 4a as shown in FIG. 1B can be obtained.
도 1a에서 부호 1은 필드영역, 부호 2는 활성영역, 부호 3은 게이트가 위치하는 부분을 각각 지시하며, 도 1b에서 부호 4b는 상기 콘택홀(4a)의 상부, 부호 4c는 상기 콘택홀(4a)의 하부를 각각 지시한다. 상기 콘택홀(4a)의 하부(4c)는 상기 게이트(3)의 측벽에 형성된 스페이서에 의해 상부(4b)보다 좁게 형성된다.In FIG. 1A, reference numeral 1 denotes a field region, reference numeral 2 denotes an active region, and reference numeral 3 denotes a portion where a gate is located. In FIG. 1B, reference numeral 4b denotes an upper portion of the contact hole 4a, and reference numeral 4c denotes the contact hole ( The lower part of 4a) is indicated, respectively. The lower portion 4c of the contact hole 4a is formed narrower than the upper portion 4b by a spacer formed on the sidewall of the gate 3.
그런데 상기와 같이 콘택홀(4a)을 형성할 경우 식각 공정시 활성영역(2)과 필드영역(1)이 같이 노출되기 때문에 결정 구조가 약한 활성영역(2)과 필드영역(1) 계면의 반도체 기판이 손상되고, 손상에 의한 피해가 활성영역(2)으로 전달되어 소자의 동작시 누설전류가 발생된다. 그리고 이러한 문제점은 디램(DRAM)과 같은 메모리 소자의 리플래쉬(Reflash) 특성을 열화시키는 원인으로 작용한다.However, when the contact hole 4a is formed as described above, since the active region 2 and the field region 1 are exposed together during the etching process, the semiconductor of the interface between the active region 2 and the field region 1 having a weak crystal structure is exposed. The substrate is damaged and damage caused by the damage is transferred to the active region 2 to generate a leakage current during operation of the device. This problem also contributes to the deterioration of the reflash characteristics of memory devices such as DRAM.
도 1c는 도 1b의 A1 - A2 부분을 절취한 상태의 단면도로서, 필드영역(1)과 활성영역(2)으로 구분된 반도체 기판(10)상에 층간절연막(5)이 형성되고, 상기 활성영역(2)과 필드영역(1)의 일부가 노출되도록 상기 층간절연막(5)에 콘택홀(4a)이 형성된 상태로서, 상기 콘택홀(4a)을 형성하기 위한 식각 공정시 활성영역(2)과 필드영역(1)의 계면("X" 부분)이 손상된 상태가 도시된다.FIG. 1C is a cross-sectional view of the portion A1-A2 of FIG. 1B, in which the interlayer insulating film 5 is formed on the semiconductor substrate 10 divided into the field region 1 and the active region 2. A contact hole 4a is formed in the interlayer insulating film 5 so that a portion of the region 2 and the field region 1 are exposed, and the active region 2 during the etching process for forming the contact hole 4a. The state where the interface ("X" portion) of the field region 1 is damaged is shown.
따라서 본 발명은 콘택홀을 형성하기 위한 식각 공정시 필드영역과 활성영역의 계면부에 절연막이 일부 잔류되도록 하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device, which can solve the above-mentioned disadvantages by partially remaining an insulating film at an interface between a field region and an active region during an etching process for forming a contact hole. have.
상기한 목적을 달성하기 위한 본 발명은 필드영역 및 활성영역에 걸쳐 길게 형성되는 라인 형태의 콘택홀 형성 방법에 있어서, 필드영역 및 활성영역을 포함하는 반도체 기판상에 층간절연막을 형성하는 단계와, 소정의 마스크를 이용한 식각 공정으로 층간절연막을 패터닝하여 필드영역 및 활성영역의 반도체 기판이 노출되도록 콘택홀을 형성하되, 필드영역 및 활성영역 계면의 반도체 기판상에 층간절연막의 일부가 잔류되도록 하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a line shape extending over a field region and an active region, the method comprising: forming an interlayer insulating film on a semiconductor substrate including the field region and the active region; Patterning the interlayer insulating film by an etching process using a predetermined mask to form a contact hole to expose the semiconductor substrate in the field region and the active region, and leaving a part of the interlayer insulating layer on the semiconductor substrate at the interface of the field region and the active region Characterized in that comprises a.
또한, 본 발명에 따른 반도체 소자의 콘택홀 형성 방법은 소자분리막 및 웰이 형성된 반도체 기판상에 게이트 전극을 형성한 후 노출된 부분의 반도체 기판에 LDD 영역을 형성하는 단계와, 게이트 전극의 양측벽에 스페이서를 형성한 후 노출된 부분의 반도체 기판에 불순물 이온을 주입하여 LDD 구조의 접합영역을 형성하는 단계와, 전체 상부면에 층간절연막을 형성한 후 표면을 평탄화시키는 단계와, 소정의 마스크를 이용한 식각 공정으로 층간절연막을 패터닝하여 필드영역 및 활성영역의 반도체 기판이 노출되도록 콘택홀을 형성하되, 필드영역 및 활성영역 계면의 반도체 기판상에 층간절연막의 일부가 잔류되도록 하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In addition, the method for forming a contact hole in a semiconductor device according to the present invention comprises forming a gate electrode on a semiconductor substrate on which an isolation layer and a well are formed, and then forming an LDD region on an exposed semiconductor substrate, and forming both side walls of the gate electrode. Forming a junction region of an LDD structure by implanting impurity ions into the exposed semiconductor substrate after forming a spacer in the spacer; forming an interlayer insulating film on the entire upper surface; and then planarizing the surface; And forming a contact hole to expose the semiconductor substrate in the field region and the active region by patterning the interlayer insulating layer using an etching process, wherein a part of the interlayer insulating layer is left on the semiconductor substrate at the interface of the field region and the active region. It is characterized by.
상기 마스크는 이웃하는 세 메모리 셀의 접합영역이 노출되며, 필드영역과 활성영역의 계면부가 다른 부분보다 좁게 이루어진 콘택패턴을 구비한 것을 특징으로 한다.The mask may include a contact pattern in which junction regions of three neighboring memory cells are exposed and the interface portion of the field region and the active region is narrower than the other portions.
도 1a는 종래의 콘택홀 형성용 마스크를 설명하기 위한 평면도.1A is a plan view illustrating a conventional contact hole forming mask.
도 1b는 종래의 방법으로 형성된 콘택홀을 도시한 단면도.1B is a cross-sectional view showing a contact hole formed by a conventional method.
도 1c는 도 1b의 A1 - A2 부분을 절취한 상태를 도시한 단면도.1C is a cross-sectional view illustrating a state in which the portion A1-A2 of FIG. 1B is cut out;
도 2a 내지 도 2e는 본 발명에 따른 콘택홀 형성 방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of devices for explaining a method for forming a contact hole according to the present invention.
도 3a는 본 발명에 사용되는 콘택홀 형성용 마스크를 설명하기 위한 평면도.3A is a plan view for explaining a contact hole forming mask used in the present invention.
도 3b는 본 발명에 따라 형성된 콘택홀을 도시한 단면도.3B is a cross-sectional view illustrating a contact hole formed in accordance with the present invention.
도 3c는 도 3b의 B1 - B2 부분을 절취한 상태를 도시한 단면도.3C is a cross-sectional view illustrating a state in which the portion B1-B2 of FIG. 3B is cut out;
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 및 21: 필드영역2 및 14b: 활성영역1 and 21: field areas 2 and 14b: active area
3 및 12: 게이트4 및 24: 콘택패턴3 and 12: gates 4 and 24: contact pattern
4a 및 18: 콘택홀4b 및 18a: 콘택홀의 상부4a and 18: contact hole 4b and 18a: upper part of contact hole
4c 및 18b: 콘택홀의 하부5 및 17: 층간절연막4c and 18b: lower portions of contact holes 5 and 17: interlayer insulating film
10 및 11: 반도체 기판13: 마스크 패턴10 and 11: semiconductor substrate 13: mask pattern
14: LDD 영역14a: 접합영역14: LDD region 14a: junction region
15: 스페이서16: 식각 방지막15: spacer 16: etching prevention film
19: 플러그19: plug
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도로서, 도 3a 내지 도 3c를 참조하여 설명하면 다음과 같다.2A through 2E are cross-sectional views of devices for describing a method of forming a contact hole in a semiconductor device according to the present invention, which will be described below with reference to FIGS. 3A through 3C.
도 2a는 소자분리막 및 웰이 형성된 반도체 기판(11)상에 게이트 전극용 도전층(12)을 형성하고 마스크 패턴(13)을 이용하여 게이트 전극(12)을 형성한 후 노출된 부분의 반도체 기판(11)에 불순물 이온을 주입하여 LDD 영역(14)을 형성한 상태의 단면도로서, 상기 게이트 전극용 도전층(12)은 도프(Doped) 폴리실리콘 또는 금속으로 형성하거나, 도프 폴리실리콘과 금속이 적층된 구조로 형성하며, 상기 마스크 패턴(13)은 질화막으로 형성한다.FIG. 2A illustrates a semiconductor substrate in an exposed portion after forming a conductive layer 12 for a gate electrode on a semiconductor substrate 11 having a device isolation film and a well formed therein, and forming a gate electrode 12 using a mask pattern 13. A cross-sectional view of a state in which the LDD region 14 is formed by implanting impurity ions into (11), wherein the gate electrode conductive layer 12 is formed of doped polysilicon or metal, or doped polysilicon and metal It is formed in a stacked structure, the mask pattern 13 is formed of a nitride film.
도 2b는 상기 게이트 전극(12) 및 마스크 패턴(13)의 양측벽에 스페이서(15)를 형성한 후 노출된 반도체 기판(11)에 불순물 이온을 주입하여 접합영역(14a)의 형성을 완료한 상태의 단면도로서, 이때, 예를들어, NMOS 트랜지스터용 마스크를 이용한 스페이서 형성 및 이온 주입을 실시한 후 PMOS 트랜지스터용 마스크를 이용한 스페이서 형성 및 이온 주입을 실시한다.2B illustrates that spacers 15 are formed on both sidewalls of the gate electrode 12 and the mask pattern 13, and then impurity ions are implanted into the exposed semiconductor substrate 11 to complete formation of the junction region 14a. As a cross-sectional view of the state, at this time, for example, spacer formation and ion implantation using a mask for an NMOS transistor are performed, followed by spacer formation and ion implantation using a mask for a PMOS transistor.
또한, 상기 스페이서(15)는 질화막과 산화막이 적층된 구조로 형성하며, 주변회로 지역은 산화막 및 질화막을 순차적으로 식각하여 각 게이트 전극(12)의 측벽에 질화막과 산화막으로 이루어진 스페이서(15)가 형성되도록 하고, 셀 지역은 산화막을 제거한 후 질화막을 스페이서 식각하여 각 게이트 전극(12)의 측벽에 질화막으로만 이루어진 스페이서(15)가 형성되도록 하여 콘택홀을 통한 접촉면적이 충분히 확보되도록 한다.In addition, the spacer 15 is formed of a structure in which a nitride film and an oxide film are stacked, and in the peripheral circuit region, an oxide film and a nitride film are sequentially etched so that a spacer 15 made of a nitride film and an oxide film is formed on the sidewall of each gate electrode 12. After the oxide layer is removed, the cell region is etched to form a spacer 15 etched on the sidewall of each gate electrode 12 so that the contact area through the contact hole is sufficiently secured.
도 2c는 전체 상부면에 식각 방지막(16) 및 층간절연막(17)을 순차적으로 형성한 후 예를들어, 화학적 기계적 연마(CMP) 공정으로 상기 층간절연막(17)을 평탄화한 상태의 단면도로서, 상기 식각 방지막(16)은 질화막으로 형성하고, 상기 층간절연막(17)은 BPSG로 형성한다.FIG. 2C is a cross-sectional view of the etch stop layer 16 and the interlayer dielectric layer 17 formed on the entire upper surface thereof sequentially and then planarized, for example, by the chemical mechanical polishing (CMP) process. The etch stop layer 16 is formed of a nitride film, and the interlayer insulating layer 17 is formed of BPSG.
도 2d는 소정의 마스크를 이용하여 상기 식각 방지막(16)이 노출되는 시점까지 상기 층간절연막(17)을 식각하므로써 상기 접합영역(14a)이 노출되도록 콘택홀(18)이 형성된 상태의 단면도인데, 이때, 필드영역과 활성영역의 계면부에 상기 층간절연막(17)이 일부 잔류되도록 하여 필드영역과 활성영역 계면의 반도체 기판(11)이 손상되지 않도록 한다.FIG. 2D is a cross-sectional view of a state in which a contact hole 18 is formed to expose the junction region 14a by etching the interlayer insulating layer 17 until a point where the etch stop layer 16 is exposed using a predetermined mask. At this time, the interlayer insulating film 17 remains partially at the interface portion between the field region and the active region so that the semiconductor substrate 11 at the interface between the field region and the active region is not damaged.
예를들어, 도 3a에 도시된 바와 같이, 이웃하는 세 메모리 셀의 접합영역(14a)이 노출되며, 필드영역(21)과 활성영역(14b)의 계면부가 다른 부분보다 좁게 이루어진 콘택패턴(24)이 형성된 마스크를 사용하므로써 도 3b에 도시된 바와 같이 상기 콘택홀(18)의 하부(18b)는 상기 게이트(12)의 측벽에 형성된 스페이서(15)에 의해 상부(18c)보다 좁게 형성되며, 상기 콘택홀(18) 저면의 반도체 기판(11) 즉, 필드영역(21)과 활성영역(14b) 계면부의 반도체 기판(11)에는 상기 층간절연막(17)이 일부 잔류된다.For example, as shown in FIG. 3A, the contact region 14a of three neighboring memory cells is exposed, and the contact pattern 24 having the interface portion between the field region 21 and the active region 14b is narrower than the other portions. As shown in FIG. 3B, the lower portion 18b of the contact hole 18 is formed to be narrower than the upper portion 18c by the spacer 15 formed on the sidewall of the gate 12. The interlayer insulating layer 17 partially remains in the semiconductor substrate 11 at the bottom of the contact hole 18, that is, the semiconductor substrate 11 at the interface between the field region 21 and the active region 14b.
따라서, 잔류된 층간 절연막(17)에 의해 필드영역(21)과 활성영역(14b) 계면부의 반도체 기판(11)이 노출되지 않기 때문에 상기 식각 과정에서 반도체기판(11)의 손상이 발생되지 않는다.Therefore, since the semiconductor substrate 11 at the interface between the field region 21 and the active region 14b is not exposed by the remaining interlayer insulating layer 17, the semiconductor substrate 11 is not damaged during the etching process.
도 2e는 상기 콘택홀(18)이 매립되도록 전체 상부면에 폴리실리콘을 증착한 후 상기 마스크 패턴(13)이 노출되는 시점까지 상기 폴리실리콘을 평탄화시켜 상기 게이트 전극(12)의 사이에 상기 접합영역(14a)과 접속되는 플러그(19)가 형성되도록 한 상태의 단면도이다.FIG. 2E illustrates that the silicon is planarized by depositing polysilicon on the entire upper surface of the contact hole 18 to be filled and then planarizing the polysilicon until the mask pattern 13 is exposed. It is sectional drawing of the state which made the plug 19 connected with the area | region 14a form.
이후, 전체 상부면에 층간절연막을 형성한 후 패터닝하여 상기 플러그(19)가 노출되도록 콘택홀을 형성하고, 상기 콘택홀을 통해 상기 플러그(19)와 접속되도록 상부 도전층을 형성하는 후속 공정을 진행한다.Subsequently, after forming the interlayer insulating film on the entire upper surface, patterning is performed to form a contact hole so that the plug 19 is exposed, and an upper conductive layer is formed to be connected to the plug 19 through the contact hole. Proceed.
상술한 바와 같이 본 발명은 콘택홀을 형성하기 위한 식각 공정시 필드영역과 활성영역의 계면부에 절연막이 일부 잔류되도록 하므로써 잔류된 절연막에 의해 필드영역과 활성영역 계면부의 반도체 기판이 노출되지 않기 때문에 식각 과정에서 반도체 기판의 손상이 발생되지 않는다. 그러므로 계면부의 식각손상에 따른 접합영역의 피해가 발생되지 않아 소자의 수율 및 신뢰성이 향상되며, 특히 누설전류의 발생이 방지되어 디램과 같은 메모리 소자의 리플래쉬 특성이 향상된다.As described above, the semiconductor substrate of the present invention does not expose the semiconductor substrate at the interface between the field region and the active region by allowing the insulating layer to partially remain at the interface between the field region and the active region during the etching process for forming the contact hole. There is no damage to the semiconductor substrate during the etching process. Therefore, the damage of the junction region due to the etch damage of the interface part is not generated, and the yield and reliability of the device are improved. In particular, the leakage current is prevented, thereby improving the refresh characteristics of the memory device such as DRAM.
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