KR20020052458A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20020052458A KR20020052458A KR1020000081745A KR20000081745A KR20020052458A KR 20020052458 A KR20020052458 A KR 20020052458A KR 1020000081745 A KR1020000081745 A KR 1020000081745A KR 20000081745 A KR20000081745 A KR 20000081745A KR 20020052458 A KR20020052458 A KR 20020052458A
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- Prior art keywords
- insulating film
- forming
- oxide film
- mask
- etching
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000012212 insulator Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 19
- 239000010410 layer Substances 0.000 description 18
- 239000011229 interlayer Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게 에스.오.아이.(silicon on insulator, 이하 SOI라 함)기판에 트랜지스터를 형성하는 공정 시 트랜지스터의 채널 하부에 에어-터널을 형성하여 반도체소자의 동작 특성 및 신뢰성을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form an air-tunnel under a channel of a transistor during a process of forming a transistor on a silicon on insulator (SOI) substrate. The present invention relates to a method of improving the operating characteristics and reliability of a semiconductor device.
일반적으로 SOI 기판을 제조하는 방법은 여러가지 형태가 있으나, 그 중의 하나로 접합에 의한 방법이 있다.In general, there are various methods of manufacturing an SOI substrate, but one of them is a method by bonding.
상기 접합에 의한 방법은 두 장의 웨이퍼를 접합한 후, 후면 연마와 식각을 통해 수 ㎛ 까지 씨닝(thinning) 공정을 진행한 뒤, 최종적으로 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)를 통해 소자 형성을 위한 얇은 실리콘층을 얻는 방법이다(상기 두 장의 웨이퍼 중, 후에 소자를 형성시킬 실리콘층을 제공하는 씨드 웨이퍼(seed wafer)와 이 얇은 실리콘층을 지지해주는 지지 웨이퍼(supporting wafer)라고 칭한다). 여기서, 상기와 같은 CMP공정은 주로 LOCOS(LOCal Oxidation of Silicon) 방법에서 소자분리용으로 사용하는 소자분리절연막을 연마정지층으로 사용하는 방법이 주종을 이루고 있다. 그러나 이러한 방법은 셀 영역(cell region)과 주변회로영역(periphery region)에서의 소자분리절연막의 두께 차이로 인하여 CMP공정 후, 활성영역의 불균일성을 야기하고, 이로 인해 후속 노광 공정에서 초점의 기준을 설정할 수 없게 되어 소자의 형성이 불가능하게 된다.In the bonding method, two wafers are bonded to each other, followed by a thinning process up to several μm through backside polishing and etching, and finally through chemical mechanical polishing (CMP). It is a method of obtaining a thin silicon layer for forming an element (of the two wafers, a seed wafer that provides a silicon layer for forming an element later, and a supporting wafer that supports the thin silicon layer. ). Here, the CMP process as described above mainly consists of using a device isolation insulating film used for device isolation in the LOCOS (LOCal Oxidation of Silicon) method as a polishing stop layer. However, this method causes non-uniformity of the active region after the CMP process due to the difference in the thickness of the device isolation insulating film in the cell region and the peripheral region. It becomes impossible to set, and formation of an element becomes impossible.
반도체소자가 고집적화되고, 상기의 문제점을 해결하기 위하여 얕은 트렌치 소자분리(shallow trench isolation)방법을 사용하게 되었다. 하지만, 계속적인 스케일링(scaling)은 면적을 적게 차지하면서 소자 간의 간섭이 없는 새로운 절연을요구하고 있다.In order to solve the above problems, semiconductor devices have been highly integrated, and shallow trench isolation methods have been used. However, continuous scaling requires less isolation and new isolation without interference between devices.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 고성능의 SOI 소자는 지지웨이퍼와 씨드웨이퍼 간에 산화막이 가로막아 소오스/드레인 간의 내압이 저하되어 펀치 쓰루가 발생하기 쉽다. 이로 인하여 드레인전류는 포화영역에서도 포화되지 않고, 드레인의 전압 증가와 함께 급증한다. 또한, 서브트레쉬홀드 특성도 저하되어 비동작영역에서도 전류가 증가하여 게이트로 동작하는 제어소자로서의 원활한 역할을 기대하기 어려운 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the prior art, a high performance SOI device is likely to cause punch through due to a decrease in the internal pressure between the source and drain due to an oxide film interposed between the support wafer and the seed wafer. As a result, the drain current does not saturate even in the saturation region, but increases rapidly with the increase of the drain voltage. In addition, there is a problem in that the sub-threshold characteristic is also deteriorated, so that the current increases in the non-operational region and thus, it is difficult to expect a smooth role as a control element operating as a gate.
본 발명은 상기한 문제점을 해결하기 위하여, SOI 기판에 트랜지스터를 형성하는 공정에서 지지웨이퍼와 씨드웨이퍼 간의 산화막을 제거하여 에어-터널을 형성함으로써 단채널효과 및 ESD 특성을 개선하여 소자의 동작특성 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems, in the process of forming a transistor on an SOI substrate, an air-tunnel is formed by removing an oxide film between a support wafer and a seed wafer to improve short channel effects and ESD characteristics, thereby improving operation characteristics and It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves reliability.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도.1 to 6 are cross-sectional views of a method of manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 지지웨이퍼 13 : 산화막11 support wafer 13 oxide film
15 : 씨드웨이퍼 17 : 베리어막15: seed wafer 17: barrier film
19 : 소자분리절연막 21 : 게이트절연막19: device isolation insulating film 21: gate insulating film
23 : 게이트전극 25 : 마스크절연막패턴23 gate electrode 25 mask insulating film pattern
27 : LDD영역 29 : 절연막 스페이서27: LDD region 29: insulating film spacer
31 : 홈 33 : 에어-터널31: home 33: air-tunnel
35 : 도전층 37 : 콘택플러그35: conductive layer 37: contact plug
39 : 제1층간절연막 41 : 제2층간절연막39: first interlayer insulating film 41: second interlayer insulating film
43 : 비트라인 콘택플러그43: bit line contact plug
상기 목적을 달성하기 위해 본 발명에 따른 반도체소자의 제조방법은,The semiconductor device manufacturing method according to the present invention to achieve the above object,
지지웨이퍼, 산화막 및 씨드웨이퍼의 적층구조로 이루어지는 SOI 구조의 반도체기판에 활성영역을 정의하는 소자분리절연막을 형성하는 공정과,Forming a device isolation insulating film defining an active region on a semiconductor substrate having an SOI structure comprising a stacked structure of a support wafer, an oxide film and a seed wafer;
상기 SOI 기판 상부에 게이트절연막패턴, 게이트전극 및 마스크절연막패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of a gate insulating film pattern, a gate electrode and a mask insulating film pattern on the SOI substrate;
상기 적층구조 양측 SOI 기판에 LDD영역을 형성하는 공정과,Forming an LDD region on both sides of the stacked structure SOI substrate;
상기 적층구조의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the laminated structure;
상기 마스크절연막패턴과 절연막 스페이서를 식각마스크로 상기 씨드웨이퍼, 산화막 및 지지웨이퍼를 식각하여 소정 두께의 홈을 형성하는 공정과,Etching the seed wafer, the oxide film, and the support wafer by using the mask insulating film pattern and the insulating film spacer as an etching mask to form grooves having a predetermined thickness;
상기 홈에서 노출되는 산화막을 식각하여 에어-터널을 형성하는 공정과,Etching the oxide film exposed from the groove to form an air-tunnel;
전체표면 상부에 도전층을 형성하는 공정과,Forming a conductive layer over the entire surface,
상기 도전층을 식각하여 상기 홈을 매립하는 활성영역과 콘택플러그를 동시에 형성하는 것을 특징으로 한다.The conductive layer may be etched to simultaneously form an active region filling the groove and a contact plug.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6 는 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도이다.1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 지지웨이퍼(11), 산화막(13) 및 씨드웨이퍼(15)의 적층구조로 이루어진 SOI 기판에 소자분리영역으로 예정되는 부분에 트렌치를 형성한다.First, a trench is formed in a portion of the SOI substrate having a stacked structure of the support wafer 11, the oxide film 13, and the seed wafer 15, as a device isolation region.
다음, 트렌치 표면에 에피택셜 실리콘층, 다결정실리콘층 또는 산화막과 식각선택비 차이를 갖는 절연막으로 베리어막(17)을 형성한다. 이때, 상기 베리어막(17)은 후속공정에서 소자분리절연막이 손실되는 것을 방지한다.Next, the barrier film 17 is formed on the trench surface by using an epitaxial silicon layer, a polycrystalline silicon layer, or an insulating film having an etch selectivity difference from the oxide film. In this case, the barrier film 17 prevents the device isolation insulating film from being lost in a subsequent process.
그 다음, 상기 트렌치를 매립하는 제1소자분리절연막(19)을 형성한다. (도 1 참조)Next, a first device isolation insulating film 19 is formed to fill the trench. (See Figure 1)
다음, 전체표면 상부에 게이트절연막, 게이트전극용 도전층 및 마스크절연막의 적층구조를 형성한다.Next, a stacked structure of a gate insulating film, a gate electrode conductive layer and a mask insulating film is formed over the entire surface.
그 다음, 게이트전극을 정의하는 게이트전극 마스크를 식각마스크로 상기 적층구조를 식각하여 게이트절연막패턴(21), 게이트전극(23) 및마스크절연막패턴(25)의 적층구조 패턴을 형성한다.Next, the stacked structure is etched using a gate electrode mask defining an gate electrode as an etch mask to form a stacked structure pattern of the gate insulating film pattern 21, the gate electrode 23, and the mask insulating film pattern 25.
다음, 상기 적층구조 패턴의 양측 씨드웨이퍼(15)에 저농도의 불순물을 이온주입하여 LDD영역(27)을 형성한다. (도 2 참조)Next, the LDD region 27 is formed by ion implanting impurities of low concentration into both seed wafers 15 of the stacked structure pattern. (See Figure 2)
그 다음, 상기 적층구조 패턴의 측벽에 절연막 스페이서(29)를 형성한다.Next, an insulating film spacer 29 is formed on sidewalls of the stacked structure pattern.
다음, 상기 절연막 스페이서(29)와 마스크절연막패턴(25)을 식각마스크로 상기 씨드웨이퍼(15), 산화막(13) 및 지지웨이퍼(11)를 소정 두께 제거하여 홈(31)을 형성한다. 상기 홈(31)은 1000 ∼ 2000Å 깊이로 형성된다.Next, the seed wafer 15, the oxide film 13, and the support wafer 11 are removed from the insulating layer spacer 29 and the mask insulating layer pattern 25 using an etch mask to form a groove 31. The groove 31 is formed to a depth of 1000 ~ 2000Å.
그 다음, 상기 홈(31)을 통해서 노출되는 SOI 기판의 산화막(13)을 제거하여 에어-터널(33)을 형성한다. (도 3 참조)Next, the oxide film 13 of the SOI substrate exposed through the groove 31 is removed to form an air-tunnel 33. (See Figure 3)
다음, 전체표면 상부에 도전층(35)을 형성한다. 이때, 상기 도전층(35)은 다결정실리콘층으로 형성된다. (도 4 참조)Next, the conductive layer 35 is formed on the entire surface. In this case, the conductive layer 35 is formed of a polycrystalline silicon layer. (See Figure 4)
그 다음, 상기 도전층(35)을 전면식각 또는 CMP공정으로 제거하여 활성영역 및 콘택플러그(37)를 형성하되, 상기 전면식각 또는 CMP공정은 상기 마스크절연막패턴(25)을 식각장벽으로 사용한다. 상기 홈(31)에 매립된 상기 도전층(35)은 활성영역으로 된다. (도 5 참조)Next, the conductive layer 35 is removed by an entire surface etching or CMP process to form an active region and a contact plug 37. The entire surface etching or CMP process uses the mask insulating film pattern 25 as an etching barrier. . The conductive layer 35 embedded in the groove 31 becomes an active region. (See Figure 5)
다음, 상기 구조에서 소자분리영역으로 예정되는 부분을 노출시키는 소자분리마스크를 식각마스크로 상기 콘택플러그(37)를 제거한다.Next, the contact plug 37 is removed by using an element isolation mask that exposes a portion of the structure to be an element isolation region as an etch mask.
그 다음, 상기 콘택플러그(37)가 제거된 부분을 절연막으로 매립하여 제2소자분리절연막(39)을 형성한다.Next, the portion where the contact plug 37 is removed is filled with an insulating film to form a second device isolation insulating film 39.
다음, 전체표면 상부에 층간절연막(41)을 형성한다.Next, an interlayer insulating film 41 is formed over the entire surface.
그 다음, 상기 콘택플러그(37)에서 비트라인 콘택으로 예정되는 부분을 노출시키는 비트라인 콘택마스크를 식각마스크로 상기 층간절연막(41)을 식각하여 비트라인 콘택홀을 형성한다.Next, the interlayer insulating layer 41 is etched using a bit line contact mask that exposes a portion of the contact plug 37 to be a bit line contact as an etch mask to form a bit line contact hole.
다음, 상기 비트라인 콘택홀을 매립하는 비트라인 콘택플러그(43)를 형성한다. (도 6 참조)Next, a bit line contact plug 43 filling the bit line contact hole is formed. (See Figure 6)
상기한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, SOI 기판에 트랜지스터를 형성하는 공정 시 상기 SOI기판의 실리콘 사이에 산화막을 제거하여 에어-터널을 형성하여 문턱전압을 개선시키고, 드레인-소오스 간의 내압 증대 및 서브트레쉬홀드 특성을 개선시켜 단채널효과를 개선하는 동시에 ESD 특성도 개선할 수 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, in the process of forming a transistor on an SOI substrate, an oxide film is removed between silicon of the SOI substrate to form an air-tunnel, thereby improving a threshold voltage, and drain-source. Increasing the breakdown voltage and improving the sub-threshold characteristics of the liver improves the short-channel effect and the ESD characteristics.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7265031B2 (en) | 2003-11-27 | 2007-09-04 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces |
| KR100944342B1 (en) * | 2008-03-13 | 2010-03-02 | 주식회사 하이닉스반도체 | Semiconductor having floating body transistor and method for manufacturing thereof |
| KR100967017B1 (en) * | 2008-05-28 | 2010-06-30 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100979362B1 (en) * | 2008-04-24 | 2010-08-31 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
| KR101043665B1 (en) * | 2010-09-08 | 2011-06-24 | 주식회사 엠뱅크 | Break device of wrecker sub axle |
| KR101051810B1 (en) * | 2004-12-30 | 2011-07-25 | 매그나칩 반도체 유한회사 | Cells of Nonvolatile Memory Devices and Manufacturing Method Thereof |
| US8178924B2 (en) | 2007-06-28 | 2012-05-15 | Samsung Electronic Co., Ltd. | Semiconductor device having floating body element and bulk body element |
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| JPH0483361A (en) * | 1990-07-26 | 1992-03-17 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH08274158A (en) * | 1995-03-30 | 1996-10-18 | Toshiba Corp | Manufacture of semiconductor device |
| JP2000031490A (en) * | 1998-07-10 | 2000-01-28 | Sony Corp | Manufacturing semiconductor device |
| JP4362880B2 (en) * | 1998-11-06 | 2009-11-11 | ソニー株式会社 | Crystal growth seed and method for forming the same, silicon layer and method for forming the same, and semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7265031B2 (en) | 2003-11-27 | 2007-09-04 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces |
| US8685805B2 (en) | 2004-08-06 | 2014-04-01 | Samsung Electronics Co., Ltd. | Semiconductor devices with connection patterns |
| KR101051810B1 (en) * | 2004-12-30 | 2011-07-25 | 매그나칩 반도체 유한회사 | Cells of Nonvolatile Memory Devices and Manufacturing Method Thereof |
| US8178924B2 (en) | 2007-06-28 | 2012-05-15 | Samsung Electronic Co., Ltd. | Semiconductor device having floating body element and bulk body element |
| KR100944342B1 (en) * | 2008-03-13 | 2010-03-02 | 주식회사 하이닉스반도체 | Semiconductor having floating body transistor and method for manufacturing thereof |
| KR100979362B1 (en) * | 2008-04-24 | 2010-08-31 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
| US7947541B2 (en) | 2008-04-24 | 2011-05-24 | Hynix Semiconductor Inc. | Method of fabricating a semiconductor device |
| US8193588B2 (en) | 2008-04-24 | 2012-06-05 | Hynix Semiconductor Inc. | Semiconductor device |
| KR100967017B1 (en) * | 2008-05-28 | 2010-06-30 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR101043665B1 (en) * | 2010-09-08 | 2011-06-24 | 주식회사 엠뱅크 | Break device of wrecker sub axle |
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