KR101051810B1 - Cells of Nonvolatile Memory Devices and Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a cell of a nonvolatile memory device and a method of manufacturing the same, which can prevent the reliability of the cell of the memory device from deteriorating due to deterioration of the gate insulating film. A support layer formed to cover the device isolation layer, a cavity formed on the substrate, a floating gate formed on the cavity with both sides supported by the support layer, a dielectric film formed to cover the floating gate, and the floating gate And a control gate formed to cover the dielectric layer so as to overlap the dielectric layer, and a source / drain region formed on the substrate exposed to both sides of the control gate.

Nonvolatile Memory Devices, EEPROMs, Gate Insulators, Cavities

Description

CELL OF NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME             

1A and 1B are cross-sectional views illustrating cells formed by a method of manufacturing a nonvolatile memory device according to the prior art.

2 is a cross-sectional view illustrating a cell of a nonvolatile memory device according to a preferred embodiment of the present invention.

3A and 3B, 4A and 4B, 5A and 5B, 6A and 6B, 7A and 7B are cross-sectional views illustrating a method of manufacturing a cell of a nonvolatile memory device according to a preferred embodiment of the present invention. .

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate

11, 111: device isolation film

12: gate insulating film

13, 114: floating gate                 

14, 116: dielectric film

15, 117: control gate

16, 119: gate electrode

17, 119: spacer

18, 120: source / drain regions

112: support layer

113: sacrificial gate insulating film

115: Cavity

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell of a nonvolatile memory device (NVM) and a method of fabricating the same. In particular, a cell of an electrically erasable programmable read-only memory (EEPROM) device having a gate electrode of a stacked structure and the same It relates to a manufacturing method.

The semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device. Volatile memory devices lose their data when their power supplies are interrupted, such as DRAM (Dynamic Random Access Memory) devices and static RAM (SRAM) devices. Nonvolatile memory devices include memory devices that retain data of the memory devices even when power supply is interrupted, such as EEPROM devices and flash devices.

In general, cells of nonvolatile memory devices such as EEPROM devices and flash memory devices have a stacked gate structure that is advantageous for high integration. The stacked gate structure includes a tunnel oxide film, a floating gate, a dielectric film, and a control gate stacked on a semiconductor substrate.

Program operation in such a nonvolatile memory device is performed by F-N tunneling (Fowler-nordheim tunneling) method and hot electron injection (hot electron injection) method. The F-N tunneling method is a method in which a program operation is performed by applying a high electric field to a gate insulating film to inject electrons into a floating gate from a semiconductor substrate. The hot electron injection method is a method in which a hot electron generated in a channel region near a drain is injected into a floating gate to perform a program operation. Meanwhile, an erase operation of the nonvolatile memory device is performed by releasing electrons injected into the floating gate into the semiconductor substrate or the source through a program operation.

Hereinafter, a cell and a method of manufacturing the nonvolatile memory device according to the prior art will be described with reference to FIGS. 1A and 1B. Here, FIG. 1A is a cross-sectional view cut in the channel length direction, and FIG. 1B is a cross-sectional view cut in the channel width direction.

As shown in FIGS. 1A and 1B, a cell of a conventional nonvolatile memory device includes a gate insulating film 12, a floating gate 13, and a dielectric film on a semiconductor substrate 10 on which an isolation layer 11 is formed. The gate electrode 16 including the 14 and the control gate 15 is formed in a stacked structure, and source / drain regions 18 are formed in the substrate 10 exposed to both sides of the gate electrode 16. Here, '17' is shown as a spacer.

In the cell structure of the conventional nonvolatile memory device described above, the characteristics of the gate insulating layer 12 play an important role in determining the reliability of the device. Accordingly, degradation due to voltage, current, and use time of the gate insulating layer 12 should be minimized. However, since the reliability of the gate insulating film 12 is inherently a unique property of the material, it cannot be completely removed, and enormous development time and cost are required to secure the reliability of the device.

Factors that determine the reliability of the gate insulating film 12 are charge to breakdown (Qbd) and hole trap charge of oxide breakdown (Qb). These factors represent the breakdown characteristics of the external electric field of all materials consisting of atoms and molecules, and include inherent properties that exist even in the case of defect free materials. Therefore, in the nonvolatile memory device using the FN tunneling characteristic, most of the current component is occupied by the current flowing through the gate insulating layer 12. As a result, the reliability of the nonvolatile memory device will be determined by the reliability of the gate insulating film 12.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and a cell of a nonvolatile memory device and a method of manufacturing the same, which can prevent the reliability of the cell of the memory device from deteriorating due to deterioration of the gate insulating film. The purpose is to provide.

According to an aspect of the present invention, there is provided a substrate on which an isolation layer is formed, a support layer formed to cover the isolation layer, a cavity formed on the substrate, and both sides of the substrate being supported by the support layer. A floating gate formed on the cavity, a dielectric film formed to cover the floating gate, a control gate formed to cover the dielectric film so as to overlap the floating gate, and a source formed on the substrate exposed to both sides of the control gate. A cell of a nonvolatile memory device including a drain region is provided.

According to another aspect of the present invention, there is provided a substrate on which an isolation layer is formed, forming a support layer to cover an upper portion of the isolation layer, and a sacrificial gate in an active region between the support layers. Depositing an insulating film, forming a floating gate on the sacrificial gate insulating film so that both sides are supported by the support layer, and removing the sacrificial gate insulating film to form a cavity between the floating gate and the substrate; And sequentially depositing a dielectric film and a control gate to cover the floating gate, and forming a source / drain region on the substrate exposed to both sides of the control gate. to provide.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

2 is a cross-sectional view illustrating a cell of a nonvolatile memory device according to a preferred embodiment of the present invention.

Referring to FIG. 2, a cell of a nonvolatile memory device according to a preferred embodiment of the present invention is gated on a semiconductor substrate 110 defined as an active region and a field region through a device isolation layer 111. A cavity 115 serving as an insulating film, a floating gate 114 formed on the cavity 115, a dielectric film 116 formed to cover the floating gate 114, and a dielectric film 116. And a gate electrode 118 formed of a control gate 117 formed to cover. In addition, the source / drain regions 120 are formed on the substrate 110 exposed to both sides of the gate electrode 118. Here, the cavity 115 is sealed between the floating gate 114 and the substrate 110 by the dielectric film 116. Also, '119', which is not described, is a spacer.

A cell according to a preferred embodiment of the present invention having such a structure forms a gate insulating film as a cavity 115. Accordingly, the program operation is not performed in the cell of the prior art by using the F-N tunneling scheme, but by using the compton effect. On the other hand, the Compton effect is a technique known by those skilled in the art, and a detailed description thereof will be omitted herein.

As is well known, using the Compton effect in a program operation can lower the bias voltage than using the F-N tunneling scheme. Accordingly, when the preferred embodiment of the present invention is applied, the device can be driven at a low voltage, and the reliability deterioration due to the deterioration of the gate insulating film due to the bias voltage, the current, the repeated use, and the use time can be prevented.

For example, when performing a program operation using FN tunneling as in the prior art, approximately 16 V should be applied to the control gate. However, in the case of a cell formed through a preferred embodiment of the present invention, the electron affinity is 4.05. If the voltage of the floating gate corresponding to the eV, the cell can be programmed. Therefore, assuming that the coupling ratio of the dielectric film is 80%, the bias voltage applied to the control gate is about 5V. Therefore, when the cell of the nonvolatile memory device proposed in the present invention is mounted on a mobile low power product, battery life may be greatly increased.

Hereinafter, with reference to Figures 3a and 3b, 4a and 4b, 5a and 5b, 6a and 6b, 7a and 7b non-volatile according to the preferred embodiment of the present invention shown in Figure 2 A cell manufacturing method of a memory device will be described. 3A, 4A, 5A, 6A, and 7A are cross-sectional views cut along the channel length direction, and FIGS. 3B, 4B, 5B, 6B, and 7B are channel widths. It is sectional drawing cut in the (channel width) direction.

3A and 3B, a shallow trench isolation (STI) process is performed to form an isolation layer 111 that defines an active region and a field region. In this case, the device isolation layer 111 is formed of a high density plasma (HDP) oxide film.

Subsequently, a well ion implantation process using a screen oxide film and an ion implantation process for adjusting the threshold voltage are sequentially performed to form a well region (not shown) in a predetermined region inside the semiconductor substrate 110.

Next, the support layer 112 is formed to cover the upper portion of the device isolation layer 111. In this case, the support layer 112 may be formed in a hat shape by depositing an insulating film on the entire structure and then performing a photolithography process. On the other hand, the support layer 12 is formed using a nitride film-based material.

Subsequently, as shown in FIGS. 4A and 4B, the sacrificial gate insulating layer 113 is formed in the active region between the support layers 112. In this case, the sacrificial gate insulating layer 113 may be formed by an oxidation process or a deposition process using an oxide-based material, or may be formed by combining an oxidation process and a deposition process.

Subsequently, a floating gate conductive film 114 (hereinafter referred to as a first conductive film) is deposited on the sacrificial gate insulating film 113. In this case, the first conductive film 114 is formed of a polysilicon film. For example, the polysilicon film is formed of an undoped or doped silicon film. In the case of undoped, Si ₂ H ₆ gas is deposited by LPCVD (Low Pressure Chemical Vapor Deposition) method, and in the case of dope (P type), Si ₂ H ₆ and PH ₃ are deposited by LPCVD method.

Subsequently, after the photoresist is applied onto the first conductive film 114, an exposure and development process using a photomask is sequentially performed to form a photoresist pattern (not shown).

Subsequently, the floating gate 114 is defined by etching the first conductive layer 114 and the sacrificial gate insulating layer 113 by performing an anisotropic dry etching process using the photoresist pattern.

Subsequently, as shown in FIGS. 5A and 5B, a photoresist pattern (not shown) in which only a cell region is opened is formed. At this time, the region (not shown) in which the MOSFET gate electrode is formed is closed.

Subsequently, an isotropic wet etching process using the photoresist pattern is performed to remove the sacrificial gate insulating layer 113 (see FIGS. 4A and 4B). As a result, the cavity 115 is formed in the portion where the sacrificial gate insulating layer 113 is removed. The reason why the sacrificial gate insulating layer 113 can be removed through the isotropic wet etching process is that both sides of the floating gate 114 are formed to span the support layer 112 in the channel width direction as shown in FIG. 5B. This is because the etching solution penetrates 113 and the first conductive layer 114 and the substrate 110 function as an etch stop layer during the wet etching process. That is, the sacrificial gate insulating layer 113 interposed between the floating gate 114 and the substrate 110 may be selectively removed. In this case, the cavity 115 may be an air layer or a vacuum layer.

Subsequently, a strip process is performed to remove the photoresist pattern.

Subsequently, in order to remove residues and / or natural oxide layers remaining in the wet etching process, a cleaning process using a dilute HF (DHF) or a buffer oxide etchant (BOE) solution may be performed.

Subsequently, a thermal oxidation process using a weak acid may be performed to compensate for the substrate 110 and the floating gate 114 that are exposed and damaged during the wet etching process to improve the interface characteristics.

6A and 6B, a dielectric film 116 is formed over the entire structure to cover the floating gate 114. In this case, the dielectric film 116 improves the coupling ratio by using a nitride film having a higher dielectric constant than the oxide film. In addition, a material having a relatively poor step coverage characteristic is used so that the cavity 115 is not filled by the dielectric film 116 serving as the gate insulating film of the control gate 117. In addition, the deposition thickness is appropriately adjusted in consideration of the magnitude of the voltage applied to the control gate 117. For example, the dielectric film 116 may be formed in a structure of NO (Nitride / Oxide) or ONO (Oxide / Nitride / Oxide). In the case of the ONO structure, the oxide layer, which is the lowermost layer, is formed by an oxidation process, and the nitride layer, which is the middle layer, and the oxide layer, which is the uppermost layer, are formed through a deposition process.

Subsequently, a control gate conductive film 117 (hereinafter referred to as a second conductive film) is deposited on the dielectric film 116. At this time, the second conductive film 117 is formed of a polysilicon film. For example, the polysilicon film is formed of an undoped or doped silicon film. In the case of undoped, Si ₂ H ₆ gas is deposited by LPCVD method, and in the case of dope (P type), Si ₂ H ₆ and PH ₃ are deposited by LPCVD method.

Subsequently, as shown in FIGS. 7A and 7B, after the photoresist is applied on the second conductive layer 117, an exposure and development process using a photo mask is sequentially performed to form a photoresist pattern (not shown). do.

Subsequently, an etching process using the photoresist pattern is performed to etch the second conductive layer 117 and the dielectric layer 116. Thus, the control gate 117 is defined. Thus, a gate electrode 118 composed of the cabbage 115, the floating gate 114, the dielectric film 116, and the control gate 117 is formed.

Meanwhile, the control gate 117 may be etched using a hard mask scheme. In addition, the control gate 117 etching process may be performed in a blanket manner instead of the photolithography process so as to overlap the sidewall of the floating gate 114.

Subsequently, a strip process is performed to remove the photoresist pattern.

Next, an LDD (Lightly Doped Drain) ion implantation process or a Doubled Diffused Drain (DDD) ion implantation process is performed to form an LDD region or a DDD region on the substrate 110 exposed to both sides of the gate electrode 118.                     

Subsequently, spacers 119 (see FIG. 2) are formed on both side walls of the gate electrode 118.

Subsequently, a source / drain ion implantation process is performed to form a source / drain region 120 (see FIG. 2) on the substrate 110 exposed to both sides of the spacer 119.

Next, although not shown, a salicide process may be performed to form a TiSi ₂ layer or a CoSi ₂ layer on the gate electrode 118 and on the source / drain region 120.

Subsequently, a metal wiring process is performed through a general process to form metal wiring (not shown).

The cell of the nonvolatile memory device according to the preferred embodiment of the present invention described above may be applied to a system on chip (SoC).

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a gate insulating film according to voltage, current, and usage time is formed by forming a cabbage with the gate insulating film of the floating gate electrode, and performing a program operation using the Compton effect instead of the FN tunneling method. The deterioration of the device due to deterioration of the device can be prevented at the source, thereby improving the disturbance characteristics, retention characteristics, and endurance characteristics. In addition, a low voltage driving device may be implemented by performing a program operation using the Compton effect.

Claims (10)

A substrate on which an isolation layer is formed; A support layer formed to cover the device isolation layer; A cavity formed on the substrate; A floating gate formed at both sides of the support layer by being supported on the support layer; A dielectric film formed to cover the floating gate; A control gate formed to cover the dielectric layer so as to overlap the floating gate; And Source / drain regions formed in the substrate exposed to both sides of the control gate; A cell of a nonvolatile memory device comprising a. The method of claim 1, The cavity of the cell of the non-volatile memory device consisting of an air layer or a vacuum layer. The method of claim 1, And wherein the cavity is sealed between the floating gate and the substrate by the dielectric film. The method of claim 1, Both sides of the dielectric layer contact the substrate. Providing a substrate on which an isolation layer is formed; Forming a support layer to cover an upper portion of the device isolation layer; Depositing a sacrificial gate insulating film in an active region between the support layers; Forming a floating gate on the sacrificial gate insulating layer so that both sides thereof are supported by the support layer; Removing the sacrificial gate insulating film to form a cavity between the floating gate and the substrate; Sequentially depositing a dielectric film and a control gate to cover the floating gate; And Forming a source / drain region in the substrate exposed to both sides of the control gate; Cell manufacturing method of a nonvolatile memory device comprising a. The method of claim 5, The cavity is a cell manufacturing method of a nonvolatile memory device consisting of an air layer or a vacuum layer. The method of claim 5, The support layer is a cell manufacturing method of a nonvolatile memory device formed of a nitride film. The method of claim 5, The cavity is a cell manufacturing method of a nonvolatile memory device formed by a wet etching process. The method of claim 8, In the wet etching process, the sacrificial gate insulating layer and the substrate and the floating gate may have high etching selectivity to selectively remove the sacrificial gate insulating layer. The method of claim 5, And forming a cavity to further perform a thermal oxidation process with a weak acid.

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